BB_Player_High_Level_characteristics.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
<title>BB Player High-level characteristics</title>
</head>
<body>
<h1>BB Player High Level Information</h1>
This document is intended as a summary of the main characteristics/targets
for the BB SoC and system. For details refer to the <a href="http://therouter.routefree.com/bb/rf/doc/hw/index.html">
hardware documentation</a>
<a href="http://therouter.routefree.com/bb/rf/doc/hw/index.html">.<br>
</a>
<br>
<h3>BB SoC Area Estimate (NEC 0.25u process, UC2)</h3>
<br>
<table cellpadding="2" cellspacing="2" border="1" width="100%">
<tbody>
<tr>
<td valign="Top"><b>Item</b><br>
</td>
<td valign="Top"><b>Area (mm^2)</b><br>
</td>
</tr>
<tr>
<td valign="Top">BCP (Includes, SI, PI, AI, VI, RSP, RDP, USB, RI,
MI), without SRAMs (with SRAMS, without the PAD Ring it is 72.38 mm^2, so
this is a conservative number)<br>
</td>
<td valign="Top">40<br>
</td>
</tr>
<tr>
<td valign="Top">R4300 Core CPU, includes 8 kbyte dcache and 16 kbyte
icache<br>
</td>
<td valign="Top">20<br>
</td>
</tr>
<tr>
<td valign="Top">Internal single ported secure SRAM, 32 Kbyte, 64
bits x 4096 words<br>
</td>
<td valign="Top">4<br>
</td>
</tr>
<tr>
<td valign="Top">Internal SRAM, IMEM, DMEM, TMEM, dual ported, 4kbytes,
64 bits x 512 words x 3<br>
</td>
<td valign="Top">3<br>
</td>
</tr>
<tr>
<td valign="Top">Internal SRAM: there is another block of memory in
the layout, could be VI line or Memspan<br>
</td>
<td valign="Top">1<br>
</td>
</tr>
<tr>
<td valign="Top">Internal Flash (64 Kbyte)<br>
</td>
<td valign="Top">4<br>
</td>
</tr>
<tr>
<td valign="Top"><b>Sub-total</b><br>
</td>
<td valign="Top">72 (= 8.5 * 8.5)<br>
</td>
</tr>
<tr>
<td valign="Top">Pad ring, 0.5 mm on all sides<br>
</td>
<td valign="Top">9 * 9<br>
</td>
</tr>
<tr>
<td valign="Top"><b>Total</b><br>
</td>
<td valign="Top">81<br>
</td>
</tr>
</tbody>
</table>
<br>
<br>
<h3>BB SoC Power Estimate</h3>
Power estimates are derived from known (at least roughtly) RCP estimates
and scaling for voltage and frequency. Since power is dominated by switching,
it is linear in frequency and proportional to the square of the voltage.<br>
<br>
Original RCP: 62.5 MHz core, 250 MHz RDRAM, 0.35u process, 3.3 Volts. Power
consumption: 3 Watts<br>
BCP: 93.75 MHz core, 187.5 MHz DDR, 0.25u process, 2.5 Volts. Estimated
power consumption: 2.6 Watts<br>
R4300 CPU core: power consumption, from NEC estimates of 0.25u core: 1 Watt
at 100 MHz<br>
R4300 CPU core: 140.625, estimated, 1.4 Watts<br>
<br>
Total BB SoC (assuming we run CPU at 140.625 MHz): 4 Watts<br>
<br>
We can probably subtract something from these since it includes RDRAM, which
used a lot of power.<br>
<h3>BB System Power Estimate</h3>
Add DDR power consumption (Doug?)<br>
Others are minor.<br>
<h3>BB Player System COGS</h3>
<br>
<table cellpadding="2" cellspacing="2" border="1" width="100%">
<tbody>
<tr>
<td valign="Top"><b>Item/Description</b><b><br>
</b></td>
<td valign="Top"><b>Supplier(s)</b><b><br>
</b></td>
<td valign="Top"><b>Cost</b><br>
</td>
</tr>
<tr>
<td valign="Top">BB SoC, 0.25u, 100 mm squared, 208 pin PQFP (4 watts
possible?)<br>
</td>
<td valign="Top">NEC<br>
</td>
<td valign="Top">$6.00<br>
</td>
</tr>
<tr>
<td valign="Top">BB Memory module, includes 1x8MB Nand flash on board,
1 multi-color LED for status, 2 expansion slots for additional card (these
are smart-media like, but with mechanical changes so they are not directly
compatible with existing smart-media)<br>
</td>
<td valign="Top">For Nand flash, Toshiba, Samsung, etc<br>
</td>
<td valign="Top">$10.00<br>
</td>
</tr>
<tr>
<td valign="Top">16 MByte (128 mbit) x 32 DDR<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$5.00<br>
</td>
</tr>
<tr>
<td valign="Top">Integrated A/V DAC, as used on N64. <br>
</td>
<td valign="Top">Ricoh<br>
</td>
<td valign="Top">$1.60<br>
</td>
</tr>
<tr>
<td valign="Top">Audio Amplifier<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$0.60<br>
</td>
</tr>
<tr>
<td valign="Top">Clock generators/crystals. Current plan is to have
separate clocks for System and Video, since this allows a form of random number
generation on chip. All other internal clocks will be synthesized from the
system clock. <br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$1.00<br>
</td>
</tr>
<tr>
<td valign="Top">Regulators/On-board switcher. Two voltages: 3.3,
2.5 volt for BB SoC. 5 V is required for USB (double check power requirements).<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$3.00<br>
</td>
</tr>
<tr>
<td valign="Top">Passive/Active components: caps, zeners for USB,
pull-ups, etc<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top"><br>
</td>
</tr>
<tr>
<td valign="Top">Plastic Case and Buttons<br>
</td>
<td valign="Top">Foxcon?<br>
</td>
<td valign="Top">$2.00<br>
</td>
</tr>
<tr>
<td valign="Top">PCB, 4 layer<br>
</td>
<td valign="Top">Foxcon?<br>
</td>
<td valign="Top">$2.00<br>
</td>
</tr>
<tr>
<td valign="Top">Power supply, 5V wall plug, 1-2A<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$2.00<br>
</td>
</tr>
<tr>
<td valign="Top">Basic Cable: 1 composite video, 2 audio, power and
ground (5 total), 10 ft long<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$1.00<br>
</td>
</tr>
<tr>
<td valign="Top">Transformation cost (assume ~2% of total parts cost)<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$0.80<br>
</td>
</tr>
<tr>
<td valign="Top">Total cost<br>
</td>
<td valign="Top"><br>
</td>
<td valign="Top">$34.00<br>
</td>
</tr>
</tbody>
</table>
<br>
</body>
</html>