ewattadder.v 2.57 KB
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: ewattadder.v,v 1.2 2002/11/22 00:34:20 rws Exp $

   /////////////////////////////////////////////////////////////////////////
   //
   // Project Reality
   //
   // module:      ewattadders
   // description: two 16-bit adders to compute attributes at triangle
   // 	       	   edge.
   //
   // designer:    Mike M. Cai   6/18/94
   //
   /////////////////////////////////////////////////////////////////////////

module ewattadder(wa_data, 
      	       	  in_att, in_dade,
		  cs_ew_data,
		  add32b, add_clear, ld_a, 
      	       	  ew_stall_attr, clk, start_gclk);
output [31:0]  wa_data;	      	 // data write to Attribute port of RF
input [31:0]   in_att, in_dade;
input [31:0]   cs_ew_data;
input 	       add32b, add_clear;
input 	       ld_a;
input 	       ew_stall_attr, clk, start_gclk;

wire [31:0]    sum;
wire  	       msbcarryin, lsbcarryin;
wire  	       msbcarryout, lsbcarryout;
reg   	       msbcarryout_s, lsbcarryout_s;
reg [31:0]     sum_att;
wire [31:0]    sum_att_delay;
wire [31:0]    wa_data;


adder16bi    addermsb(.sum(sum[31:16]), .co(msbcarryout), .a(in_att[31:16]),
      	       	     .b(in_dade[31:16]), .ci(msbcarryin)),
	    adderlsb(.sum(sum[15:0]), .co(lsbcarryout), .a(in_att[15:0]),
	       	     .b(in_dade[15:0]), .ci(lsbcarryin));

always @(posedge clk)
   if (start_gclk) begin
      msbcarryout_s <= ew_stall_attr ? msbcarryout_s : msbcarryout;
      lsbcarryout_s <= ew_stall_attr ? lsbcarryout_s : lsbcarryout; 
      sum_att <= ew_stall_attr ? sum_att : sum;
   end

ewrfdelay delaywdata(.out_data(sum_att_delay), .in_data(sum_att));

assign  
   wa_data = ld_a ? cs_ew_data : sum_att_delay,
   msbcarryin = add32b ? lsbcarryout: (msbcarryout_s & ~add_clear),
   lsbcarryin = lsbcarryout_s & ~add_clear;
   
endmodule  //  ewattadder