/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: ewshuffle.v,v 1.2 2002/11/22 00:34:20 rws Exp $

   /////////////////////////////////////////////////////////////////////////
   //
   // Project Reality
   //
   // module:      ewshuffle
   // description: Shuffles the attributes so that both integer and
   // 	       	   fraction part of an attribute is a one 32-bit word.
   //
   // designer:    Mike M. Cai   6/18/94
   //
   /////////////////////////////////////////////////////////////////////////

module ewshuffle( att_out, dade_out, att_in, dade_in, 
      	       	  shuffle, noshuffle, clk, start_gclk);
output [22:0]   att_out, dade_out;
input [31:0]   att_in, dade_in;
input 	       shuffle, // 0 selects first shuffled data, 1 selects second;
      	       noshuffle; // 0 selects shuffled data, 1 not shuffled.
input 	       clk, start_gclk; // ew_stall_attr;

reg   [15:0]   inta_1delay, fraca_1delay, fraca_2delay; // attribute shuffle
wire  [15:0]   inta_shuffle, fraca_shuffle;

reg   [15:0]   intd_1delay, fracd_1delay, fracd_2delay; // da/de shuffle
wire  [15:0]   intd_shuffle, fracd_shuffle;

wire [31:0]    att_out_m, dade_out_m;
reg [22:0]     att_out_s, att_out;
reg [22:0]     dade_out_s, dade_out;
always @(posedge clk)
   if (start_gclk) begin
      // attribute
//      inta_1delay <= ew_stall_attr ? inta_1delay : att_in[31:16];
      inta_1delay <=  att_in[31:16];
      fraca_1delay <= att_in[15:0];
      fraca_2delay <= fraca_1delay ;
      // da/de
      intd_1delay <=  dade_in[31:16];
      fracd_1delay <= dade_in[15:0];
      fracd_2delay <= fracd_1delay ;
   end 

assign  // attribute
   inta_shuffle = shuffle ? fraca_1delay : att_in[31:16],
   fraca_shuffle = shuffle ? fraca_2delay : inta_1delay,
   att_out_m[31:16]  = noshuffle ? inta_1delay : inta_shuffle,
   att_out_m[15:0]  = noshuffle ? fraca_1delay : fraca_shuffle;
assign  // da/de
   intd_shuffle = shuffle ? fracd_1delay : dade_in[31:16],
   fracd_shuffle = shuffle ? fracd_2delay : intd_1delay,
   dade_out_m[31:16]  = noshuffle ? intd_1delay : intd_shuffle,
   dade_out_m[15:0]  = noshuffle ? fracd_1delay : fracd_shuffle;

// added two pipeline stages since da/dy's are not ready before these
// two stages
always @(posedge clk)
   if (start_gclk) begin
      att_out_s <= att_out_m[31:9];
      att_out   <= att_out_s;
      dade_out_s <= dade_out_m[31:9];
      dade_out <= dade_out_s;
   end

endmodule  //  ewshuffle