ewx.v 3.2 KB
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: ewx.v,v 1.2 2002/11/22 00:34:20 rws Exp $
   /////////////////////////////////////////////////////////////////////////
   //
   // Project Reality
   //
   // module:      ewx
   // description: Computes xh0, xh1, xh2, xh3, xm0, xm1, xm2, xm3
   // 	       	   for each span in a triagle or ractagle.
   //
   // designer:    Mike M. Cai  6/17/94
   //
   /////////////////////////////////////////////////////////////////////////

module ewx( x, x_sticky, edge_cross,
      	    cs_ew_d, ld_xmh, switch_xl, 
      	    ld_dxmdy, ld_dxldy, ld_dxhdy,
	    left_xmajor, cmp_cross_valid,
	    clk, start_gclk);
output [19:0]  x;
output 	       x_sticky;
output	       edge_cross;
input [63:0]   cs_ew_d;
input 	       ld_xmh, switch_xl;
input 	       ld_dxmdy, ld_dxldy, ld_dxhdy;
      	       // ld_xm, ld_xl, ld_xh;
input 	       left_xmajor, cmp_cross_valid;
input 	       clk, start_gclk;

wire [26:0]    dxmdy_m, dxhdy_m;  // 27 bits = s11.15
reg [26:0]     dxmdy_s, dxldy_s, dxhdy_s;
wire [26:0]    xm_m, xh_m;
reg [26:0]     xm_s, xl_s, xh_s;
wire [26:0]     xh_mm;
reg   	       x_sticky;
wire [26:0]    sum;
/* edge crossing variables */
wire [13:0]    cross_a, cross_b;
wire   	       edge_cross_m, edge_cross;
reg   	       edge_cross_s;

assign  
   dxmdy_m = ld_xmh ? cs_ew_d[29:3] : dxhdy_s, // right shifted by two
   dxhdy_m = switch_xl ? dxldy_s : dxmdy_s;
   
assign  
   xm_m = ld_xmh ? cs_ew_d[59:33] : sum,
   xh_m = switch_xl ? xl_s : xm_s;

adder27bi addit (.sum(sum), .a(xh_s), .b(dxhdy_s));

always @(posedge clk)
   if (start_gclk) begin
      dxmdy_s <= ld_dxmdy ? dxmdy_m : dxmdy_s;
      dxldy_s <= ld_dxldy ? cs_ew_d[29:3] : dxldy_s; // dxdy = dxdy / 4;
      dxhdy_s <= ld_dxhdy ? dxhdy_m : dxhdy_s;
      xm_s <= ld_dxmdy ? xm_m : xm_s;
      xl_s <= ld_dxldy ? cs_ew_d[59:33] : xl_s;
//      xh_mm = ld_dxhdy ? xh_m : xh_s;
      xh_s <= xh_mm;
      x_sticky <= |xh_mm[12:0];
   end
assign  xh_mm = ld_dxhdy ? xh_m : xh_s;
assign  x = xh_s[26:7];

/*  Detect triangle edge crossing */
assign cross_a = left_xmajor ? xh_mm[26:13] : xh_s[26:13];
assign cross_b = left_xmajor ? xh_s[26:13] : xh_mm[26:13];
assign edge_cross_m = {~cross_a[13], cross_a[12:0]} < {~cross_b[13], cross_b[12:0]};
always @(posedge clk)
  if (start_gclk) begin
      edge_cross_s <= cmp_cross_valid ? edge_cross_m : edge_cross_s;
  end
assign  edge_cross = cmp_cross_valid ? edge_cross_m : edge_cross_s;

endmodule  //  ewx