ls.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ls.v,v 1.3 2002/11/17 19:55:47 berndt Exp $
// ls.v rsp load/store unit
// The RSP is big-endian.
// Alignment of unaligned data is implemented with a two-stage rotator.
// The first stage takes the 16 bytes of raw dmem output and rotates it
// right by 0 to 3 words. (1 word = 4 bytes) The second stage rotates
// the output of the first stage by 0 to 3 bytes right.
// The scalar unit communicates with bits <127:96> of the data bus.
`timescale 1ns / 10ps
module ls(clk, reset_l, halt, rd_base, ls_drive_rd_base,
rd_offset, rd_elem_num,
address, df_ls_drive_ls_in_wb, df_pass_thru,
su_ex_store, su_ex_load, vu_ex_store, vu_ex_load,
ex_mtc2, ex_mfc2, ex_cfc2, cp0_write, ex_mfc0, pc,
vu_rd_ld_dec_k, vu_rd_st_dec_k,
vu_bwe, chip_sel, df_datain, df_wen_l, df_chip_sel_l,
df_addr_low, df_addr_high, debug_df_dma_rd_to_dm,
dmem_dataout, ex_su_byte_ls, ex_su_half_ls, ex_su_uns_ls,
ex_dma_rd_to_dm, ex_dma_dm_to_rd, dma_wen, mem_write_data,
dma_address, dmem_rd_data,
ls_data, ls_ls_data, cp0_din, cp0_dout);
input clk;
input reset_l;
input halt;
input [3:0] rd_base;
input ls_drive_rd_base;
input [3:0] rd_offset;
input [3:0] rd_elem_num;
input [11:0] address; // byte address
input df_ls_drive_ls_in_wb;
input df_pass_thru;
input su_ex_store;
input su_ex_load;
input vu_ex_store;
input vu_ex_load;
input ex_mtc2;
input ex_mfc2;
input ex_cfc2;
input cp0_write;
input [11:0] vu_rd_ld_dec_k; // RD stage
input [11:0] vu_rd_st_dec_k; // RD stage
input chip_sel; // from suctl, active high
input ex_su_byte_ls;
input ex_su_half_ls;
input ex_su_uns_ls;
input ex_dma_rd_to_dm;
input ex_dma_dm_to_rd;
input [3:0] dma_wen;
input [11:3] dma_address;
input [127:0] dmem_dataout;
input [63:0] mem_write_data;
input ex_mfc0;
input [11:2] pc;
output [15:0] vu_bwe;
output df_chip_sel_l; // chip select, active low
output [15:0] df_wen_l;
output [11:0] df_addr_low;
output [11:0] df_addr_high;
output [63:0] dmem_rd_data;
output [127:0] df_datain;
output debug_df_dma_rd_to_dm; // for debug only
input [127:0] ls_data;
output [127:0] ls_ls_data;
input [31:0] cp0_din;
output [31:0] cp0_dout;
wire ex_dma_wen_noswap;
wire ex_dma_wen_swap;
wire [3:0] ex_rot;
wire [3:0] wb_rot;
wire wb_su_uns_ls;
wire wb_su_load;
wire wb_pass_thru;
wire wb_mfc2;
wire wb_cfc2;
wire ls_drive_ls;
wire wb_dma_dm_to_rd;
wire [11:0] vu_ex_st_dec;
wire [9:6] vu_wb_ld_dec;
lsdp lsdp (
.clk (clk),
.reset_l (reset_l),
.halt (halt),
.pc (pc),
.ls_data (ls_data),
.ls_ls_data (ls_ls_data),
.ex_mfc0 (ex_mfc0), // used to enable cbus drivers
.df_datain (df_datain),
.dmem_dataout (dmem_dataout),
.ex_su_byte_ls (ex_su_byte_ls),
.ex_su_half_ls (ex_su_half_ls),
.cp0_write (cp0_write),
.cp0_data (cp0_din),
.cp0_data_out (cp0_dout),
.ex_dma_wen_noswap (ex_dma_wen_noswap),
.ex_dma_wen_swap (ex_dma_wen_swap),
.vu_ex_st_dec (vu_ex_st_dec),
.ex_rot (ex_rot),
.wb_rot (wb_rot),
.wb_su_load (wb_su_load),
.wb_su_uns_ls (wb_su_uns_ls),
.wb_pass_thru (wb_pass_thru),
.wb_mfc2 (wb_mfc2),
.wb_cfc2 (wb_cfc2),
.ls_drive_ls (ls_drive_ls),
.wb_dma_dm_to_rd (wb_dma_dm_to_rd),
.vu_wb_ld_dec (vu_wb_ld_dec),
.mem_write_data (mem_write_data),
.dmem_rd_data (dmem_rd_data)
);
lsctl lsctl (
.clk (clk),
.reset_l (reset_l),
.address (address),
.rd_base (rd_base),
.ls_drive_rd_base (ls_drive_rd_base),
.ls_base (ls_data[99:96]),
.rd_offset (rd_offset),
.rd_elem_num (rd_elem_num),
.df_ls_drive_ls_in_wb (df_ls_drive_ls_in_wb),
.df_pass_thru (df_pass_thru),
.su_ex_store (su_ex_store),
.su_ex_load (su_ex_load),
.vu_ex_store (vu_ex_store),
.vu_ex_load (vu_ex_load),
.ex_mtc2 (ex_mtc2),
.ex_mfc2 (ex_mfc2),
.ex_cfc2 (ex_cfc2),
.vu_rd_ld_dec_k (vu_rd_ld_dec_k),
.vu_rd_st_dec_k (vu_rd_st_dec_k),
.vu_ex_st_dec (vu_ex_st_dec),
.ex_dma_wen_noswap (ex_dma_wen_noswap),
.ex_dma_wen_swap (ex_dma_wen_swap),
.vu_wb_ld_dec (vu_wb_ld_dec),
.vu_bwe (vu_bwe),
.chip_sel (chip_sel),
.df_wen_l (df_wen_l),
.df_chip_sel_l (df_chip_sel_l),
.df_addr_low (df_addr_low),
.df_addr_high (df_addr_high),
.debug_df_dma_rd_to_dm (debug_df_dma_rd_to_dm),
.ex_su_byte_ls (ex_su_byte_ls),
.ex_su_half_ls (ex_su_half_ls),
.ex_su_uns_ls (ex_su_uns_ls),
.dma_address (dma_address),
.dma_wen (dma_wen),
.ex_dma_rd_to_dm (ex_dma_rd_to_dm),
.ex_dma_dm_to_rd (ex_dma_dm_to_rd),
.ex_rot (ex_rot),
.wb_rot (wb_rot),
.wb_dma_dm_to_rd (wb_dma_dm_to_rd),
.wb_su_load (wb_su_load),
.wb_su_uns_ls (wb_su_uns_ls),
.wb_pass_thru (wb_pass_thru),
.wb_mfc2 (wb_mfc2),
.wb_cfc2 (wb_cfc2),
.ls_drive_ls (ls_drive_ls)
);
endmodule