/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: ms.v,v 1.14 2003/01/23 17:47:45 berndt Exp $
//		top level for memspan
//  this module contains instantiation of spanbuf.v and the four memspan
//  logic modules ms_sm.v, ms_sc.v, ms_si.v, ms_rp.v as well as the
//  dither module from phil ms_rand.v;
//
//	added:  tristate driver cells dbus_driver.v  ebus_driver.v
//	to add:  64b driver to/from texture unit (tonyd, rws)
//
//  Note:  memspan does not differentiate between primitives, e.g. each
//  span from its point of view is a primitive;  it's up to the host to
//  perform sync's as needed to achieve expected results...
//
//  Phasing info:  all is relative to "startspant0" here:  later by:
//	5 clocks:  z to blend OR load data to texture unit
//	6 clocks:  c to blend AND alpha from color combiner unit
//*new* 7 clocks:  copy data from texture unit to memspan
//	8 clocks:  z from blend 
//	9 clocks:  c from blend
//	14 clocks: writemasks latched, launch write of spanlet

//  (note:  above is max case; actual can be up to 3 less due to mode
//   controlled pipe length, needed to allow sustained throughput r/w c/z
//   of the single port register file spanbufs;  and behaviorally all are
//   extended a clock functionally if twocycle mode case, but this is details)
//
//  Prefetch occurs much before the above, determined by EW output to
//	span buffer timing relative to startspant0.

//	span buffer not yet designed/sized (see notes herein);
//	***add cbus i/f module, tristate dbus module********

//  a note on stalls:  the working assumption is that the memspan stall
//  signal "stopgclock" is used "immediately" to defer next rising edge
//  of gclock.

//mods 10-19-94:  rel_sync_full, stb_sync_full, unfreeze_gclk, freeze_gclk;
//mods 10-20-94:  tristate drivers ms_drve/t/d.v, cbus module "ms_dma.v";
//			add pipe_busy output from ms_sm.v
//mods 10-26-94:  add startspant12, endspant11, fullc/zwmt11, stallnxtwm
//mods 10-28-94:  cbus read/write separate enables, add stopgclock to ms_sc.v
//mods 11-7 add endspant14 (sc, rp)
//mods 11-10 add BIST
//mods 11-16:  add wire copywen (ms_si to ms_rp), si:  ccalpha, alphacompen;
//		also wrcopymode_buf, wrcsize8_buf, wrcsize16_buf;
//mods 11-17:  add rdpc/zwptrn[6:0] from ms_rp to ms_si for ldc/zbufwen phasing;
//mods 11-20:  add to si: dithalpha, dithalphaen, blendalpha for copymode;
//mods 11-21:  add stallwptr from ms_rp to ms_si to kill rdpwe at stalls;
//	add rmwcsize32 to ms_rp for cptrinc;
//mods 11-23:  add ms_sm outport start_gclk, prop to top level;
//mods 11-29:  buffer fillcolor as wrfillcolor in ms_sc.v
//mods 12-2:  add stallptr input to ms_si for conflict sm
//mods 12-5:  add out/in wrrender_buf ms_sc/ms_rp
//     12-6:  add rmwenreadc into ms_si for coverage hack;
//	12-7:  mod startspan(input), startspand2(stall creation);
//		undo d2 mod
//	12-22:  add sc->rp:  wrloadmode_buf, wrenreadz_buf for transl fix;
//	12-30:  add validt2 to ms_sc.v (new year's hack);
//	1-3 add rmwenreadz from ms_sc to ms_si for zread force at enreadz=0;
//	1-4 add test_mode1 from ms_debug to ms_si, ms_rp; test_mode0 to ms_sc;
//	  stallrdctxtd, stallwrctxtd, stallczwmd, stallc/zr/wd to ms_debug;
//		also add stopgclockd;
//	1-5 add  rel_sync_full to diags; also:  stb_sync_full;
//	2-1  add start4ms from ms_sm to ms_si for extphase bug fix;
//		SECOND TAPEOUT MODS
//	3-30-95  add new ports rp => si:  limitcw, limitzw (timing paths);
//		remove stallwptr rp => si ports;
//	4-4-95  connect test_mode0 from ms_debug to ms_sc to reset ptrs;
//	6/2/95 (pg) added ordered dither stuff
//	6-9-95 update buswidth for start_gclk, now a bus for new gclk scheme;

`timescale 1ns/1ns

module ms(clock, start_gclk, reset_l, grant, start, finish, dma_write_enable,
	dma_read_enable, cbus_read_enable, cbus_write_enable, cbus_select,
	cbus_command, read_grant,
	stb_sync_full, freeze_gclk, unfreeze_gclk,
	cycle_type, image_read_en, z_update_en, z_compare_en, color_base,
	color_size, color_format, z_base, tex_base, tex_size, tex_format,
	load_tlut_en, fillcolor, alphacompen, dithalphaen, blendalpha, noise,
	startspant0, nextspanxi, nextspanxf, nextspancount, nextspanxdec,
	load_en, spanbufmt, rdpwdepthin, rdpwredin, rdpwgreenin,
	rdpwbluein, rdpwalphain, rdpcolorwen, ccalpha,
	dither_sel, rgb_dither,

// (was) bidirectional
	copy_load, 
	ms_copy_load, 

//c,d&e busses
	cbus_din,  dbus_din,  ebus_din,
	cbus_dout, dbus_dout, ebus_dout,

//outputs begin
	load_dv, rel_sync_full, pipe_busy, stopgclock,
	start_gclock, rdramreq, read_request, rdramrw,
	spanbufrd, rdprred, rdprgreen, rdprblue, rdpralpha,
//	bist_go, bist_check,
//	start_gclk1, start_gclk2, start_gclk3,
//	start_gclk4, start_gclk5, start_gclk6,
	rdprdepthd);

// `include "ms.vh"	// Note: causes some sort of asic synth problem.
`include "ms.vh"	//hmmm...right now I need it to compile....rws 10-19

input clock;					// system clock
input start_gclk;

input reset_l;					// system reset
input stb_sync_full;				//full sync request to ms
input freeze_gclk;				//from host, freeze gclk
input unfreeze_gclk;				//from sp, undo fullsync freeze

input grant;					//dma grant
input start;					//dma data valid
input finish;					//dma read last cycle
input dma_write_enable;				//ms to io tristate en
input dma_read_enable;				//io to ms enable

input cbus_read_enable;
input cbus_write_enable;
input [1:0] cbus_select;
input [2:0] cbus_command;
input read_grant;

input [1:0]  cycle_type;			//attributes etc. begin
input image_read_en;
input z_update_en;
input z_compare_en;
input [25:0]  color_base;
input [1:0]  color_size;
input [2:0]  color_format;
input [25:0]  z_base;
input [25:0]  tex_base;
input [1:0]  tex_size;
input [2:0]  tex_format;
input load_tlut_en;				//ignored unless load_en set
input [31:0]  fillcolor;
input alphacompen;
input dithalphaen;
input [7:0]  blendalpha;
input [2:0] noise;				//cc noise to dither gen

input startspant0;				//startspan from EW pipe, delay

input [19:0]  nextspanxi;			//EW initial span pix coord
input [11:0]  nextspanxf;			//EW final span pix coord
input [11:0]  nextspancount;			//EW count per span
input nextspanxdec;				//right major per span
input load_en;					//load enable per span
input spanbufmt;				//span buffer empty

input [17:0]  rdpwdepthin;			//depth value from blend
input [7:0] rdpwredin;
input [7:0] rdpwgreenin;
input [7:0] rdpwbluein;
input [2:0] rdpwalphain;
input rdpcolorwen;				//wen (sync'd with color)
input [7:0]  ccalpha;				//alpha from cc
input [1:0] dither_sel;
input [2:0] rgb_dither;

input [63:0] copy_load;			// copy / load in
output [63:0] ms_copy_load;		// copy / load out
input [31:0] cbus_din;
input [63:0] dbus_din;
input [7:0] ebus_din;
output [31:0] cbus_dout;
output [63:0] dbus_dout;
output [7:0] ebus_dout;

output load_dv;			// valid load data on copy_load bus
output rdramreq;
output rdramrw;
output read_request;		//output of cbus module to io 

output stopgclock;		//stall output:  used by rws sim env only
output start_gclock;		//new polarity of above for system level
output rel_sync_full;		//to EW, sync done, gclk to stop
output pipe_busy;		//memspan not in rel_sync_full condition

output spanbufrd;				//pop span buffer
			//note:  for simplicity, we might not want to read and
			//write span buffer at same time, add logic to do this?
			//e.g. spanbufmt = spanbufmt.in || spanbufload from EW
			//note also:  spanbuf never overflows (choose size!);

output [7:0] rdprred;				//color to blend unit
output [7:0] rdprgreen;
output [7:0] rdprblue;
output [2:0] rdpralpha;

output [17:0]  rdprdepthd;			//depth to blend unit

// output bist_go;
// output bist_check;

//wires define

//sm

wire [3:0] smcwincwr, smzwincwr;

//sc

wire [1:0] cycle_type, color_size, tex_size;
wire [2:0] color_format, tex_format;
wire [6:0] rdramlen;
wire [11:0] nextspanxf, nextspancount, stepcount, pixcount, wrcxf_buf;
wire [19:0] nextspanxi;
wire [25:0] color_base, tex_base, z_base, rdramaddr;
wire [25:0] rdcxi, savezxi, rdzxi, rmwcxi, rmwzxi, wrcxi_buf, wrzxi_buf,
		wrcxi, wrzxi;
wire [3:0] rmwrbcrptr, rdrbzrptr, wrrbcrptr_buf, wrrbzrptr_buf;
wire [31:0] wrfillcolor;

//si

wire [143:0] din, dout;
wire [3:0] addr0, addr1;
wire [7:0] ebus_din;
wire [26:0] rdprcolor, rdpwcolor;
wire [17:0] rdprdepthd, rdpwdepth;
wire [31:0] zwmask, fillcolor;
wire [63:0] dbus_din, dbus_data_out, cwmask, copy_load, dataload;
wire [7:0] ebus_data_out;
wire [6:0] rdpcrptrsb, rdpzrptrsb, rdpcwptrsbc, rdpzwptrsbc, rdpcwptrn, rdpzwptrn;
wire [3:0] rbcrptr, rbzrptr, rbcwptr, rbzwptr;

wire [7:0] rdpwredin, rdpwgreenin, rdpwbluein;
wire [2:0] rdpwalphain;
wire [17:0] rdpwdepthin;

//rp

wire [7:0] copywen, ccalpha, dithalpha, blendalpha;

//rand

wire [2:0] rand_r, rand_g, rand_b;

//iomsdma

wire [1:0] cbus_select;
wire [2:0] cbus_command;
wire [DRAM_ADDRESS_SIZE-1:0] dma_address;
wire [DMA_LENGTH_SIZE-1:0] dma_length;
wire [31:0] cbus_din;
wire [31:0] cbus_dout;
wire start_gclock, start_gclk;

//module instantiations

ms_sm sm ( .clock(clock), .reset_l(reset_l), .stb_sync_full(stb_sync_full),
	.freeze_gclk(freeze_gclk), .unfreeze_gclk(unfreeze_gclk),
	.rdspace(rdspace), .rdenreadc(rdenreadc), .rdenreadz(rdenreadz),
        .grant(grant), .start(start), .finish(finish),
        .creqw(creqw), .zreqw(zreqw), .cwmzero(cwmzero), .zwmzero(zwmzero),
	.rddone(rddone), .smcwincwr(smcwincwr), .smzwincwr(smzwincwr),
        .stallphase(stallphase), .stallrw(stallrw), .stallrdctxt(stallrdctxt),
	.stallwrctxt(stallwrctxt), .stallptr(stallptr), .stallczwm(stallczwm),
	.stallnxtwm(stallnxtwm), .spanproc(spanproc),

        .steprddone(steprddone),
	.finishd1(finishd1),
	.finishd2(finishd2),
        .rdramreqcr(rdramreqcr), .rdramreqzr(rdramreqzr),
	.rdramreqcw(rdramreqcw), .rdramreqzw(rdramreqzw),
        .enrbwe(enrbwe), .selrbcr(selrbcr), .selrbzr(selrbzr),
        .selrbcw(selrbcw), .selrbzw(selrbzw),
	.selcwmask(selcwmask), .selzwmask(selzwmask),
	.resetcreqw(resetcreqw), .resetzreqw(resetzreqw),
        .steprbcrptr(steprbcrptr), .steprbzrptr(steprbzrptr),
	.steprbcwptr(steprbcwptr), .steprbzwptr(steprbzwptr),
	.rbphase(rbphase), .start_gclock(start_gclock),
	.start4ms(start4ms),
	.stopgclock(stopgclock), .rel_sync_full(rel_sync_full),
	.pipe_busy(pipe_busy), .stopgclockd() );


ms_sc sc ( .clock(clock), .start_gclk(start_gclk), .reset_l(reset_l),
	.stopgclock(stopgclock),
        .cycle_type(cycle_type), .image_read_en(image_read_en),
	.z_update_en(z_update_en), .z_compare_en(z_compare_en),
        .color_base(color_base), .color_size(color_size),
	.z_base(z_base), .tex_base(tex_base),
	.tex_size(tex_size), .load_en(load_en),
        .color_format(color_format), .fillcolor(fillcolor),
	.tex_format(tex_format), .ldtlut_en(load_tlut_en),
        .nextspanxi(nextspanxi), .nextspanxf(nextspanxf),
	.nextspancount(nextspancount), .nextspanxdec(nextspanxdec),
	.spanbufmt(spanbufmt),
        .startspant0(startspant0d), .startspant1(startspant1),
	.startspant7m(startspant7m), .steprddone(steprddone),
        .steprbcrptr(steprbcrptr), .steprbzrptr(steprbzrptr),
	.steprbcwptr(steprbcwptr), .steprbzwptr(steprbzwptr),
        .rdramreqcr(rdramreqcr), .rdramreqzr(rdramreqzr),
	.rdramreqcw(rdramreqcw), .rdramreqzw(rdramreqzw),
	.creqw(creqw), .zreqw(zreqw), .test_mode0(1'b0),
        .resetcreqw(resetcreqw), .resetzreqw(resetzreqw),
	.startspant12(startspant12), .endspant11(endspant11),
	.fullcwmt11(fullcwmt11), .fullzwmt11(fullzwmt11),
	.startspant8(startspant8), .endspant12(endspant12),
	.endspant14(endspant14), .validt2 (validt2),

        .rdspace(rdspace), .rddone(rddone), .rdenreadc(rdenreadc),
	.rdenreadz(rdenreadz), .rdcxi(rdcxi), .savezxi(savezxi),
	.rdxdec(rdxdec), .rdzxi(rdzxi),
        .rmwenreadc(rmwenreadc), .rmwenreadz(rmwenreadz),
	.wrfillmode(wrfillmode),
	.wrzxi_buf(wrzxi_buf), .wrxdec_buf(wrxdec_buf),
        .rmwenwritec(rmwenwritec), .rmwenwritez(rmwenwritez),
	.wrenwritec_buf(wrenwritec_buf), .wrenwritez_buf(wrenwritez_buf),
	.stallrdctxt(stallrdctxt), .stallrdctxtd(),
	.stallwrctxtd(),
        .stallwrctxt(stallwrctxt), .rdramreq(rdramreq), .rdramlen(rdramlen),
	.rdramaddr(rdramaddr), .rdramdir(rdramdir), .rdramrw(rdramrw),
        .rdtwophase(rdtwophase), .rmwtwophase(rmwtwophase),
	.rdcopymode(rdcopymode), .rdfillmode(rdfillmode),
	.rdloadmode(rdloadmode), .wrloadmode(wrloadmode),
        .rmwcopymode(rmwcopymode), .rmwfillmode(rmwfillmode),
	.rmwloadmode(rmwloadmode), .pixcount(pixcount),
        .wrcopymode_buf(wrcopymode_buf), .wrfillmode_buf(wrfillmode_buf),
	.rmwrgbmode(rmwrgbmode), .rmwloadtlut(rmwloadtlut),
        .rdperclk8(rdperclk8), .rdperclk4(rdperclk4),
	.rdperclk2(rdperclk2), .rmwperclk8(rmwperclk8),
	.rmwperclk4(rmwperclk4), .rmwperclk2(rmwperclk2),
        .rmwcsize8(rmwcsize8), .rmwcsize16(rmwcsize16),
	.rmwcsize32(rmwcsize32), .wrcsize8_buf(wrcsize8_buf),
	.wrcsize16_buf(wrcsize16_buf), .wrfillcolor(wrfillcolor),
        .wrcsize32_buf(wrcsize32_buf), .wrcxi_buf(wrcxi_buf),
	.wrcxf_buf(wrcxf_buf), .rmwcxi(rmwcxi), .rmwzxi(rmwzxi),
	.rmwxdec(rmwxdec), .spanproc(spanproc), .wrrender_buf(wrrender_buf),
	.smcwincwr(smcwincwr), .smzwincwr(smzwincwr),
	.rmwrbcrptr(rmwrbcrptr), .rdrbzrptr(rdrbzrptr),
	.wrrbcrptr_buf(wrrbcrptr_buf), .wrrbzrptr_buf(wrrbzrptr_buf),
        .stepcount(stepcount), .rbzrptr(rbzrptr),
	.rbcrptr(rbcrptr), .rbzwptr(rbzwptr), .rbcwptr(rbcwptr),
  	.rbcrptrd(), .rbzwptrd(),
	.rbcwptrd(), .rbzrptrd(),
	.wrcxi(wrcxi), .wrzxi(wrzxi), .wrxdec(wrxdec), .stallnxtwm(stallnxtwm),
	.wrloadmode_buf(wrloadmode_buf), .wrenreadz_buf(wrenreadz_buf),
        .spanbufrd(spanbufrd), .wrcopymode(wrcopymode) );

ms_si si ( .clock(clock), .start_gclk(start_gclk), .reset_l(reset_l),
	.rbphase(rbphase), .finishd1(finishd1), .finishd2(finishd2), 
	.start(start), .rdpwcolor(rdpwcolor), .rmwenreadz(rmwenreadz),
	.rdpwdepth(rdpwdepth), .stopgclock(stopgclock),
	.dbus_din(dbus_din), .dma_read_en(dma_read_enable),
	.ebus_din(ebus_din), .wrcopymode_buf(wrcopymode_buf),
        .dout(dout), .selrbcr(selrbcr), .selrbzr(selrbzr),
	.selrbcw(selrbcw), .selrbzw(selrbzw),
        .rmwrgbmode(rmwrgbmode), .wrcopymode(wrcopymode),
        .rdpreqcr(rdpreqcr), .rdpreqzr(rdpreqzr), .rdpreqcw(rdpreqcw),
	.rdpreqzw(rdpreqzw), .enrbwe(enrbwe),
	.selcwmask(selcwmask), .selzwmask(selzwmask),
        .wrfillcolor(wrfillcolor), .rbcrptr(rbcrptr),
	.rbzrptr(rbzrptr), .rbcwptr(rbcwptr),
	.rbzwptr(rbzwptr), .rdcxi(rdcxi), .rdzxi(rdzxi), .rdxdec(rdxdec),
        .wrcxi(wrcxi), .wrzxi(wrzxi), .wrxdec(wrxdec),
	.rmwcsize8(rmwcsize8), .rmwcsize16(rmwcsize16),
	.rmwcsize32(rmwcsize32), .rmwenreadc(rmwenreadc),
        .wrfillmode(wrfillmode), .cwmask(cwmask),
        .zwmask(zwmask), .rdpcrptrsb(rdpcrptrsb), .rdpzrptrsb(rdpzrptrsb),
	.rdpcwptrsbc(rdpcwptrsbc), .rdpzwptrsbc(rdpzwptrsbc),
	.rdprpixc(rdprpixc), .rdprpixz(rdprpixz),
        .rdpwpixc(rdpwpixc), .rdpwpixz(rdpwpixz),
	.rmwcopymode(rmwcopymode), .rmwloadtlut(rmwloadtlut),
	.load_dve(load_dve), .blendalpha(blendalpha), .alphacompen(alphacompen),
	.wrcsize8_buf(wrcsize8_buf), .wrcsize16_buf(wrcsize16_buf),
	.rdpcwptrn(rdpcwptrn), .dithalpha(dithalpha),
	.rdpzwptrn(rdpzwptrn), .dithalphaen(dithalphaen),
	.stallptr(stallptr), .test_mode1(1'b0),
	.start4ms(start4ms), .limitcw(limitcw),  .limitzw(limitzw), 

        .dbus_dout(dbus_data_out), .ebus_dout(ebus_data_out), .din(din),
        .rdprcolor({rdprred, rdprgreen, rdprblue, rdpralpha}),
	.rdprdepthd(rdprdepthd), .copywen(copywen),
	.addr0(addr0), .addr1(addr1),
	.we0(we0), .we1(we1), .copy_load(copy_load), .dataload(dataload),
        .stallphase(stallphase), .stallrw(stallrw) );


ms_rp rp ( .clock(clock), .start_gclk(start_gclk), .reset_l(reset_l),
	.startspan(startspant0), .pixcount(pixcount),
	.stepcount(stepcount), .stopgclock(stopgclock),
        .rdloadmode(rdloadmode), .rdfillmode(rdfillmode),
	.rdcopymode(rdcopymode), .rmwxdec(rmwxdec),
        .rdtwophase(rdtwophase), .rmwtwophase(rmwtwophase),
	.rmwloadmode(rmwloadmode), .rmwcopymode(rmwcopymode),
	.rmwfillmode(rmwfillmode), .copywen(copywen),
        .rmwloadtlut(rmwloadtlut), .rdperclk8(rdperclk8),
	.rdperclk4(rdperclk4), .rdperclk2(rdperclk2),
        .rmwperclk8(rmwperclk8), .rmwperclk4(rmwperclk4),
	.rmwperclk2(rmwperclk2), .rmwcxi(rmwcxi), .rmwzxi(rmwzxi),
        .wrcxi_buf(wrcxi_buf), .wrcxf_buf(wrcxf_buf),
	.wrzxi_buf(wrzxi_buf), .wrxdec_buf(wrxdec_buf),
        .rbzrptr(rbzrptr), .rbcrptr(rbcrptr), .rbzwptr(rbzwptr),
	.rbcwptr(rbcwptr), .rmwenreadz(rmwenreadz), .rmwenreadc(rmwenreadc),
        .rmwenwritec(rmwenwritec), .rmwenwritez(rmwenwritez),
	.rmwcsize16(rmwcsize16), .rmwcsize32(rmwcsize32),
        .rdpwdepthin(rdpwdepthin), .wrloadmode(wrloadmode),
	.rdpwcolorin({rdpwredin, rdpwgreenin, rdpwbluein, rdpwalphain}),
	.rdpcolorwen(rdpcolorwen), .alphacompen(alphacompen),
	.dithalphaen(dithalphaen),
        .blendalpha(blendalpha), .dithalpha(dithalpha),
	.ccalpha(ccalpha), .rand_r(rand_r), .rand_g(rand_g), .rand_b(rand_b),
        .rdcxi(rdcxi), .savezxi(savezxi), .wrrender_buf(wrrender_buf),
        .resetcreqw(resetcreqw), .resetzreqw(resetzreqw),
	.wrenwritez_buf(wrenwritez_buf), .wrenwritec_buf(wrenwritec_buf),
        .wrcsize8_buf(wrcsize8_buf), .wrcsize16_buf(wrcsize16_buf),
	.wrcsize32_buf(wrcsize32_buf), .rdxdec(rdxdec),
        .wrfillmode_buf(wrfillmode_buf), .wrcopymode_buf(wrcopymode_buf),
        .rmwrbcrptr(rmwrbcrptr), .rdrbzrptr(rdrbzrptr),
        .wrrbcrptr_buf(wrrbcrptr_buf), .wrrbzrptr_buf(wrrbzrptr_buf),
	.wrloadmode_buf(wrloadmode_buf), .wrenreadz_buf(wrenreadz_buf),
	.test_mode1(1'b0),

        .startspant1(startspant1), .startspant7m(startspant7m),
        .stallptr(stallptr), .stallczwm(stallczwm), .load_dv(load_dv),
	.startspant12(startspant12), .endspant11(endspant11),
	.fullcwmt11(fullcwmt11), .fullzwmt11(fullzwmt11),
        .creqw(creqw), .zreqw(zreqw), .cwmask(cwmask), .zwmask(zwmask),
	.cwmzero(cwmzero), .zwmzero(zwmzero), .stallczwmd(),
	.startspant8(startspant8), .startspant0(startspant0d),
        .rdprpixz(rdprpixz), .rdprpixc(rdprpixc), .rdpwpixz(rdpwpixz),
	.rdpwpixc(rdpwpixc), .rdpreqzr(rdpreqzr), .rdpreqcr(rdpreqcr),
        .rdpreqzw(rdpreqzw), .rdpreqcw(rdpreqcw), .rdpzrptrsb(rdpzrptrsb),
	.rdpcrptrsb(rdpcrptrsb), .rdpzwptrsbc(rdpzwptrsbc),
	.rdpcwptrsbc(rdpcwptrsbc), .endspant12(endspant12),
	.endspant14(endspant14), .load_dve(load_dve),
 	.stallcrd(), .stallzrd(),
   	.stallcwd(), .stallzwd(),
        .rdpcwptrn(rdpcwptrn), .validt2 (validt2),
        .rdpzwptrn(rdpzwptrn),
	.limitcw(limitcw),  .limitzw(limitzw),
        .rdpwdepth(rdpwdepth), .rdpwcolor(rdpwcolor) );

ms_rand rand ( .clk(clock), .reset_l(reset_l),
	.dither_sel(dither_sel), .rgb_dither(rgb_dither), .noise(noise),
	.rand_r(rand_r), .rand_g(rand_g), .rand_b(rand_b),
	.alpha_dither(dithalpha) );

ms_spanbuf sb0 ( .wen(we0), .clk(clock), .a(addr0), .di(din[143:72]),
						 .dout(dout[143:72]) );

ms_spanbuf sb1 ( .wen(we1), .clk(clock), .a(addr1), .di(din[71:0]),
						 .dout(dout[71:0]) );

ms_dma iomsdma ( .clock(clock), .reset_l(reset_l),
	.cbus_read_enable(cbus_read_enable),
	.cbus_write_enable(cbus_write_enable),
	.cbus_select(cbus_select), .cbus_command(cbus_command),
	.read_grant(read_grant),
	.dma_read(rdramrw), .dma_down(rdramdir), .dma_address(rdramaddr[23:0]),
	.dma_length(rdramlen),
	.read_request(read_request),
	.cbus_din(cbus_din), .cbus_dout(cbus_dout) );

wire [63:0] dbus_dout = dma_write_enable ? dbus_data_out : {64{1'b0}};
wire [7:0]  ebus_dout = dma_write_enable ? ebus_data_out : {8{1'b0}};

//dbus_driver drvd ( .dbus_data_out(dbus_data_out), 
//		     .dbus_enable(dma_write_enable),
//		     .dbus_data(dbus_data) );

//ebus_driver drve ( .ebus_data_out(ebus_data_out), 
//		     .ebus_enable(dma_write_enable),
//                   .ebus_data(ebus_data) );

//tmem_driver drvt ( .tmem_data_out(dataload), .tmem_enable(load_dv),
//                .tmem_data(copy_load) );

wire [63:0] ms_copy_load = load_dv ? dataload : {64{1'b0}};

endmodule