ms_latch72.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ms_latch72.v,v 1.3 2003/01/13 21:08:36 rws Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: ms_latch72
// description: Transparent latches: rdram to spanbuf, transp=clk
//
// designer: Mike M. Cai / Robert W. Sherburne
// date: 12/16/94 revised 1/6/95
//
////////////////////////////////////////////////////////////////////////
module ms_latch72 (d_out, clk, g, d_in);
output [71:0] d_out;
input [71:0] d_in;
input clk, g;
reg [71:0] d_reg;
wire [71:0] d_out = d_reg;
always @(posedge clk) begin
if (g) begin
d_reg <= d_in;
end
end
endmodule //