/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: ms_rp.v,v 1.10 2003/01/24 23:07:37 berndt Exp $
//		rdp-sync'd control and datapath for memspan
//	this module receives "startspan" from EW pipe and delays it
//	thru a pipeline for use by the memspan RMW datapath;
//	generates validcycle, validcount, valid, endspan;
//	contains all r/w c/z spanbuf regfile pointers and r/w c/z
//	extraction/insertion pointers;  generates overflow stalls
//	for spanbuf accesses;  phases data flow for spanbuf c/z writes
//	depending on depth, z enable etc. to minimize (sustained) conflicts
//	at spanbuf r/w ports;  assembles c/z writemasks as needed and
//	generates write requests (creqw, zreqw) to the state machine modules.

//	mechanism: ptr if = rbptr generates immediate stall
//	as fn of r/w enable, planes enable, valid. stall goes away at rbptr++.

//	later:  copy alphacompareenable wmask contributions....
//	later: loadmode/copymode use for controlling load/copy wmask?
//      also:  rgb dither?????? maybe need to do in phil's block, as
//		not enuf time in our path (in-mux-transp-mux-regwrite-3ns tsu!)
//			**also remember there's a clock boundary too!**

//mods 10-12-94:  two cycle mode requires c/z r/w -ptrold registers for reg gen
//mods 10-19-94:  add dither rgb; affects input of reg rdpwcolord1; add dithen
//mods 10-20-94:  disable spanbuf write requests/stalls if wrfillmode_buf set
//mods 10-24-94:  cwmask uses (colorwen or fillmode)
//mods 10-25-94:  rep fout2 to 8b;  and with !fillmode/copymode;
//also mod'd cwmask update as fn of creqw/resetcreqw;  test, mod z also.
//but...really need gclock stalls here..
//mods 11-2  add c/zr/wptrt*sb and nextc/zr/wptrsb versions
//mods 11-5  make fullc/zwmt11 independent of *enwritec/z, for ptr usage (ms_sc)
//mods 11-7  add endspant14 for sc usage;  add copywen/mod cwmask; TBD: logic**
//mods 11-8  inhibit next c/zreqw with stopgclock, to avoid multi stall deadlock
//		add clock domain for c/zreqw state
//mods 11-10 add c/zreqrdt4/2c, rdpc/zwptrsbc and output for ms_si transp latches
//mods 11-12/94 fix setvalid term; mod cptrinc to 2 for rmwloadtlut;
//	add validt2ld, validt3ld for load_dv/dve calc and loadcount;
//	mod startspant7 out to startspant7m, as it's a muxed value.
//mods 11-15-94:  adj zreqwrt9 xor, have to do creqwr as well.....****
//  	11-16-94 cwmask update also for loadmode; finish all nxtptrs fn copymode
//	  mod copywen to 8b;  make it an input from ms_si;
//	11-17 add outputs rdpc/zwptrn (negedge clock, half phase early) to ms_si
//		and generate likewise validt9cn,11cn and stall all of above;
//	11-20 force c/zwmzero low for now....test later. mod creqwrt11;
//	11-21 add stallwptr for ms_si we kill; add rmwcsize32 for cptrinc;
//	11-22 mod startvalid;
//	11-23 mod c/zwptrt10 to xor w/xdec all bits; **later:  readptrs too***
//	12-1 mod stallzw for copymode16 case
//	12-5 add variable delay on startspant0, create d1-d6, and 0m versions
//	  mod fullc/zwmt11 to accommodate 4/8 word cases;  import wrrender_buf;
//	  also, mod copy:  delays = 6 (2cy), 1 (copy), 0 (load), 4 (other);
//	12-6 add nirvana, add 6 more delays startspan;
//		load:  d3, copy: d4, 1cycle: d10, 2cycle: d12;
//		minus one above to startspant0, which then creates stalls;
//	12-7 mod above to have d1-d11, then t0;  stall at d2 (conservative);
//		mod input to "startspan", undo d2 mod;  reset rd*modes;
//	12-8 re-enable write bypass of c/zwmzero;
//***************this version undoes above****************
//	12-12 revise always @ loop of endspant0 to fix simulator bug (now assigns)
//	12-13 allow culling of cwmzero/zwmzero cases; fix color dither field
//	12-14 fix color dither to use bitwise OR....and fix dith color generation
//	12-15 add ldstall, lddelayd1/d2 to fix load_tile bug? add wrloadmode in;
//	12-19 add mods to above via lddelayd1a/2a;
//	12-20 cleanup;
//	12-22 translucency fix:  allow zreqw, set zwmzero for zr/!zw/!ldmode
//		add inports:  wrloadmode_buf, wrenreadz_buf;
//	12-27 cleanup and merge jlsmith's improvements;
//	12-29 fix alphacompare bitwise OR bug;
//	12-29 delete envphaset0 register, unused;
//	12-30 new year's hack:  add output validt2 to ms_sc;
//	1-4  add inport test_mode1 to force high c/zwmzero to kill rdram writes;
//		add/reg outports stallc/zr/wd;
//	1-5  remove c/zwmzero kill;
//	1-9  instantiate negedge dff's;  add wires cwptrfn, zwptrfn[7:0];
//	1-24 this is a test version to convert latch8/10 to neg clock transp
//		here we reassign rdpc/zwptrn to be merely c/zwptrt8/10sb
//		and ditto for rdpreqzw/cw with validt9/11;
//	1-25 add gclk'd flop delay to rdpc/zwptrn generation;
//              SECOND TAPEOUT MODS
//      3-30-95  add new ports rp => si:  limitcw, limitzw (timing paths);
//		remove stallwptr;
//	4-24-95  mod stallzw to be OR of both cases, as now WE is not killed
//		by copymode zreqw assertion (as of 3-30 change);
//	5-9-95  OUCH! bug fix:  load tile case;  add lddelayd3a register;
//	5-10-95 improve above fix to handle other stall interactions;
//	6/2/95 (pg) removed dither control from here

`timescale 1ns/1ns

module ms_rp(clock, start_gclk, reset_l, startspan, pixcount, stepcount, 
	rdloadmode, rdfillmode, rdcopymode, rmwxdec, stopgclock,
	rdtwophase, rmwtwophase, rmwloadmode, rmwcopymode, rmwfillmode,
	rmwloadtlut, rdperclk8, rdperclk4, rdperclk2,
	rmwperclk8, rmwperclk4, rmwperclk2, rmwcxi, rmwzxi,
	wrcxi_buf, wrcxf_buf, wrzxi_buf, wrxdec_buf,
	rbzrptr, rbcrptr, rbzwptr, rbcwptr, rmwenreadz, rmwenreadc,
	rmwenwritec, rmwenwritez, rmwcsize16, rmwcsize32,
	rdpwdepthin, rdpwcolorin, rdpcolorwen, alphacompen, dithalphaen,
	blendalpha, dithalpha, ccalpha, rand_r, rand_g, rand_b,
	rdcxi, savezxi, rdxdec, wrloadmode,
	resetcreqw, resetzreqw, wrenwritez_buf, wrenwritec_buf,
	wrcsize8_buf, wrcsize16_buf, wrcsize32_buf,
	wrfillmode_buf, wrcopymode_buf, copywen, wrrender_buf,
	rmwrbcrptr, rdrbzrptr, wrrbcrptr_buf, wrrbzrptr_buf,
	wrloadmode_buf, wrenreadz_buf, test_mode1,
	
	startspant1, startspant7m, startspant12, endspant11,
	endspant12, endspant14, rdpcwptrn, rdpzwptrn,
	stallptr, stallczwm, load_dv, load_dve, startspant8,
	creqw, zreqw, cwmask, zwmask, cwmzero, zwmzero, validt2,
	stallcrd, stallzrd, stallcwd, stallzwd, stallczwmd,
	rdprpixz, rdprpixc, rdpwpixz, rdpwpixc, rdpreqzr, rdpreqcr,
	rdpreqzw, rdpreqcw, rdpzrptrsb, rdpcrptrsb, rdpzwptrsbc, rdpcwptrsbc,
	rdpwdepth, rdpwcolor, fullcwmt11, fullzwmt11, startspant0,
	limitcw, limitzw);

`include "ms.vh"

input clock;					// system clock
input start_gclk;
input reset_l;					// system reset
input stopgclock;

input startspan;
input [11:0] pixcount;				//total span iterations
input [11:0] stepcount;				//post-scissored iterations
input rmwxdec;
input rdtwophase;
input rmwtwophase;
input rmwloadmode;
input rmwcopymode;
input rmwfillmode;
input rdperclk8;
input rdperclk4;
input rdperclk2;
input rmwperclk8;
input rmwperclk4;
input rmwperclk2;
input [25:0] rmwcxi;
input [25:0] rmwzxi;

input [3:0] rbzrptr;
input [3:0] rbcrptr;
input [3:0] rbzwptr;
input [3:0] rbcwptr;

input rdloadmode;
input rdfillmode;
input rdcopymode;

input rmwenreadc;
input rmwenreadz;
input rmwenwritec;
input rmwenwritez;
input rmwcsize16;
input rmwcsize32;
input rmwloadtlut;
input wrloadmode;

input [17:0] rdpwdepthin;
input [26:0] rdpwcolorin;	
input rdpcolorwen;
input alphacompen;
input dithalphaen;
input [7:0] blendalpha;
input [7:0] dithalpha;
input [7:0] ccalpha;
input [2:0] rand_r;
input [2:0] rand_g;
input [2:0] rand_b;

input [25:0] rdcxi;
input [25:0] savezxi;
input rdxdec;
input [25:0] wrcxi_buf;
input [11:0] wrcxf_buf;
input [25:0] wrzxi_buf;
input wrxdec_buf;
input wrenwritec_buf;
input wrenwritez_buf;

input resetcreqw;
input resetzreqw;
input wrcsize8_buf, wrcsize16_buf, wrcsize32_buf;
input wrfillmode_buf, wrcopymode_buf;

input [3:0] rmwrbcrptr, rdrbzrptr, wrrbcrptr_buf, wrrbzrptr_buf;
input [7:0] copywen;
input wrrender_buf;
input wrloadmode_buf, wrenreadz_buf;
input test_mode1;

output startspant1;
output startspant7m;
output startspant12;
output endspant11;
output stallptr;
output stallczwm;
output stallczwmd;
output creqw;
output zreqw;
output [63:0] cwmask;
output [31:0] zwmask;
output cwmzero;
output zwmzero;
output validt2;

output stallcrd, stallzrd, stallcwd, stallzwd;

output endspant12, endspant14;

output rdpreqzr, rdpreqcr, rdpreqzw, rdpreqcw;
output rdprpixz, rdprpixc, rdpwpixz, rdpwpixc;
output [6:0] rdpzrptrsb, rdpcrptrsb, rdpzwptrsbc, rdpcwptrsbc;
output startspant8;
output [6:0] rdpcwptrn, rdpzwptrn;

output [17:0] rdpwdepth;
output [26:0] rdpwcolor;
output load_dv, load_dve;			//for tristate WE's on loads
output fullcwmt11, fullzwmt11;
output startspant0;
output limitcw, limitzw;

// input/output registers

reg validcyclet1;
reg endvalidt1;
reg enphaset0;
reg [11:0] currcount;
reg [11:0] rmwstepcount;
reg startvalid; 

reg [7:0] zrptrt1;
reg [7:0] zrptrt2;
reg [7:0] crptrt3;
reg [7:0] crptrt4;

reg [17:0] rdpwdepthd1;
reg [17:0] rdpwdepthd2;
reg [26:0] rdpwcolord1;
reg [26:0] rdpwcolord2;
reg [26:0] rdpwcolord3;

reg [7:0] zwptrt8;
reg [7:0] zwptrt9;
reg [7:0] zwptrt10;
reg [7:0] zwptrt11;
reg [7:0] cwptrt11;
reg [7:0] cwptrt10;

reg [63:0] cwmask;
reg [31:0] zwmask;
reg [63:0] nxtwmaskc;
reg [31:0] nxtwmaskz;
reg cwmzero, zwmzero;

reg xdect3, xdect8, xdect10;
reg rdpwend1, rdpwend2, rdpwend3;
reg alphacompd1, alphacompd2, alphacompd3;
reg [12:0] loadcount;

reg stallcrd, stallzrd, stallcwd, stallzwd;

// internal registers

reg [2:0] cxit11, cxft11;
reg endspant0en;
reg [4:0] nirvana;				//test coverage indicator only
reg load_dv, load_dve;

// non-resettable registers

reg lddelayd1, lddelayd2;
reg lddelayd1a, lddelayd2a, lddelayd3a;
//reg [6:0] rdpcwptrn, rdpzwptrn;
reg zrptrold, crptrold, zwptrold, cwptrold;
reg zwptrold2, cwptrold2;
reg zreqrdt2, zreqrdt2c, creqrdt4, creqrdt4c, zreqwrt9, creqwrt11;
reg creqw, zreqw;
reg startspand1, startspand2, startspand3, startspand4,
        startspand5, startspand6, startspand7, startspand8,
        startspand9, startspand10, startspand11, startspant0;
reg [2:0] cwptrmodt11;
reg fullcwmt11, fullzwmt11;
reg [7:0] zrptrt1sb, crptrt3sb, zwptrt8sb, cwptrt10sb;
reg [7:0] zrptrt2sb, crptrt4sb, zwptrt9sb, cwptrt11sb;
//reg validt11cn, validt9cn;
reg [6:0] cwptrt11sbc, zwptrt9sbc;
reg validt2ld, validt3ld;

reg startspant1, startspant2, startspant3, startspant4, startspant5,
        startspant6, startspant7, startspant7m,
        startspant8, startspant9, startspant10,
        startspant11, startspant12;
reg endspant1, endspant2, endspant3, endspant4, endspant5, endspant6,
        endspant7, endspant8, endspant9, endspant10, endspant11, endspant12;
reg endspant13, endspant14;
reg validphaset1;
reg validt2, validt3, validt4, validt5, validt6, validt7, validt8, validt9,
                                validt10, validt11;

// pseudo registers

reg [12:0] nextcount;
reg [7:0] cptrinc;				//color r/w ptr increment/valclk
reg rdpwen;
reg [17:0] rdpwdepth;
reg [26:0] rdpwcolor;
reg stallcr, stallzr, stallcw, stallzw;
reg rdpreqzr, rdpreqcr, rdpreqcw, rdpreqzw;
reg [6:0] rdpzrptrsb, rdpcrptrsb, rdpzwptrsbc, rdpcwptrsbc;
reg rdprpixc, rdprpixz, rdpwpixc, rdpwpixz;
reg stallptr;
reg stallczwm;
reg stallczwmd;
wire validt1, endspant0, validphaset0, setvalid;
wire [7:0] nextzrptr;
wire [7:0] nextcrptr;
wire [7:0] nextzwptr;
wire [7:0] nextcwptr;
reg [7:0] fstart;
reg [7:0] fend;
reg [7:0] fsetcbmask;
reg [3:0] fsetzbmask;
reg [63:0] fsetcwmask;
reg [31:0] fsetzwmask;
reg [7:0] fout1;
reg [7:0] fout2;
reg [7:0] fcbptr;
reg [7:0] fcwptr;
reg [3:0] fzbptr;
reg [7:0] fzwptr;
reg [23:0] rdpwcolordith;
reg [7:0] dithred;
reg [7:0] dithgreen;
reg [7:0] dithblue;

wire [6:0] cwptrfn, zwptrfn;
reg [6:0] rdpcwptrn, rdpzwptrn;
wire validt9cn, validt11cn;

wire [7:0] nextzrptrsb;
wire [7:0] nextcrptrsb;
wire [7:0] nextzwptrsb;
wire [7:0] nextcwptrsb;
reg ldstall;
reg limitcw, limitzw;

// wires

//startspant0m generation (3:1 mux output):

//always @(startspant0 or startspant0d1 or startspant0d2 or startspant0d3 or
//	startspant0d4 or startspant0d5 or startspant0d6 or rdloadmode or
//	startspant0d7 or startspant0d8 or startspant0d9 or startspant0d10
//	or startspant0d11 or rdcopymode or rdtwophase) begin

//	if (rdloadmode) begin
//		startspant0m <= startspant0;
//	end
//	else if (rdtwophase) begin
//		startspant0m <= startspant0d6;
//	end
//	else if (rdcopymode) begin
//		startspant0m <= startspant0d1;
//	end
//	else begin
//		startspant0m <= startspant0d4;
//	end
//end

//startspant7m generation (3:1 mux output):

always @(rmwtwophase or rmwenreadz or rmwenwritez or startspant5 or
	startspant6 or startspant7) begin

        if (!rmwtwophase & (rmwenreadz || rmwenwritez)) begin
                startspant7m <= startspant5;
        end
        else if (rmwtwophase & !(rmwenreadz || rmwenwritez)) begin
                startspant7m <= startspant6;
        end
        else begin
                startspant7m <= startspant7;
        end
end

//DELAYED DEPTH, COLOR to ms_si.v
//note:  don't code up unknown case, as don't plan to reset req'd state

//note:  rdpwcolor is 1b (we) and 8 8 8 3;  only 27 lsb's output, rest use here

always @(rdpwdepthin or rdpwdepthd1 or rdpwdepthd2 or rdpwcolorin or
		rdpwcolord1 or rdpwcolord2 or rdpwcolord3 or
		rmwenreadz or rmwenwritez or rmwtwophase or
		rdpwend1 or rdpwend2 or rdpwend3) begin

	if (!rmwtwophase & (rmwenreadz || rmwenwritez)) begin
		rdpwdepth <= rdpwdepthin;
		rdpwcolor <= rdpwcolord1;
		rdpwen <= rdpwend1;
	end
	else if (rmwtwophase & !(rmwenreadz || rmwenwritez)) begin
		rdpwdepth <= rdpwdepthd1;
		rdpwcolor <= rdpwcolord2;
		rdpwen <= rdpwend2;
	end
	else begin
		rdpwdepth <= rdpwdepthd2;
		rdpwcolor <= rdpwcolord3;
		rdpwen <= rdpwend3;
	end
end

//NEXTCOUNT DECREMENTER:  determines "endspant0" (via nextcount[12]);

always @(currcount or rdperclk8 or rdperclk4 or rdperclk2 or
		rmwperclk8 or rmwperclk4 or rmwperclk2 or startspant1) begin
  if (startspant1) begin
	if (rdperclk8) begin
		nextcount <= {1'b0, currcount} + 13'h0ff8;
	end
        else if (rdperclk4) begin
                nextcount <= {1'b0, currcount} + 13'h0ffc;
        end
        else if (rdperclk2) begin
                nextcount <= {1'b0, currcount} + 13'h0ffe;
        end
        else if (!rdperclk8 & !rdperclk4 & !rdperclk2) begin
                nextcount <= {1'b0, currcount} + 13'h0fff;
        end
        else begin
                nextcount <= 13'bx;
        end
  end
  else begin
        if (rmwperclk8) begin
                nextcount <= {1'b0, currcount} + 13'h0ff8;
        end
        else if (rmwperclk4) begin
                nextcount <= {1'b0, currcount} + 13'h0ffc;
        end
        else if (rmwperclk2) begin
                nextcount <= {1'b0, currcount} + 13'h0ffe;
        end
        else if (!rmwperclk8 & !rmwperclk4 & !rmwperclk2) begin
                nextcount <= {1'b0, currcount} + 13'h0fff;
        end
        else begin
                nextcount <= 13'bx;
        end
  end
end

//RDP COLOR R/W POINTER INCREMENT VALUES

always @(rmwperclk8 or rmwperclk4 or rmwperclk2 or rmwcsize16 or
	rmwcsize32 or rmwloadtlut) begin

	if (rmwperclk8 || rmwperclk2) begin
		cptrinc <= 8'h8;
	end
	else if (rmwperclk4 & rmwcsize16) begin
		cptrinc <= 8'h8;
	end
        else if (rmwperclk4 & !rmwcsize16) begin
                cptrinc <= 8'h4;
        end
        else if (rmwloadtlut) begin
                cptrinc <= 8'h2;
        end
	else if (!rmwperclk8 & !rmwperclk4 & !rmwperclk2 & !rmwloadtlut) begin
	  if (rmwcsize32) begin
		cptrinc <= 8'h4;
	  end
          else if (rmwcsize16) begin
                cptrinc <= 8'h2;
	  end
          else begin
                cptrinc <= 8'h1;
	  end
	end
	else begin
		cptrinc <= 8'bx;
	end
end

//RDP POINTERS AND REQUESTS TO ms_si.v and...
//STALL GENERATION:  read/write c/z pointers exceed rdram-based buffer domain
//  stallzr generated when read request has regword ptr[7:4] = rbrptr[3:0]
//      this stall goes away at rbptr update, as it's not a gclock domain reg

always @(cwptrt11sb or rbcwptr or zwptrt9sb or rbzwptr) begin
	limitcw <= (cwptrt11sb[7:4] == rbcwptr[3:0]);
	limitzw <= (zwptrt9sb[7:4] == rbzwptr[3:0]);
end

always @(zreqrdt2 or creqrdt4 or zreqwrt9 or creqwrt11 or rbzrptr or rbcrptr or
		zrptrt2sb or crptrt4sb or limitcw or limitzw or
			zreqrdt2c or creqrdt4c or zwptrt9sbc or cwptrt11sbc or
		stallzr or stallzw or stallcr or stallcw or wrcsize16_buf or
			wrcopymode_buf or zreqw) begin

        stallzr <= zreqrdt2 & (zrptrt2sb[7:4] == rbzrptr[3:0]);

        stallcr <= creqrdt4 & (crptrt4sb[7:4] == rbcrptr[3:0]);

        stallzw <= ((wrcsize16_buf & wrcopymode_buf & zreqw) ||
		(zreqwrt9 & limitzw));

        stallcw <= creqwrt11 & limitcw;

	stallptr <= stallzr || stallcr || stallzw || stallcw;

	rdpreqzr <= zreqrdt2c;
	rdpreqcr <= creqrdt4c;
	rdpreqzw <= zreqwrt9;
	rdpreqcw <= creqwrt11;

	rdpzrptrsb <= zrptrt2sb[6:0];
	rdpcrptrsb <= crptrt4sb[6:0];
	rdpzwptrsbc <= zwptrt9sbc[6:0];
	rdpcwptrsbc <= cwptrt11sbc[6:0];
end

always @(validt2 or validt4 or validt9 or validt11) begin
	rdprpixz <= validt2;
	rdprpixc <= validt4;
	rdpwpixz <= validt9;
	rdpwpixc <= validt11;
end

//WRITEMASK BUFFER STALL GENERATION for case of wmasks busy...

always @(creqw or zreqw or resetcreqw or resetzreqw or
		endspant12 or fullcwmt11 or fullzwmt11 or wrenwritec_buf or
			ldstall or wrenwritez_buf or wrenreadz_buf or
				wrloadmode_buf) begin

//	stallcwm <= creqw & (endspant12 || fullcwmt11);
//	stallzwm <= zreqw & (endspant12 || fullzwmt11);
//	stallczwm <= ((creqw || zreqw) & (endspant12 ||
//			fullcwmt11 || fullzwmt11));

//**new and improved wmask stalls....to be checked out....

	stallczwm <= (ldstall || (((creqw & !resetcreqw) || (zreqw & !resetzreqw)) &
		((fullcwmt11 & wrenwritec_buf) ||
			(fullzwmt11 & (wrenwritez_buf ||
			(wrenreadz_buf & !wrloadmode_buf))) || endspant12)));
end

always @(endspant12 or lddelayd1 or lddelayd2 or fullzwmt11 or lddelayd1a or
				lddelayd2a or lddelayd3a) begin
	
	ldstall <= (endspant12 & (lddelayd1 || lddelayd2)) ||
		(fullzwmt11 & (lddelayd1a || lddelayd2a || lddelayd3a));
end

//********bug above:  if endspant11, still need to stall because otherwise
//lose the request.  (creqw will not be set again).  maybe need a buffer
//for the creqw so it can be loaded when available;  e.g. nxtwmask can wait,
//and we have add'l stall if a startspan comes....in which case must stall.

//solution: for now, use endspant12 as a stall condition.  later may add
//a buffer of it to generate a further request, this is tricky due to
//must still stall a 1 pixel span coming afterward....case.

//RGB DITHERING

always @(dithred or dithgreen or dithblue or rdpwcolorin or rand_r or rand_g or rand_b) begin
	if (rdpwcolorin[21:19] > rand_r) begin
		dithred <= ({rdpwcolorin[26:22], 3'h0} + 8'h8) |
				{8{rdpwcolorin[26:22] == 5'h1f}};
	end
	else begin
		dithred <= rdpwcolorin[26:19];
	end
        if (rdpwcolorin[13:11] > rand_g) begin
                dithgreen <= ({rdpwcolorin[18:14], 3'h0} + 8'h8) |
                                {8{rdpwcolorin[18:14] == 5'h1f}};
	end
        else begin
                dithgreen <= rdpwcolorin[18:11];
        end
        if (rdpwcolorin[5:3] > rand_b) begin
                dithblue <= ({rdpwcolorin[10:6], 3'h0} + 8'h8) |
                                {8{rdpwcolorin[10:6] == 5'h1f}};
	end
        else begin
                dithblue <= rdpwcolorin[10:3];
        end
	rdpwcolordith <= {dithred, dithgreen, dithblue};
end

assign       validt1 =  validphaset1 & validcyclet1;

assign       endspant0 = validphaset0 & !nextcount[12] & endspant0en;

//endspant0en added to come out of reset, otherwise endspan cycles by itself
//combinational assigns for ease of interpretation (in theory...)

assign       validphaset0 = enphaset0 || (!rmwtwophase & !startspant1 ||
                                !rdtwophase & startspant1);
assign       setvalid = (startspant1 & (rdloadmode || rdfillmode || rdcopymode)) ||
                (((startspant1 & !(rdloadmode || rdfillmode || rdcopymode)) ||
                (startvalid & !(rmwloadmode || rmwfillmode || rmwcopymode))) &
                        !(currcount > rmwstepcount));
assign       nextzrptr = zrptrt1 + (8'h2 & ~{8{rmwloadmode || rmwcopymode}}) +
				(cptrinc & {8{rmwloadmode || rmwcopymode}});
assign       nextcrptr = crptrt3 + cptrinc;
assign       nextzwptr = zwptrt8 + (8'h2 & ~{8{rmwloadmode || rmwcopymode}}) +
                              	(cptrinc & {8{rmwloadmode || rmwcopymode}});
assign       nextcwptr = cwptrt10 + cptrinc;

assign       nextzrptrsb = zrptrt1sb + (8'h2 & ~{8{rmwloadmode || rmwcopymode}}) +
                               	(cptrinc & {8{rmwloadmode || rmwcopymode}});
assign       nextcrptrsb = crptrt3sb + cptrinc;
assign       nextzwptrsb = zwptrt8sb + (8'h2 & ~{8{rmwloadmode || rmwcopymode}}) +
                                (cptrinc & {8{rmwloadmode || rmwcopymode}});
assign       nextcwptrsb = cwptrt10sb + cptrinc;

//stuff for converting transp latches in ms_si to clock domain

//first, advance write ptrs a half clock for glitch-free usage in ldc/zbufwen's

//always @(negedge clock) begin
//  if (!stopgclock) begin
//        validt11cn <= validt10;
//        validt9cn <= validt8;
//	rdpcwptrn <= cwptrt10sb ^ {4'h0, {4{xdect10}}};
//	rdpzwptrn <= zwptrt8sb ^ {4'h0, {4{xdect8}}};
//  end
//  else begin
//        validt11cn <= validt11cn;
//        validt9cn <= validt9cn;
//        rdpcwptrn <= rdpcwptrn;
//	rdpzwptrn <= rdpzwptrn;
//  end
//end
//recode above as instantiated dff's to maintain negedge clock species for synth

//assign	rdpcwptrn = (cwptrt10sb[6:0] ^ {3'h0, {4{xdect10}}});
//assign rdpzwptrn = (zwptrt8sb[6:0] ^ {3'h0, {4{xdect8}}});

//mbnfnr ndff_1(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(validt10), .db(validt11cn), .q(validt11cn));
//mbnfnr ndff_2(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(validt8), .db(validt9cn), .q(validt9cn));

//assign cwptrfn = (cwptrt10sb[6:0] ^ {3'h0, {4{xdect10}}});
//assign zwptrfn = (zwptrt8sb[6:0] ^ {3'h0, {4{xdect8}}});

//mbnfnr ndff_4(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[6]), .db(rdpcwptrn[6]), .q(rdpcwptrn[6]));
//mbnfnr ndff_5(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[5]), .db(rdpcwptrn[5]), .q(rdpcwptrn[5]));
//mbnfnr ndff_6(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[4]), .db(rdpcwptrn[4]), .q(rdpcwptrn[4]));
//mbnfnr ndff_7(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[3]), .db(rdpcwptrn[3]), .q(rdpcwptrn[3]));
//mbnfnr ndff_8(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[2]), .db(rdpcwptrn[2]), .q(rdpcwptrn[2]));
//mbnfnr ndff_9(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[1]), .db(rdpcwptrn[1]), .q(rdpcwptrn[1]));
//mbnfnr ndff_a(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(cwptrfn[0]), .db(rdpcwptrn[0]), .q(rdpcwptrn[0]));

//mbnfnr ndff_c(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[6]), .db(rdpzwptrn[6]), .q(rdpzwptrn[6]));
//mbnfnr ndff_d(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[5]), .db(rdpzwptrn[5]), .q(rdpzwptrn[5]));
//mbnfnr ndff_e(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[4]), .db(rdpzwptrn[4]), .q(rdpzwptrn[4]));
//mbnfnr ndff_f(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[3]), .db(rdpzwptrn[3]), .q(rdpzwptrn[3]));
//mbnfnr ndff_g(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[2]), .db(rdpzwptrn[2]), .q(rdpzwptrn[2]));
//mbnfnr ndff_h(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[1]), .db(rdpzwptrn[1]), .q(rdpzwptrn[1]));
//mbnfnr ndff_i(.cpn(clock), .sa(~stopgclock), .sb(stopgclock),
                        //.da(zwptrfn[0]), .db(rdpzwptrn[0]), .q(rdpzwptrn[0]));

always @(posedge clock) begin
	lddelayd1 <= fullzwmt11 & wrloadmode & !endspant12;
	lddelayd2 <= lddelayd1;
	lddelayd1a <= (endspant12 || endspant13) & wrloadmode & !fullzwmt11;
	lddelayd2a <= lddelayd1a;
	lddelayd3a <= lddelayd2a;
	
	stallcrd <= stallcr;
	stallzrd <= stallzr;
	stallcwd <= stallcw;
	stallzwd <= stallzw;
	stallczwmd <= stallczwm;

  if (!stopgclock) begin
//	validt11c <= validt10;
//	validt9c <= validt8;
	cwptrt11sbc <= cwptrt10sb ^ {4'h0, {4{xdect10}}};
        zwptrt9sbc <= zwptrt8sb ^ {4'h0, {4{xdect8}}};
       creqrdt4c <=  rmwenreadc & (startspant4 ||
               ((crptrold ^ crptrt3[4]) & validt3));
        zreqrdt2c <=  rmwenreadz & (startspant2 ||
                ((zrptrold ^ zrptrt1[4]) & validt1));
	rdpcwptrn <= (cwptrt10sb[6:0] ^ {3'h0, {4{xdect10}}});
	rdpzwptrn <= (zwptrt8sb[6:0] ^ {3'h0, {4{xdect8}}});

  end
  else begin
//	validt11c <= validt11c;
//	validt9c <= validt9c;
	cwptrt11sbc <= cwptrt11sbc;
	zwptrt9sbc <= zwptrt9sbc;
	creqrdt4c <= creqrdt4c;
	zreqrdt2c <= zreqrdt2c;
        rdpcwptrn <= rdpcwptrn;
        rdpzwptrn <= rdpzwptrn;
  end

end


always @(posedge clock) begin
  if (start_gclk) begin

//calculating write enable for rdp pixel as fn of alphacompare

        rdpwend1 <= rdpcolorwen & (!alphacompen || alphacompd3);
        alphacompd3 <= alphacompd2;
        alphacompd2 <= alphacompd1;
        alphacompd1 <= ~(ccalpha < ({8{dithalphaen}} & dithalpha |
                                {8{!dithalphaen}} & blendalpha));

//delayed versions of data and we

        rdpwend2 <= rdpwend1;
        rdpwend3 <= rdpwend2;

        rdpwdepthd1 <= rdpwdepthin;
        rdpwdepthd2 <= rdpwdepthd1;
        rdpwcolord1 <= {rdpwcolordith, rdpwcolorin[2:0]};
        rdpwcolord2 <= rdpwcolord1;
        rdpwcolord3 <= rdpwcolord2;

//delayed versions of startspan from EW

	startspand1 <= startspan;
        startspand2 <= startspand1;
        startspand3 <= startspand2;
        startspand4 <= startspand3;
        startspand5 <= startspand4;
        startspand6 <= startspand5;
        startspand7 <= startspand6;
        startspand8 <= startspand7;
        startspand9 <= startspand8;
        startspand10 <= startspand9;
        startspand11 <= startspand10;

  if (rdloadmode) begin
        startspant0 <= startspand2;
  end
  else if (rdcopymode) begin
	startspant0 <= startspand3;
  end
  else if (!rdtwophase) begin
	startspant0 <= startspand9;
  end
  else begin
	startspant0 <= startspand11;
  end

        startspant1 <=  startspant0;
        startspant2 <= startspant1;
        startspant3 <= startspant2;
        startspant4 <= startspant3;
        startspant5 <= startspant4;
        startspant6 <= startspant5;
        startspant7 <= startspant6;


//calculating valid and endspan, also delayed versions

        if (!rmwtwophase & (rmwenreadz || rmwenwritez)) begin
                startspant8 <= startspant5;
                endspant7 <= endspant4;
                validt7 <= validt4;
        end
        else if (rmwtwophase & !(rmwenreadz || rmwenwritez)) begin
                startspant8 <= startspant6;
                endspant7 <= endspant5;
                validt7 <= validt5;
        end
        else begin
                startspant8 <= startspant7;
                endspant7 <= endspant6;
                validt7 <= validt6;
        end

        startspant9 <= startspant8;
        startspant10 <= startspant9;
        startspant11 <= startspant10;
        startspant12 <= startspant11;

        validphaset1 <= validphaset0;

        validt2 <= validt1;
        validt3 <= validt2;
        validt4 <= validt3;
        validt5 <= validt4;
        validt6 <= validt5;
//missing entry is above in startspan pipemod code
        validt8 <= validt7;
        validt9 <= validt8;
        validt10 <= validt9;
	validt11 <= validt10;


        endspant1 <= endspant0;
        endspant2 <= endspant1 & validcyclet1;
        endspant3 <= endspant2;
        endspant4 <= endspant3;
        endspant5 <= endspant4;
        endspant6 <= endspant5;
//missing entry is above in startspan pipemod code
        endspant8 <= endspant7;
        endspant9 <= endspant8;
        endspant10 <= endspant9;
        endspant11 <= endspant10;
        endspant12 <= endspant11;
        endspant13 <= endspant12;
        endspant14 <= endspant13;
  end
end
always @(posedge clock) begin
   if (reset_l == 1'b0) begin
      // resettable registers
	endvalidt1 <= low;
	validcyclet1 <= low;
	startvalid <= low;
	enphaset0 <= low;
        nxtwmaskc <= 64'b0;
	nxtwmaskz <= 32'b0;
	load_dv <= low;
	load_dve <= low;
	endspant0en <= low;
        cwmzero <= low;
        zwmzero <= low;
	nirvana <= 5'b0;

//assume EWpipe resets startspan before memspan receives it...
	
//nonresettable registers
  
//	rdpwdepthd1 <= 18'bx;
//	rdpwdepthd2 <= 18'bx;
//	rdpwcolord1 <= 27'bx;
//	rdpwcolord2 <= 27'bx;
//	rdpwcolord3 <= 27'bx;
//	alphacompd1 <= 'bx;
//      alphacompd2 <= 'bx;
//      alphacompd3 <= 'bx;

//	rdpwend1 <= 'bx;
//	rdpwend2 <= 'bx;
//	rdpwend3 <= 'bx;
   end
   else if (start_gclk) begin

	nirvana <= {(rdpreqzr & rdpreqcr & rdpreqzw & rdpreqcw) || nirvana[4],
		(!rdpreqzr & rdpreqcr & rdpreqzw & rdpreqcw) || nirvana[3],
		(rdpreqzr & !rdpreqcr & rdpreqzw & rdpreqcw) || nirvana[2],
		(rdpreqzr & rdpreqcr & !rdpreqzw & rdpreqcw) || nirvana[1],
		(rdpreqzr & rdpreqcr & rdpreqzw & !rdpreqcw) || nirvana[0]};

	if (startspant0) begin
		currcount <= pixcount;
	end
	else if (validphaset0) begin
		currcount <= nextcount;
	end
	else if (!startspant0 & !validphaset0) begin
		currcount <= currcount;
	end
	else begin
		currcount <= 12'bx;
	end

	enphaset0 <= startspant0 || (!enphaset0);

	if (startspant0) begin
		rmwstepcount <= stepcount;
	end
	else if (!startspant0) begin
		rmwstepcount <= rmwstepcount;
	end
	else begin
		rmwstepcount <= 12'bx;
	end
//loadcount determines # of load_dv cycles, can be one less than valid...

	if (startspant1) begin
		loadcount <= {1'b1, rmwstepcount};
	end
	else if (validt1 & !rmwloadtlut) begin
	  if (rmwperclk4) begin
		loadcount <= loadcount + 13'h1ffc;
   	  end
          else if (rmwperclk8) begin
                loadcount <= loadcount + 13'h1ff8;
          end
          else if (rmwperclk2) begin
                loadcount <= loadcount + 13'h1ffe;
          end
	end
        else if (validt1 & rmwloadtlut) begin
                loadcount <= loadcount + 13'h1fff;
        end
	else begin
		loadcount <= loadcount;
	end

  	validt2ld <= loadcount[12] & validt1 & rmwloadmode;

	endvalidt1 <= endspant0 & validphaset0;

	if (startspant1) begin
		startvalid <= high;
	end
	else if (validcyclet1) begin
		startvalid <= low;
	end
	else if (!(startspant1 || validcyclet1)) begin
		startvalid <= startvalid;
	end
	else begin
		startvalid <= 'bx;
	end

	if (setvalid) begin
		validcyclet1 <= high;
	end
	else if (endvalidt1) begin
		validcyclet1 <= low;
	end
	else if (!(setvalid || endvalidt1)) begin
		validcyclet1 <= validcyclet1;
	end
	else begin
		validcyclet1 <= 'bx;
	end

	load_dv <= validt3ld;			//indicate valid data load clks
	load_dve <= validt2ld;			//one clk earlier for io mux si
	validt3ld <= validt2ld;

//endspant0en added to come out of reset, otherwise endspan cycles by itself
        if (startspant0) begin
                endspant0en <= high;
        end
        else if (validphaset0 & !nextcount[12]) begin
                endspant0en <= low;
        end
        else begin
                endspant0en <= endspant0en;
        end

//R-S flipflop:

nxtwmaskc <= fsetcwmask | (nxtwmaskc &
  {~{64{endspant12 || (fullcwmt11 & (wrenwritec_buf || wrcopymode_buf))}}});

if (endspant12 || (fullcwmt11 & (wrenwritec_buf || (wrcopymode_buf)))) begin
        cwmask <= nxtwmaskc;
        cwmzero <=    ~|(nxtwmaskc);
end
else if (!(endspant12 ||
		(fullcwmt11 & (wrenwritec_buf || (wrcopymode_buf))))) begin
        cwmask <= cwmask;
        cwmzero <= cwmzero;
end
else begin
        cwmask <= 64'bx;
        cwmzero <= cwmzero;
end

//R-S flipflop:

nxtwmaskz <= fsetzwmask | (nxtwmaskz & {~{32{endspant12 || (fullzwmt11 & wrenwritez_buf)}}});


//if (endspant12 || (fullzwmt11 & wrenwritez_buf)) begin
if (endspant12 || (fullzwmt11)) begin
        zwmask <= nxtwmaskz;
        zwmzero <=  (wrcopymode_buf ? ~|(nxtwmaskc) : ~|(nxtwmaskz)) ||
			(wrenreadz_buf & !wrenwritez_buf & !wrloadmode_buf);
end
//else if (!(endspant12 || (fullzwmt11 & wrenwritez_buf))) begin
else if (!(endspant12 || (fullzwmt11))) begin
        zwmask <= zwmask;
        zwmzero <= zwmzero;
end
else begin
        zwmask <= 32'bx;
        zwmzero <= zwmzero;
end

end 
end


always @(posedge clock) begin
   if (reset_l == 1'b0) begin
      // resettable registers
        creqw <= low;
        zreqw <= low;
   end
   else begin

//WRITE REQUEST GENERATION when wmasks full or end of span
//**have set higher priority than reset;  allow no gap in reqw**
//must add stopgclock to avoid deadlock in event of multiple stall sources!

if (wrenwritec_buf & !stopgclock & (endspant12 || fullcwmt11)) begin
        creqw <= high;
end
else if (resetcreqw) begin
        creqw <= low;
end
else if (!resetcreqw & !(wrenwritec_buf & !stopgclock &
				(endspant12 || fullcwmt11))) begin
        creqw <= creqw;
end
else begin
        creqw <= 'bx;
end

if ((wrenwritez_buf || (wrenreadz_buf & !wrloadmode_buf)) &
		!stopgclock & (endspant12 || fullzwmt11)) begin
        zreqw <= high;
end
else if (resetzreqw) begin
        zreqw <= low;
end
else if (!resetzreqw & !((wrenwritez_buf || (wrenreadz_buf & !wrloadmode_buf)) &
		!stopgclock & (endspant12 || fullzwmt11))) begin

        zreqw <= zreqw;
end
else begin
        zreqw <= 'bx;
end

end
end

always @(posedge clock) begin
	if (reset_l == 1'b0) begin

        fullcwmt11 <= low;
        fullzwmt11 <= low;
end
	else if (start_gclk) begin

//RDPTR LOGIC
//mod'd for xdec (note:  xdec is set for right major triangle)
//	init is xdec xor ptr 2:0 due to up/down iterations
//	then always increment...at this point. (xor again afterward).
//also:  must locally buffer xdec...changes per primitive

//nasty changes 10-12-94:  due to twophase/validcycle behavior, the
//c/zreqrd/wr xor detect fails;  address is stable per 2 clocks!
//fix:  must latch with validcycle, create *ptrold registers.
//for writes, set to same polarity to kill any write during first detect xor;
//same for reads but OR in startspan to force prefetch...

	if (startspant1) begin
		zrptrt1 <= savezxi[7:0] ^ {4'h0, {4{rdxdec}}};
		zrptrt1sb <= {rdrbzrptr[3:0], savezxi[3:0]} ^ {4'h0, {4{rdxdec}}};
	end
	else if (validt1) begin
		zrptrt1 <= nextzrptr;
		zrptrt1sb <= nextzrptrsb;
	end
	else if (!startspant1 & !validt1) begin
		zrptrt1 <= zrptrt1;
		zrptrt1sb <= zrptrt1sb;
	end
	else begin
		zrptrt1 <= 8'bx;
		zrptrt1sb <= 8'bx;
	end

// FYI:	zrwordptr = zrptrt1[4:0]; (used on t2).

	zrptrt2 <= zrptrt1 ^ {4'h0, {4{rmwxdec}}};
//sb used for spanbuf addressing
        zrptrt2sb <= zrptrt1sb ^ {4'h0, {4{rmwxdec}}};

//	zreqrdt2 <= rmwenreadz & (startspant2 ||
//		((zrptrt2[4] ^ zrptrt1[4]) & validt1));
	zreqrdt2 <= rmwenreadz & (startspant2 ||
                ((zrptrold ^ zrptrt1[4]) & validt1));

	if (startspant2 || validt1) begin
		zrptrold <= zrptrt1[4];
	end
	else begin
		zrptrold <= zrptrold;
	end

//  we request z word read when iterate out of current word (and valid)
//  	OR when startspan received (regardless of scissor delay) for prefetch;
//  therefore, when zrptr[4] changes, it's a new word.

        if (startspant3) begin
               crptrt3 <= rmwcxi[7:0] ^ {4'h0, {4{rmwxdec}}};
               crptrt3sb <= {rmwrbcrptr[3:0], rmwcxi[3:0]} ^ {4'h0, {4{rmwxdec}}};
        end
        else if (validt3) begin
                crptrt3 <= nextcrptr;
		crptrt3sb <= nextcrptrsb;
        end
        else if (!startspant3 & !validt3) begin
                crptrt3 <= crptrt3;
		crptrt3sb <= crptrt3sb;
        end
        else begin
                crptrt3 <= 8'bx;
                crptrt3sb <= 8'bx;
        end

// FYI: crwordptr = crptrt3[4:0]; (use on t4).

	if (startspant3) begin
		xdect3 <= rmwxdec;
	end
	else if (!startspant3) begin
		xdect3 <= xdect3;
	end
	else begin
		xdect3 <= 'bx;
	end

        crptrt4 <= crptrt3 ^ {4'h0, {4{xdect3}}};
        crptrt4sb <= crptrt3sb ^ {4'h0, {4{xdect3}}};
//  moved to clock, creqrdt4c for transp latch timing
       creqrdt4 <= rmwenreadc & (startspant4 ||
               ((crptrold ^ crptrt3[4]) & validt3));

        if (startspant4 || validt3) begin
                crptrold <= crptrt3[4];
        end
        else begin
                crptrold <= crptrold;
        end

//WRPTR LOGIC
//mod'd for xdec (note:  xdec is set for right major triangle)
//      init is xdec xor 3:0
//      then always increment...at this point.
//also:  must locally buffer xdec...changes per primitive
//******and must add xdec buffer at z stage, use delayed version for c.....

        if (startspant8) begin
                zwptrt8 <= wrzxi_buf[7:0] ^ {{8{wrxdec_buf}}};
//                zwptrt8 <= wrzxi_buf[7:0] ^ {{8{wrxdec_buf}}}; funky
                zwptrt8sb <= {wrrbzrptr_buf[3:0], wrzxi_buf[3:0]} ^
                                        {4'h0, {4{wrxdec_buf}}};
        end
        else if (validt8) begin
                zwptrt8 <= nextzwptr;
		zwptrt8sb <= nextzwptrsb;
        end
        else if (!startspant8 & !validt8) begin
                zwptrt8 <= zwptrt8;
                zwptrt8sb <= zwptrt8sb;
        end
        else begin
                zwptrt8 <= 8'bx;
                zwptrt8sb <= 8'bx;
        end

// FYI: zwwordptr = zwptrt9[4:0];

        if (startspant8) begin
                xdect8 <= wrxdec_buf;
        end
        else if (!startspant8) begin
                xdect8 <= xdect8;
        end
        else begin
                xdect8 <= 'bx;
        end

//        zwptrt9 <= zwptrt8 ^ {5'h0, {3{xdect8}}};
        zwptrt9 <= zwptrt8 ^ {{8{xdect8}}};
        zwptrt9sb <= zwptrt8sb ^ {4'h0, {4{xdect8}}};

	zwptrt10 <= zwptrt9;
	zwptrt11 <= zwptrt10;
//we use zwptrt11 for wmask calculation;  cwptr is already generated for t11;
//        zreqwrt9 <= #1 !wrfillmode_buf & wrenwritez_buf & (endspant8 ||
//                !startspant9 & (zwptrold ^ zwptrt8[4])) & validt8;

        zreqwrt9 <= !wrfillmode_buf & wrenwritez_buf & (endspant8 ||
                !startspant8 & (nextzwptr[4] ^ zwptrt8[4])) & validt8;

//above, kill with startspant9 because zwptrold is stale, and because
//we never generate write at first pixel of span it's not a problem.

        if (startspant9 || validt8) begin
                zwptrold <= zwptrt8[4];
        end
        else begin
                zwptrold <= zwptrold;
        end


//  we request z word write when iterate out of current word (and valid)
//      OR when endspan received;

        if (startspant10) begin
                cwptrt10 <= wrcxi_buf[7:0] ^ {{8{wrxdec_buf}}};
//                cwptrt10 <= wrcxi_buf[7:0] ^ {5'h0, {3{wrxdec_buf}}};
                cwptrt10sb <= {wrrbcrptr_buf[3:0], wrcxi_buf[3:0]} ^
				{4'h0, {4{wrxdec_buf}}};
        end
        else if (validt10) begin
                cwptrt10 <= nextcwptr;
                cwptrt10sb <= nextcwptrsb;
        end
        else if (!startspant10 & !validt10) begin
                cwptrt10 <= cwptrt10;
                cwptrt10sb <= cwptrt10sb;
        end
        else begin
                cwptrt10 <= 8'bx;
                cwptrt10sb <= 8'bx;
        end

// FYI: cwwordptr = cwptrt11[4:0];

        if (startspant10) begin
                xdect10 <= wrxdec_buf;
        end
        else if (!startspant10) begin
                xdect10 <= xdect10;
        end
        else begin
                xdect10 <= 'bx;
        end
	
//        cwptrt11 <= cwptrt10 ^ {5'h0, {3{xdect10}}};
        cwptrt11 <= cwptrt10 ^ {{8{xdect10}}};
        cwptrt11sb <= cwptrt10sb ^ {4'h0, {4{xdect10}}};

        creqwrt11 <= !wrfillmode_buf & wrenwritec_buf & (endspant10 ||
                !startspant10 & (nextcwptr[4] ^ cwptrt10[4]) & validt10);


//        zreqwrt9 <= #1 !wrfillmode_buf & wrenwritez_buf & (endspant8 ||
//                !startspant8 & (nextzwptr[4] ^ zwptrt8[4])) & validt8;



//was sst11, try t10:
        if (startspant11 || validt10) begin
                cwptrold <= cwptrt10[4];
        end
        else begin
                cwptrold <= cwptrold;
        end

//COLOR WRITEMASK GENERATION
//use cwptrt11/zwptrt11 and wr_buf attributes
//
//calc wmask, store in rs flop, pass to register yielding cwmask/zwmask

//use also:   endspant11, startspant12

cwptrmodt11 <= (cwptrt10[2:0] ^ {3{xdect10}}) & {1'h1, !wrcsize32_buf,
						wrcsize8_buf};

if (startspant11) begin
	cxit11 <= wrcxi_buf[2:0];
	cxft11 <= wrcxf_buf[2:0];
end
else begin
	cxit11 <= cxit11;
	cxft11 <= cxft11;
end

//fullcwmt11 detects when we start a new bytemask group (64 bytes, aligned)
//this is used to enable stalls, and to launch new write events. c/z sync'd.
//it is NOT and'd here with wrenwritec_buf

if (!wrrender_buf) begin
	fullcwmt11 <= !startspant11 & (cwptrt10[6] ^ cwptrold2) &
						validt10;
end
else begin
        fullcwmt11 <= !startspant11 & (cwptrt10[5] ^ cwptrold2) &
                                                validt10;
end
if (startspant11 || validt10) begin
  if (!wrrender_buf) begin
	cwptrold2 <= cwptrt10[6];
  end
  else begin
	cwptrold2 <= cwptrt10[5];
  end
end
else begin
	cwptrold2 <= cwptrold2;
end

//fullzwmt11 detects when we start a new bytemask group (64 bytes, aligned)
//this is used to enable stalls, and to launch new write events. c/z sync'd.

if (!wrrender_buf) begin
	fullzwmt11 <= !startspant11 & (zwptrt10[6] ^ zwptrold2) &
						validt10;
end
else begin
        fullzwmt11 <= !startspant11 & (zwptrt10[5] ^ zwptrold2) &
                                                validt10;
end

if (startspant11 || validt10) begin
  if (!wrrender_buf) begin
        zwptrold2 <= zwptrt10[6];
  end   
  else begin
        zwptrold2 <= zwptrt10[5];
  end
end
else begin
        zwptrold2 <= zwptrold2;
end
end

end

always @(cxit11 or cxft11 or 
		cwptrmodt11 or cwptrt11 or startspant12 or endspant11 or
		wrfillmode_buf or wrcopymode_buf or wrcsize8_buf or
		wrcsize16_buf or wrcsize32_buf or fout1 or fout2 or copywen or
		validt11 or rdpwen or wrenwritec_buf or fsetcbmask or
		wrenwritez_buf) begin

//first generate start/end 8b masks for load/fill/copy usage

case (cxit11[2:0])
        3'h0: fstart = 8'hff;
        3'h1: fstart = 8'h7f;
        3'h2: fstart = 8'h3f;
        3'h3: fstart = 8'h1f;
        3'h4: fstart = 8'h0f;
        3'h5: fstart = 8'h07;
        3'h6: fstart = 8'h03;
        3'h7: fstart = 8'h01;
endcase

case (cxft11[2:0])
        3'h0: fend = 8'h80;
        3'h1: fend = 8'hc0;
        3'h2: fend = 8'he0;
        3'h3: fend = 8'hf0;
        3'h4: fend = 8'hf8;
        3'h5: fend = 8'hfc;
        3'h6: fend = 8'hfe;
        3'h7: fend = 8'hff;
endcase

//below, fcbptr is function byte pointer (per 64b field) for !(fill/copy/load)

case (cwptrmodt11[2:0])
        3'h0: fcbptr = 8'h80;
        3'h1: fcbptr = 8'h40;
        3'h2: fcbptr = 8'h20;
        3'h3: fcbptr = 8'h10;
        3'h4: fcbptr = 8'h08;
        3'h5: fcbptr = 8'h04;
        3'h6: fcbptr = 8'h02;
        3'h7: fcbptr = 8'h01;
endcase

//below fcwptr is function word pointer (of 8 words)

case (cwptrt11[5:3])
        3'h0: fcwptr = 8'h80;
        3'h1: fcwptr = 8'h40;
        3'h2: fcwptr = 8'h20;
        3'h3: fcwptr = 8'h10;
        3'h4: fcwptr = 8'h08;
        3'h5: fcwptr = 8'h04;
        3'h6: fcwptr = 8'h02;
        3'h7: fcwptr = 8'h01;
endcase

//must zero out sub-pixel precision lsb's of xi/xf for below!!!!!!
//this was done in cwptrmodt11[2:0]

        fout1 <= (~{8{startspant12}} | fstart) & (~{8{endspant11}} | fend) &
                {8{(wrfillmode_buf || wrcopymode_buf)}} &
                (~{8{wrcopymode_buf & wrcsize8_buf}} |
                        {~{4{cwptrt11[2]}}, {4{cwptrt11[2]}}});

        fout2 <= {fcbptr[7], fcbptr[6] || (fcbptr[7] & (wrcsize16_buf ||
                wrcsize32_buf)),
          (fcbptr[5] || (fcbptr[7] & wrcsize32_buf)),
          (fcbptr[4] || (fcbptr[5] & wrcsize16_buf ||
                                        fcbptr[7] & wrcsize32_buf)),
		fcbptr[3], fcbptr[2] || (fcbptr[3] & (wrcsize16_buf ||
                wrcsize32_buf)),
          (fcbptr[1] || (fcbptr[3] & wrcsize32_buf)),
          (fcbptr[0] || (fcbptr[1] & wrcsize16_buf ||
                                        fcbptr[3] & wrcsize32_buf))} &
		~{8{(wrfillmode_buf || wrcopymode_buf)}};

//bytemask selects within 8 byte field

        fsetcbmask <= (fout1 | fout2) &
			{8{(wrenwritec_buf & !wrcopymode_buf || 
			wrenwritez_buf & wrcopymode_buf) & validt11}} &
                      ({8{!wrcopymode_buf & rdpwen || wrfillmode_buf}} |
			{8{wrcopymode_buf}} & {{copywen}});

//enwritec unnecessary above but might help sim interpretation...

//expanded into 64 byte field using 8b word select: fcwptr

        fsetcwmask <= {8{fsetcbmask}} & {{8{fcwptr[7]}}, {8{fcwptr[6]}},
                {8{fcwptr[5]}}, {8{fcwptr[4]}}, {8{fcwptr[3]}}, {8{fcwptr[2]}},
                        {8{fcwptr[1]}}, {8{fcwptr[0]}}};

end

always @(zwptrt11 or fsetzbmask or rdpwen or validt11 or
		wrenwritez_buf or fsetzwmask) begin

//DEPTH WRITEMASK GENERATION

case (zwptrt11[2:1])
        2'h3: fzbptr = 4'h8;
        2'h2: fzbptr = 4'h4;
        2'h1: fzbptr = 4'h2;
        2'h0: fzbptr = 4'h1;
endcase

case (zwptrt11[5:3])
        3'h0: fzwptr = 8'h80;
        3'h1: fzwptr = 8'h40;
        3'h2: fzwptr = 8'h20;
        3'h3: fzwptr = 8'h10;
        3'h4: fzwptr = 8'h08;
        3'h5: fzwptr = 8'h04;
        3'h6: fzwptr = 8'h02;
        3'h7: fzwptr = 8'h01;
endcase

//bytemask selects within 8 byte field
//note for z each bit rep's 2 bytes in memory, since z is 16b

        fsetzbmask <= {fzbptr[0], fzbptr[1], fzbptr[2], fzbptr[3]} &
                {4{wrenwritez_buf & validt11 & rdpwen}};

//enwritez above unnecessary but might help sim interpretation

//expanded into 64 byte field using 8b word select: fzwptr

        fsetzwmask <= {8{fsetzbmask}} & {{4{fzwptr[7]}}, {4{fzwptr[6]}},
                {4{fzwptr[5]}}, {4{fzwptr[4]}}, {4{fzwptr[3]}}, {4{fzwptr[2]}},
                        {4{fzwptr[1]}}, {4{fzwptr[0]}}};

end

endmodule