/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: ms_si.v,v 1.13 2003/01/24 23:07:37 berndt Exp $
//		spanbuf interface for memspan
//	this module is a framework around the spanbuf register file
//	(which are two banks of 16 word x 72b memory, single ported)
//
//	handles read/write data paths of rdram access, with fillcolor
//		and writemask insertion as necessary;
//	contains split spanbuf address iterator for the rdram access.
//	also handles loads and copies data alignment;
//	handles c/z read data supply, write data consume, to/from rdp blend
//	it arbitrates rdp c/z r/w collisions and generates "stallrw" for
//	such incidents.  also, it generates "stallphase" for cases of these
//	rdp read/write c/z events occuring during a rdram phase (rbphase=1).

//	adding alpha compare and copy compare/bit shift enables
//	split addressing for rdram access
//	also add dither?  maybe in ms_rp.v  (rdp pipeline) where twophase also
//		buffer ops so that load will work without trashing context:
//	note also:  for safety, count stage should also define validphase,
//		and this not clobbered by load_en in rdctxt.....!
//	define rbwe0, rbwe1;
//	much later:  diags  (also affect ms_sm).
//	must stall load of cbufw, zbufw as needed; therefore those reg's are
//		stallable (feeders). **add gclock notion**

//NOTE:  each 16b source value has lsb rep'd into lower 2b of 18b field in sbuf
//therefore ebus is concatenation of 2lsb's from each 18b field = 8bits.
//span/scanline proceeds L-R across each 144b spanbuf entry...

//NOTE:  for pipe sync'ing, the LOAD data is provided AT SAME TIME AS
//read RDP depth data normally provided (tbd).
//and COPY data received ONE CLOCK BEFORE write RDP *depth* would have been
//copy:  z writes, use cwmask.  (tbd).
//load:  z reads.  (tbd). maybe need znum16?

//bytemask latest 10-12-94:  left-most byte pertains to first 8byte word,
//	and lsbit of this byte pertains to msbyte of data word, indep of xdec
//mods 10-13: rotate cwmask/zwmask for alignment with start word of span
//mods 10-20: revise for tristate driver outside module, shared io reg's
//	and add input "load_dve" early version of load_dv for mux usage
//	this changes timing of copy data, to ONE CLOCK BEFORE depth supplied
//  11-2-94:  hack rbwe
//  11-8  stallrwen state machine now fn of stopgclock, fix deadlocked stalls
//  11-9 add transp latches, ldcbuf144, ldzbuf144
//  11-10 fix loadsend for case of ptr = 7;  mod transp w: clk, r: !clk
//  	add extphaser; add inputs rdpcwptrsbc for transp
//  11-11 add delay to addr0/1 to spanbuf, fix hold time vs. we0/1....
//  11-12 fix phasing of rb mux data io, and add split address generation
//	inc zrptr at loadsend mux by simple rewiring of mux inputs, loadtlut.
//	add inports finishd1/2; killwe0/1a/b; add rdpzrptrd[2:0] for loadsend;
//  11-15 add wrcopymode for cwmask usage in z planes mode, nxtwmaskc, rotate;
//  11-16 derive copywen from copyoutd, compares....to ms_rp.v for cwmask.
//	and input alphacompen, ccalpha, wrcsize8/16_buf/output copywen;
//  11-17 add inputs rbc/zwptrn for ldc/zbufwen for hold time (generate in ms_rp
//	as half phase earlier, negedge clock registers, add addrxi toggling.
//	kill selrbcw/rbzw activity for selcwmask/selzwmask high, for rbaddress.
//  11-20 mod ccalpha to blendalpha for copymode; add dithalpha/dithalphaen in;
//  11-21 add stallwptr in, for killing rdpwe's;
//  11-22 reswizzle zwmask output;
//  11-28 mod right major cwmask swizzle; to do:  zwmask;
//  11-29 mod rbaddr init to not overflow at prep time
//  12-1 mod stallrwen to hold if rbphase; add hold time to din/addr0,1
//  12-2 another mod to above, to hold after transition out of idle state;  3 way case
//  	also delay conflict resolution state machine until after stallptr;
//  12-6 mod phaseinvert to fix read c/z bugs right major;
//	also add observation wires:  din128, dout128, transp_c/zbufr128;
//	also, create rdprcolorin, OR in 3b color !rmwenreadc for no readc case;
//  12-7 revise transp_c/zbufw for synopsys timing loop;
//  12-8 fix fields for 16b color reads; fix setting covg=7 for 8bI extraction;
//		revise all 6 transparent latches for synopsys; (6x144b)
//  12-13 fix 32b RGB insertion fields;
//  12-14 mod copymode 8b alphacompare to mask if value is zero;
//  12-19 undo above, to allow arbitrary ref compare;  add latches (mike)
//  12-27 cleanup of clock domains and add reset of regs startd/addrxdec/addrxi
//  1-3  mod rdprdepthd to force zread to blender to hex 3fff0 if !enzcompare;
//		add inport rmwenreadz;
//  1-4 add inport test_mode1 to kill rdram we into spanbuf;
//  1-9 add wire extfn/instantiate extphaser negedge dff;
//  1-10 fix ordering of 4-way spanbuf c/z r/w conflict state machine;
//  1-24 test version for elimination of half cycle stopgclock path to ndff
//		by changing 8/10b latches to be clock low transparent;
//  1-25 add delay to outputs ldc/zbufwen, c/zbufwin for sim skew reasons;
//  2-2  add inport start4ms, use to qualify extfn;
//              SECOND TAPEOUT MODS
//      3-30-95  add new ports rp => si:  limitcw, limitzw (timing paths);
//		remove stallwptr port;
//		replace ndff with ms_latch_l.v (timing path); add extphaserd;
//	4-4-94  add extphasere for delay (latch timing margin)
//	6-9-95  mod ms_latch8n/10n instantiations for hold time fix port changes;

`timescale 1ns/1ns

module ms_si(clock, start_gclk, reset_l, stopgclock,
	rbphase, start, dma_read_en, rdpwcolor, rdpwdepth,
	dout, selrbcr, selrbzr, selrbcw, selrbzw,
	rmwenreadc, rmwenreadz, rmwrgbmode, dbus_din, ebus_din,
	rdpreqcr, rdpreqzr, rdpreqcw, rdpreqzw, enrbwe, selcwmask, selzwmask,
	wrfillcolor, rbcrptr, rbzrptr, rbcwptr, rbzwptr, rdcxi, rdzxi, rdxdec,
	wrcxi, wrzxi, wrxdec, rmwcsize8, rmwcsize16, rmwcsize32,
	wrfillmode, cwmask, wrcopymode_buf, rdpcwptrn, rdpzwptrn,
	zwmask, wrcopymode, wrcsize8_buf, wrcsize16_buf,
	rdpcrptrsb, rdpzrptrsb, rdpcwptrsbc, rdpzwptrsbc, rdprpixc, rdprpixz,
	rdpwpixc, rdpwpixz, rmwcopymode, rmwloadtlut, load_dve,
	finishd1, finishd2, alphacompen, blendalpha, dithalpha, dithalphaen,
	stallptr, test_mode1, start4ms, limitcw, limitzw,
	
	copy_load,

	dbus_dout, ebus_dout, din, dataload,
	rdprcolor, rdprdepthd, addr0, addr1, we0, we1,
	stallphase, stallrw, copywen);

`include "ms.vh"

input clock;					// system clock
input start_gclk;
input reset_l;					// system reset
input stopgclock;

input rbphase;					//rdram memory usage phase
input start;
//add tristate stuff, from jeff
//input data_out_en;
input dma_read_en;
input [63:0] dbus_din;
input [7:0] ebus_din;
input [26:0] rdpwcolor;				//delayed write color from ms_rp
input [17:0] rdpwdepth;				//delayed write depth from ms_rp
input [143:0] dout;				//data from spanbuf
input selrbcr;					//address select/init
input selrbzr;
input selrbcw;
input selrbzw;
input rmwrgbmode;
input rmwenreadc;
input rmwenreadz;
input rdpreqcr;					//actual rdp r/w requests to rf
input rdpreqzr;
input rdpreqcw;
input rdpreqzw;
input enrbwe;					//enable we for rdram writes
input selcwmask;
input selzwmask;
input [31:0] wrfillcolor;
input [3:0] rbcrptr;
input [3:0] rbzrptr;
input [3:0] rbcwptr;
input [3:0] rbzwptr;
input [25:0] rdcxi;				//want rdcxi[3:3] for wordsel
input [25:0] rdzxi;
input rdxdec;
input [25:0] wrcxi;
input [25:0] wrzxi;
input wrxdec;
input rmwcsize8;
input rmwcsize16;
input rmwcsize32;
input wrfillmode;
input [63:0] cwmask;
input [31:0] zwmask;				//replicate in pairs for z
input [6:0] rdpcrptrsb;				//byte ptrs for rdp r/w
input [6:0] rdpzrptrsb;				//valid for spanbuf rd, or
input [6:0] rdpcwptrsbc;			//write insert; as well as
input [6:0] rdpzwptrsbc;			//rd extract and spanbuf wr
input [6:0] rdpcwptrn;
input [6:0] rdpzwptrn;
input rdprpixc;					//validcycle & validphase at
input rdprpixz;					//time r/w c/z spanbuf in pipe
input rdpwpixc;					//also fn of enread/enwrite c/z?
input rdpwpixz;
input rmwcopymode;				//copy mode opcode
input rmwloadtlut;				//if load, tlut mode invoked
input load_dve;
input finishd2, finishd1;
input wrcopymode;
input alphacompen;
input [7:0] blendalpha, dithalpha;
input wrcopymode_buf, wrcsize8_buf, wrcsize16_buf;
input dithalphaen;
input stallptr;
input test_mode1;
input start4ms;
input limitcw, limitzw;

input [63:0] copy_load;				//tristate bus load/copy data

output [63:0] dbus_dout;
output [7:0] ebus_dout;
output [143:0] din;				//data to spanbuf
output [26:0] rdprcolor;			//read color to blend unit
output [17:0] rdprdepthd;			//read depth to blend unit
output [3:0] addr0;				//address bank 0
output [3:0] addr1;				//address bank 1
output we0;					//write enable bank 0
output we1;					//write enable bank 1
output stallphase;				//stall for rdp r/w at rbphase
output stallrw;					//stall at rdp r/w c/z conflict
output [63:0] dataload;				//load data to tmem driver
output [7:0] copywen;

// input/output registers
//	clock domain
reg [71:0] rbdataio;				//input rdram read word
//	gclock domain
reg [26:0] rdprcolorin;
reg [17:0] rdprdepth;				//depth out from extraction
reg [17:0] rdprdepthd;				//depth out to blend, delayed

// internal registers
//		clock domain
reg extphase;					//state of rdram phase start
//reg extphaser;
reg extphaserd;
reg phaseinvert;				//odd word initialization
reg [3:0] rbaddr0;
reg [3:0] rbaddr1;
reg encw;
reg enzw;
reg encr;
reg enzr;
reg stallrwen;
reg killwe0a, killwe1a;
reg killwe0b, killwe1b;
reg startd, addrxdec, addrxi;
reg [143:0] rdpdataw_d;				//XXX

//RDP SPANBUF ACCESS CONFLICT RESOLUTION STATE MACHINE
reg [3:0] statec;
parameter
        state_firstwr           =4'h1,
        state_wrz              =4'h2,
        state_rdc              =4'h4,
        state_rdz              =4'h8;

// synopsys translate_off
`ifdef MSPAN_MON
reg [7:0] firstwr_arcs;
reg [3:0] wrz_arcs;
reg [2:0] rdc_arcs;
`endif
// synopsys translate_on

//		gclock domain
reg [63:0] loadsave;
reg [63:0] loadsend;
reg [63:0] copybuf;
reg [2:0] rdpzrptrd;
reg [63:0] copyout;
reg [63:0] copyoutd;
reg [7:0] copywen;

// pseudo registers

reg [26:0] rdprcolor;                           //color out to blend

reg [31:0] zwmask3;
reg [3:0] addr0;
reg [3:0] addr1;
reg [3:0] rdpaddr;
reg stallrw;
reg stallphase;
wire rbwe0;
wire rbwe1;
reg rdpwe;
reg ldcbufr;
reg ldzbufr;
reg [143:0] rdpdataw;
reg [35:0] cpixw;
reg [15:0] ldcbufw;
reg [15:0] ldzbufw;
reg [15:0] ldcbufwen;
reg [15:0] ldzbufwen;
reg [143:0] cbufwin;
reg [143:0] zbufwin;
reg [63:0] loadsavein;
reg [0:63] cwmask3;
reg [63:0] cwmask2;
reg [35:0] cpixr;
reg [31:0] zwmask2;
reg [7:0] ebus_dout;
reg [63:0] dbus_dout;

reg [63:0] dataload, copydin;

reg [6:0] rdpcrptr, rdpzrptr, rdpcwptr, rdpzwptr;
wire extphasere;
wire extfn; 				//added for negedge dff input assign
//reg [143:0] ldcbuf144, ldzbuf144;

// transparent latches got replaced;
wire [143:0] transp_doutd; //ld=rbphase	in=dout	input: spanbuf read to rbwrite
wire [71:0] transp_rb_hi; //ld=!extphase	in=rbdataio hi
wire [71:0] transp_rb_lo;  //ld=extphase	in=rbdataio low
wire [143:0] transp_cbufw; //ld=ldcbufwen	in=cpixw
wire [143:0] transp_zbufw; //ld=ldzbufwen	in=zpixw   //use for copy also
wire [143:0] transp_cbufr; //ld=ldcbufr	in=dout
wire [143:0] transp_zbufr; //ld=ldzbufr	in=dout		//used for load, too

//wires
//the following wires and assigns are just for ease of observability,
//by allowing copy data of bytes versus rdram data of nytes...

wire [63:0] rbdataio64;
wire [127:0] transp_doutd128, transp_cbufw128, transp_zbufw128;
wire [127:0] din128, dout128, transp_zbufr128, transp_cbufr128;
wire extphaser = extfn;

assign rbdataio64 = {rbdataio[71:56], rbdataio[53:38],
		rbdataio[35:20], rbdataio[17:2]};

assign transp_doutd128 = {transp_doutd[143:128], transp_doutd[125:110], transp_doutd[107:92], transp_doutd[89:74], transp_doutd[71:56], transp_doutd[53:38], transp_doutd[35:20], transp_doutd[17:2]};

assign transp_cbufw128 = {transp_cbufw[143:128], transp_cbufw[125:110], transp_cbufw[107:92], transp_cbufw[89:74], transp_cbufw[71:56], transp_cbufw[53:38], transp_cbufw[35:20], transp_cbufw[17:2]};

assign transp_zbufw128 = {transp_zbufw[143:128], transp_zbufw[125:110], transp_zbufw[107:92], transp_zbufw[89:74], transp_zbufw[71:56], transp_zbufw[53:38], transp_zbufw[35:20], transp_zbufw[17:2]};

assign din128 = {din[143:128], din[125:110], din[107:92], din[89:74], din[71:56], din[53:38], din[35:20], din[17:2]};

assign dout128 = {dout[143:128], dout[125:110], dout[107:92], dout[89:74], dout[71:56], dout[53:38], dout[35:20], dout[17:2]};

assign transp_cbufr128 = {transp_cbufr[143:128], transp_cbufr[125:110], transp_cbufr[107:92], transp_cbufr[89:74], transp_cbufr[71:56], transp_cbufr[53:38], transp_cbufr[35:20], transp_cbufr[17:2]};

assign transp_zbufr128 = {transp_zbufr[143:128], transp_zbufr[125:110], transp_zbufr[107:92], transp_zbufr[89:74], transp_zbufr[71:56], transp_zbufr[53:38], transp_zbufr[35:20], transp_zbufr[17:2]};

//BUS IO CONNECTIVITY

always @(loadsend) begin
	dataload <= loadsend;
	copydin <= loadsend;
end

always @(rdprcolorin or rmwenreadc) begin
	rdprcolor <= rdprcolorin | {24'b0, {3{!rmwenreadc}}};
end

always @(rdpcrptrsb or rdpzrptrsb or rdpcwptrsbc or rdpzwptrsbc) begin
	rdpcrptr <= rdpcrptrsb;
	rdpzrptr <= rdpzrptrsb;
	rdpcwptr <= rdpcwptrsbc;
	rdpzwptr <= rdpzwptrsbc;
end

//WRITEMASK BYTE ROTATE for starting span address

always @(cwmask or wrcxi or wrzxi or wrcopymode) begin
	case ((wrcxi[5:3] & {3{~wrcopymode}} |
			wrzxi[5:3] & {3{wrcopymode}}))
                3'h0: cwmask2 <= {cwmask[63:0]};
		3'h1: cwmask2 <= {cwmask[55:0], cwmask[63:56]};
		3'h2: cwmask2 <= {cwmask[47:0], cwmask[63:48]};
		3'h3: cwmask2 <= {cwmask[39:0], cwmask[63:40]};
		3'h4: cwmask2 <= {cwmask[31:0], cwmask[63:32]};
		3'h5: cwmask2 <= {cwmask[23:0], cwmask[63:24]};
		3'h6: cwmask2 <= {cwmask[15:0], cwmask[63:16]};
		3'h7: cwmask2 <= {cwmask[7:0], cwmask[63:8]};
	endcase
end
		
always @(cwmask2 or wrxdec) begin
  if (!wrxdec) begin
        cwmask3 <= {cwmask2[7:0], cwmask2[15:8], cwmask2[23:16], cwmask2[31:24],
		cwmask2[39:32], cwmask2[47:40], cwmask2[55:48], cwmask2[63:56]};
  end
  else begin
     cwmask3 <= {cwmask2[55:48], cwmask2[47:40], cwmask2[39:32],
	cwmask2[31:24], cwmask2[23:16], cwmask2[15:8], cwmask2[7:0],
	cwmask2[63:56]};
  end
end

always @(zwmask or wrxdec) begin
	if (wrxdec) begin
		zwmask3 <= {zwmask[3:0], zwmask[7:4],
		  zwmask[11:8], zwmask[15:12], zwmask[19:16], zwmask[23:20],
		  zwmask[27:24], zwmask[31:28]};
	end
	else begin
		zwmask3 <= zwmask;
	end
end

always @(zwmask3 or wrzxi or wrxdec) begin
        case (wrzxi[5:3] ^ {3{wrxdec}})
                3'h0: zwmask2 <= {zwmask3[31:0]};
                3'h1: zwmask2 <= {zwmask3[27:0], zwmask3[31:28]};
                3'h2: zwmask2 <= {zwmask3[23:0], zwmask3[31:24]};
                3'h3: zwmask2 <= {zwmask3[19:0], zwmask3[31:20]};
                3'h4: zwmask2 <= {zwmask3[15:0], zwmask3[31:16]};
                3'h5: zwmask2 <= {zwmask3[11:0], zwmask3[31:12]};
                3'h6: zwmask2 <= {zwmask3[7:0], zwmask3[31:8]};
                3'h7: zwmask2 <= {zwmask3[3:0], zwmask3[31:4]};
        endcase
end

//C PIXEL EXTRACTION (to register rdprcolorin) part I

//32b case:  only take 8883 out of 8 10 8 10 fields
//first extract 36b field into cpixr, then do formatting into rdprcolorin
always @(rmwcsize32 or rmwcsize16 or rdpcrptr or transp_cbufr) begin
        if (rmwcsize32) begin
                if (rdpcrptr[3:2] == 'h0) begin
                        cpixr <= transp_cbufr[143:108];
                end
                else if (rdpcrptr[3:2] == 'h1) begin
                        cpixr <= transp_cbufr[107:72];
                end
                else if (rdpcrptr[3:2] == 'h2) begin
                        cpixr <= transp_cbufr[71:36];
                end
                else if (rdpcrptr[3:2] == 'h3) begin
                        cpixr <= transp_cbufr[35:0];
                end
                else begin
                        cpixr <= 36'bx;
                end

        end
//16b IA case:  only take 8 3 out of 8 10 and rep into 8 8 8 3
//extract 8 10 into cpixr[17:0], then format into rdprcolorin later
//16b RGB case:  similar except formatting step at end
        else if (rmwcsize16) begin
                if (rdpcrptr[3:1] == 'h0) begin
                        cpixr <= transp_cbufr[143:126];
                end
                else if (rdpcrptr[3:1] == 'h1) begin
                        cpixr <= {transp_cbufr[125:108]};
                end
                else if (rdpcrptr[3:1] == 'h2) begin
                        cpixr <= {transp_cbufr[107:90]};
                end
                else if (rdpcrptr[3:1] == 'h3) begin
                        cpixr <= {transp_cbufr[89:72]};
                end
                else if (rdpcrptr[3:1] == 'h4) begin
                        cpixr <= {transp_cbufr[71:54]};
                end
                else if (rdpcrptr[3:1] == 'h5) begin
                        cpixr <= {transp_cbufr[53:36]};
                end
                else if (rdpcrptr[3:1] == 'h6) begin
                        cpixr <= {transp_cbufr[35:18]};
                end
                else if (rdpcrptr[3:1] == 'h7) begin
                        cpixr <= {transp_cbufr[17:0]};
                end
                else begin
                        cpixr <= 36'bx;
                end
        end
        else begin
                if (rdpcrptr[3:0] == 'h0) begin
                        cpixr <= transp_cbufr[143:136];
                end
                else if (rdpcrptr[3:0] == 'h1) begin
                        cpixr <= transp_cbufr[135:128];
                end
                else if (rdpcrptr[3:0] == 'h2) begin
                        cpixr <= transp_cbufr[125:118];
                end
                else if (rdpcrptr[3:0] == 'h3) begin
                        cpixr <= transp_cbufr[117:110];
                end
                else if (rdpcrptr[3:0] == 'h4) begin
                        cpixr <= transp_cbufr[107:100];
                end
                else if (rdpcrptr[3:0] == 'h5) begin
                        cpixr <= transp_cbufr[99:92];
                end
                else if (rdpcrptr[3:0] == 'h6) begin
                        cpixr <= transp_cbufr[89:82];
                end
                else if (rdpcrptr[3:0] == 'h7) begin
                        cpixr <= transp_cbufr[81:74];
                end
                else if (rdpcrptr[3:0] == 'h8) begin
                        cpixr <= transp_cbufr[71:64];
                end
                else if (rdpcrptr[3:0] == 'h9) begin
                        cpixr <= transp_cbufr[63:56];
                end
                else if (rdpcrptr[3:0] == 'ha) begin
                        cpixr <= transp_cbufr[53:46];
                end
                else if (rdpcrptr[3:0] == 'hb) begin
                        cpixr <= transp_cbufr[45:38];
                end
                else if (rdpcrptr[3:0] == 'hc) begin
                        cpixr <= transp_cbufr[35:28];
                end
                else if (rdpcrptr[3:0] == 'hd) begin
                        cpixr <= transp_cbufr[27:20];
                end
                else if (rdpcrptr[3:0] == 'he) begin
                        cpixr <= transp_cbufr[17:10];
                end
                else if (rdpcrptr[3:0] == 'hf) begin
                        cpixr <= transp_cbufr[9:2];
                end
                else begin
                        cpixr <= 36'bx;
                end
        end
end

// SPANBUF ADDRESS MUX

//******handle load of tex load buffer later**********

always @(rdpreqcr or rdpreqzr or rdpreqcw or rdpreqzw or
		rdpcwptr or rdpzwptr or rdpcrptr or rdpzrptr or
		transp_cbufw or transp_zbufw or
   		encw or enzw or encr or enzr or limitcw or limitzw) begin
	if (rdpreqcw & encw) begin
		rdpaddr <= {1'b0, rdpcwptr[6:4]};
		rdpwe <= !limitcw;
		ldcbufr <= low;
                ldzbufr <= low;
		rdpdataw <= transp_cbufw;
	end
        else if (rdpreqzw & enzw) begin
                rdpaddr <= {1'b1, rdpzwptr[6:4]};
		rdpwe <= !limitzw;
		ldcbufr <= low;
                ldzbufr <= low;
		rdpdataw <= transp_zbufw;
        end
        else if (rdpreqcr & encr) begin
                rdpaddr <= {1'b0, rdpcrptr[6:4]};
		rdpwe <= low;
		ldcbufr <= high;
                ldzbufr <= low;
                rdpdataw <= 144'bx;
        end
        else if (rdpreqzr & enzr) begin
                rdpaddr <= {1'b1, rdpzrptr[6:4]};
		rdpwe <= low;
		ldcbufr <= low;
                ldzbufr <= high;
                rdpdataw <= 144'bx;
        end
	else begin
		rdpaddr <= 4'bx;
		rdpwe <= low;
		ldcbufr <= low;
                ldzbufr <= low;
                rdpdataw <= 144'bx;
	end
end

//transparent latches, here we come:

//SPANBUF DATA, WE MUXING

assign rbwe0 = enrbwe & !((killwe0a || killwe0b) & finishd2 & rbphase) & !test_mode1;
assign rbwe1 = enrbwe & !((killwe1a || killwe1b) & finishd2 & rbphase) & !test_mode1;
assign din = rbphase? rdpdataw_d : {transp_rb_hi, transp_rb_lo};
assign we0 = rbphase? rbwe0 : rdpwe;
assign we1 = rbphase? rbwe1 : rdpwe;

ms_latch144 transp_doutd_lat (.d_out(transp_doutd), .clk(clock), .g(rbphase),
      	       	     	      .d_in(dout));
ms_latch72 transp_rb_lo_lat (.d_out(transp_rb_lo), .clk(clock), .g(~extphaserd),
      	       	     	      .d_in(rbdataio[71:0]));
ms_latch72 transp_rb_hi_lat (.d_out(transp_rb_hi), .clk(clock), .g(extphaserd),
      	       	     	      .d_in(rbdataio[71:0]));

ms_latch8n transp_zbufw_lat8_15(.d_out(transp_zbufw[143:136]), .clk(clock),
      	       	     	      .g(ldzbufwen[15]), .d_in(zbufwin[143:136]));
ms_latch10n transp_zbufw_lat10_14(.d_out(transp_zbufw[135:126]), .clk(clock),
      	       	     	      .g(ldzbufwen[14]), .d_in(zbufwin[135:126]));
ms_latch8n transp_zbufw_lat8_13(.d_out(transp_zbufw[125:118]), .clk(clock),
      	       	     	      .g(ldzbufwen[13]), .d_in(zbufwin[125:118]));
ms_latch10n transp_zbufw_lat10_12(.d_out(transp_zbufw[117:108]), .clk(clock),
      	       	     	      .g(ldzbufwen[12]), .d_in(zbufwin[117:108]));
ms_latch8n transp_zbufw_lat8_11(.d_out(transp_zbufw[107:100]), .clk(clock),
      	       	     	      .g(ldzbufwen[11]), .d_in(zbufwin[107:100]));
ms_latch10n transp_zbufw_lat10_10(.d_out(transp_zbufw[99:90]), .clk(clock),
      	       	     	      .g(ldzbufwen[10]), .d_in(zbufwin[99:90]));
ms_latch8n transp_zbufw_lat8_9(.d_out(transp_zbufw[89:82]), .clk(clock),
      	       	     	      .g(ldzbufwen[9]), .d_in(zbufwin[89:82]));
ms_latch10n transp_zbufw_lat10_8(.d_out(transp_zbufw[81:72]), .clk(clock),
      	       	     	      .g(ldzbufwen[8]), .d_in(zbufwin[81:72]));
ms_latch8n transp_zbufw_lat8_7(.d_out(transp_zbufw[71:64]), .clk(clock),
      	       	     	      .g(ldzbufwen[7]), .d_in(zbufwin[71:64]));
ms_latch10n transp_zbufw_lat10_6(.d_out(transp_zbufw[63:54]), .clk(clock),
      	       	     	      .g(ldzbufwen[6]), .d_in(zbufwin[63:54]));
ms_latch8n transp_zbufw_lat8_5(.d_out(transp_zbufw[53:46]), .clk(clock),
      	       	     	      .g(ldzbufwen[5]), .d_in(zbufwin[53:46]));
ms_latch10n transp_zbufw_lat10_4(.d_out(transp_zbufw[45:36]), .clk(clock),
      	       	     	      .g(ldzbufwen[4]), .d_in(zbufwin[45:36]));
ms_latch8n transp_zbufw_lat8_3(.d_out(transp_zbufw[35:28]), .clk(clock),
      	       	     	      .g(ldzbufwen[3]), .d_in(zbufwin[35:28]));
ms_latch10n transp_zbufw_lat10_2(.d_out(transp_zbufw[27:18]), .clk(clock),
      	       	     	      .g(ldzbufwen[2]), .d_in(zbufwin[27:18]));
ms_latch8n transp_zbufw_lat8_1(.d_out(transp_zbufw[17:10]), .clk(clock),
      	       	     	      .g(ldzbufwen[1]), .d_in(zbufwin[17:10]));
ms_latch10n transp_zbufw_lat10_0(.d_out(transp_zbufw[9:0]), .clk(clock),
      	       	     	      .g(ldzbufwen[0]), .d_in(zbufwin[9:0]));

ms_latch8n transp_cbufw_lat8_15(.d_out(transp_cbufw[143:136]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[15]), .d_in(cbufwin[143:136]));
ms_latch10n transp_cbufw_lat10_14(.d_out(transp_cbufw[135:126]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[14]), .d_in(cbufwin[135:126]));
ms_latch8n transp_cbufw_lat8_13(.d_out(transp_cbufw[125:118]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[13]), .d_in(cbufwin[125:118]));
ms_latch10n transp_cbufw_lat10_12(.d_out(transp_cbufw[117:108]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[12]), .d_in(cbufwin[117:108]));
ms_latch8n transp_cbufw_lat8_11(.d_out(transp_cbufw[107:100]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[11]), .d_in(cbufwin[107:100]));
ms_latch10n transp_cbufw_lat10_10(.d_out(transp_cbufw[99:90]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[10]), .d_in(cbufwin[99:90]));
ms_latch8n transp_cbufw_lat8_9(.d_out(transp_cbufw[89:82]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[9]), .d_in(cbufwin[89:82]));
ms_latch10n transp_cbufw_lat10_8(.d_out(transp_cbufw[81:72]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[8]), .d_in(cbufwin[81:72]));
ms_latch8n transp_cbufw_lat8_7(.d_out(transp_cbufw[71:64]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[7]), .d_in(cbufwin[71:64]));
ms_latch10n transp_cbufw_lat10_6(.d_out(transp_cbufw[63:54]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[6]), .d_in(cbufwin[63:54]));
ms_latch8n transp_cbufw_lat8_5(.d_out(transp_cbufw[53:46]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[5]), .d_in(cbufwin[53:46]));
ms_latch10n transp_cbufw_lat10_4(.d_out(transp_cbufw[45:36]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[4]), .d_in(cbufwin[45:36]));
ms_latch8n transp_cbufw_lat8_3(.d_out(transp_cbufw[35:28]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[3]), .d_in(cbufwin[35:28]));
ms_latch10n transp_cbufw_lat10_2(.d_out(transp_cbufw[27:18]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[2]), .d_in(cbufwin[27:18]));
ms_latch8n transp_cbufw_lat8_1(.d_out(transp_cbufw[17:10]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[1]), .d_in(cbufwin[17:10]));
ms_latch10n transp_cbufw_lat10_0(.d_out(transp_cbufw[9:0]), 
				.clk(clock),
      	       	     	      .g(ldcbufwen[0]), .d_in(cbufwin[9:0]));

//problem:  want neg clk/gclk below;  must work for conflict case
// (e.g. ldc/zbuf one clk only, gclk hi stuck) as well as normal stall cases
// (e.g. ldc/zbuf multiclock, gclk stuck hi).  OK to use clk?

ms_latch144 transp_cbufr_lat (.d_out(transp_cbufr), .clk(clock), .g(ldcbufr),
                              .d_in(dout));

ms_latch144 transp_zbufr_lat (.d_out(transp_zbufr), .clk(clock), .g(ldzbufr),
                              .d_in(dout));


//DETECT CASES OF ACCESS CONFLICTS

always @(rdpreqcr or rdpreqzr or rdpreqcw or rdpreqzw or stallrwen) begin
	if ((rdpreqcr & rdpreqzr) || (rdpreqcw & rdpreqzw) ||
		((rdpreqcr || rdpreqzr) & (rdpreqcw || rdpreqzw))) begin
		stallrw <= stallrwen;
	end
	else begin
		stallrw <= low;
	end
end

//detect case of wrong phase for rdp r/w access to spanbuf

always @(rdpreqcr or rdpreqzr or rdpreqcw or rdpreqzw or rbphase) begin
        if (rbphase & (rdpreqcr || rdpreqzr || rdpreqcw || rdpreqzw)) begin
                stallphase <= high;
        end
        else begin
                stallphase <= low;
        end
end


always @(rbphase or rbaddr0 or rbaddr1 or rdpaddr) begin
	if (rbphase) begin
		addr0 <= rbaddr0;
		addr1 <= rbaddr1;
	end
	else if (!rbphase) begin
		addr0 <= rdpaddr;
		addr1 <= rdpaddr;
	end
	else begin
		addr0 <= 4'bx;
		addr1 <= 4'bx;
	end
end

//LOAD data path input mux:  cut down to 64b to save gates;  add mux in rd path

always @(transp_zbufr or rdpzrptr) begin
	if (!rdpzrptr[3]) begin
		loadsavein <= {transp_zbufr[143:128], transp_zbufr[125:110],
			transp_zbufr[107:92], transp_zbufr[89:74]};
	end
	else begin
		loadsavein <= {transp_zbufr[71:56], transp_zbufr[53:38],
			transp_zbufr[35:20], transp_zbufr[17:2]};
	end
end

//Z PIXEL INSERTION (to transparent latch transp_zbufw)
//note:  this delay is in critical path thru latch into reg write...tsu=3ns

always @(rmwcopymode or rdpzwptrn or rdpwdepth or rdpwpixz or ldzbufw or
				copyout or rmwcsize8 or rmwcsize16) begin
        if (!rmwcopymode) begin
		zbufwin <= {8{rdpwdepth}};

                if (rdpzwptrn[3:1] == 'h0) begin
			ldzbufw <= 'hc000;
		end
                else if (rdpzwptrn[3:1] == 'h1) begin
			ldzbufw <= 'h3000;
                end
                else if (rdpzwptrn[3:1] == 'h2) begin
			ldzbufw <= 'h0c00;
                end
                else if (rdpzwptrn[3:1] == 'h3) begin
                        ldzbufw <= 'h0300;
                end
                else if (rdpzwptrn[3:1] == 'h4) begin
			ldzbufw <= 'h00c0;
                end
                else if (rdpzwptrn[3:1] == 'h5) begin
                        ldzbufw <= 'h0030;
                end
                else if (rdpzwptrn[3:1] == 'h6) begin
			ldzbufw <= 'h000c;
                end
                else if (rdpzwptrn[3:1] == 'h7) begin
                        ldzbufw <= 'h0003;
                end
                else begin
                        ldzbufw <= 16'bx;
                end

	end
	else if (rmwcopymode) begin
		zbufwin <= {copyout[63:48], copyout[48], copyout[48],
			copyout[47:32], copyout[32], copyout[32],
                        copyout[31:16], copyout[16], copyout[16],
                        copyout[15:0], copyout[0], copyout[0],
			copyout[63:48], copyout[48], copyout[48],
                        copyout[47:32], copyout[32], copyout[32],
                        copyout[31:16], copyout[16], copyout[16],
                        copyout[15:0], copyout[0], copyout[0]};
		if (rmwcsize16 & rdpzwptrn[3]) begin
			ldzbufw <= 'h00ff;
		end
		else if (rmwcsize16 & !rdpzwptrn[3]) begin
			ldzbufw <= 'hff00;
		end
		else if (rmwcsize8 & (rdpzwptrn[3:2] == 'h0)) begin
			ldzbufw <= 'hf000;
		end
                else if (rmwcsize8 & (rdpzwptrn[3:2] == 'h1)) begin
                        ldzbufw <= 'h0f00;
                end
                else if (rmwcsize8 & (rdpzwptrn[3:2] == 'h2)) begin
                        ldzbufw <= 'h00f0;
                end
                else if (rmwcsize8 & (rdpzwptrn[3:2] == 'h3)) begin
                        ldzbufw <= 'h000f;
                end
		else begin
			ldzbufw <= 16'bx;
		end
	end
	else begin
		zbufwin <= 144'bx;
		ldzbufw <= 16'bx;
	end
	ldzbufwen <= ldzbufw & {16{rdpwpixz}};
end

//C PIXEL INSERTION (to transparent latch transp_cbufw)
//note:  this delay is in critical path thru latch into reg write...tsu=3ns

//32b RGB:  first format rdpwcolor into cpixw, then demux into cbufwin

always @(rdpcwptrn or rdpwcolor or rmwcsize32 or rmwcsize16 or rmwcsize8
	or ldcbufw or rmwrgbmode or cpixw or rdpwpixc) begin
        if (rmwcsize32) begin
		cpixw <= {rdpwcolor[26:11], {2{rdpwcolor[11]}},
				rdpwcolor[10:0], 7'b0};
		cbufwin <= {4{cpixw}};
                if (rdpcwptrn[3:2] == 'h0) begin
			ldcbufw <= 'hf000;
                end
                else if (rdpcwptrn[3:2] == 'h1) begin
			ldcbufw <= 'h0f00;
                end
                else if (rdpcwptrn[3:2] == 'h2) begin
                        ldcbufw <= 'h00f0;
                end
                else if (rdpcwptrn[3:2] == 'h3) begin
                        ldcbufw <= 'h000f;
                end
		else begin
			ldcbufw <= 16'bx;
		end
        end
	else if (rmwcsize16) begin
		if (!rmwrgbmode) begin
			cpixw <= {rdpwcolor[26:19], rdpwcolor[2:0], 7'h0};
		end
		else if (rmwrgbmode) begin
			cpixw <= {rdpwcolor[26:22], rdpwcolor[18:14],
				rdpwcolor[10:6], rdpwcolor[2:0]};
		end
		cbufwin <= {8{cpixw[17:0]}};

                if (rdpcwptrn[3:1] == 'h0) begin
			ldcbufw <= 'hc000;
                end
                else if (rdpcwptrn[3:1] == 'h1) begin
			ldcbufw <= 'h3000;
                end
                else if (rdpcwptrn[3:1] == 'h2) begin
                        ldcbufw <= 'h0c00;
                end
                else if (rdpcwptrn[3:1] == 'h3) begin
			ldcbufw <= 'h0300;
                end
                else if (rdpcwptrn[3:1] == 'h4) begin
                        ldcbufw <= 'h00c0;
                end
                else if (rdpcwptrn[3:1] == 'h5) begin
			ldcbufw <= 'h0030;
                end
                else if (rdpcwptrn[3:1] == 'h6) begin
                        ldcbufw <= 'h000c;
                end
                else if (rdpcwptrn[3:1] == 'h7) begin
			ldcbufw <= 'h0003;
                end
                else begin
                        ldcbufw <= 16'bx;
                end
	end
	else if (rmwcsize8) begin
		cpixw <= {rdpwcolor[26:11], {2{rdpwcolor[11]}}};
		cbufwin <= {8{cpixw[17:0]}};

                if (rdpcwptrn[3:0] == 'h0) begin
			ldcbufw <= 'h8000;
                end
                else if (rdpcwptrn[3:0] == 'h1) begin
                        ldcbufw <= 'h4000;
                end
                else if (rdpcwptrn[3:0] == 'h2) begin
                        ldcbufw <= 'h2000;
                end
                else if (rdpcwptrn[3:0] == 'h3) begin
                        ldcbufw <= 'h1000;
                end
                else if (rdpcwptrn[3:0] == 'h4) begin
                        ldcbufw <= 'h0800;
                end
                else if (rdpcwptrn[3:0] == 'h5) begin
                        ldcbufw <= 'h0400;
                end
                else if (rdpcwptrn[3:0] == 'h6) begin
                        ldcbufw <= 'h0200;
                end
                else if (rdpcwptrn[3:0] == 'h7) begin
                        ldcbufw <= 'h0100;
                end
                else if (rdpcwptrn[3:0] == 'h8) begin
                        ldcbufw <= 'h0080;
                end
                else if (rdpcwptrn[3:0] == 'h9) begin
                        ldcbufw <= 'h0040;
                end
                else if (rdpcwptrn[3:0] == 'ha) begin
                        ldcbufw <= 'h0020;
                end
                else if (rdpcwptrn[3:0] == 'hb) begin
                        ldcbufw <= 'h0010;
                end
                else if (rdpcwptrn[3:0] == 'hc) begin
                        ldcbufw <= 'h0008;
                end
                else if (rdpcwptrn[3:0] == 'hd) begin
                        ldcbufw <= 'h0004;
                end
                else if (rdpcwptrn[3:0] == 'he) begin
                        ldcbufw <= 'h0002;
                end
                else if (rdpcwptrn[3:0] == 'hf) begin
                        ldcbufw <= 'h0001;
                end
		else begin
			ldcbufw <= 16'bx;
		end
	end
        else begin
                cpixw <= 36'bx;
		cbufwin <= 144'bx;
		ldcbufw <= 16'bx;
        end

	ldcbufwen <= ldcbufw & {16{rdpwpixc}};
end

//COPY DATA MUX for above data "copyout":  4x16b or 4x8b per clock
//never discard leading texel (leftmost) from tex unit, so no setup clks;
//form 64b bucket (for 8b, it's 32b replicated 2x) of texels.

always @(rmwcsize16 or rmwcsize8 or rdpzwptr or copydin or copybuf) begin
	if (rmwcsize16) begin
		if (rdpzwptr[2:1] == 'h0) begin
			copyout <= copydin;
		end
		else if (rdpzwptr[2:1] == 'h1) begin
                        copyout <= {copybuf[15:0], copydin[63:16]};
                end
                else if (rdpzwptr[2:1] == 'h2) begin
                        copyout <= {copybuf[31:0], copydin[63:32]};
                end
                else if (rdpzwptr[2:1] == 'h3) begin
                        copyout <= {copybuf[47:0], copydin[63:48]};
                end
		else begin
			copyout <= 64'bx;
		end
	end
	else if (rmwcsize8) begin
                if (rdpzwptr[1:0] == 'h0) begin
                        copyout <= {2{copydin[63:56], copydin[47:40],
				copydin[31:24], copydin[15:8]}};
                end
                else if (rdpzwptr[1:0] == 'h1) begin
                        copyout <= {2{copybuf[15:8], copydin[63:56],
				copydin[47:40], copydin[31:24]}};
                end
                else if (rdpzwptr[1:0] == 'h2) begin
                        copyout <= {2{copybuf[31:24], copybuf[15:8],
				copydin[63:56], copydin[47:40]}};
                end
                else if (rdpzwptr[1:0] == 'h3) begin
                        copyout <= {2{copybuf[47:40], copybuf[31:24],
				copybuf[15:8], copydin[63:56]}};
                end
		else begin
			copyout <= 64'bx;
		end
	end
	else begin
		copyout <= 64'bx;
	end
end

//
always @(rbdataio) begin
	dbus_dout <= {rbdataio[71:56], rbdataio[53:38], rbdataio[35:20],
				rbdataio[17:2]};
	ebus_dout <= {rbdataio[55:54], rbdataio[37:36], rbdataio[19:18],
				rbdataio[1:0]};
end

always @(posedge clock) begin
   if (reset_l == 1'b0) begin
      // resettable registers
// synopsys translate_off
`ifdef MSPAN_MON
	firstwr_arcs <= 8'b0;
	wrz_arcs <= 4'b0;
	rdc_arcs <= 3'b0;
`endif
// synopsys translate_on
      end
   else if (start_gclk) begin
        copybuf <= copydin;
	copyoutd <= copyout;
  	
	if (!alphacompen || !wrcopymode_buf) begin
		copywen <= 8'hff;
	end
	else if (alphacompen & wrcopymode_buf) begin
		if (wrcsize8_buf) begin
		  if (!dithalphaen) begin
			copywen <= ~{2{(blendalpha > copyoutd[31:24]),
				(blendalpha > copyoutd[23:16]),
				(blendalpha > copyoutd[15:8]),
				(blendalpha > copyoutd[7:0])}};
//                      copywen <= {2{(|copyoutd[31:24]),
//                              (|copyoutd[23:16]),
//                              (|copyoutd[15:8]),
//                              (|copyoutd[7:0])}};
		  end
		  else begin
			copywen <= ~{2{(dithalpha > copyoutd[31:24]),
                               ({dithalpha[1:0], dithalpha[7:2]} > copyoutd[23:16]),
                               ({dithalpha[3:0], dithalpha[7:4]} > copyoutd[15:8]),
                               ({dithalpha[5:0], dithalpha[7:6]} > copyoutd[7:0])}};
		  end
		end
		else if (wrcsize16_buf) begin
			copywen <= {{2{copyoutd[48]}}, {2{copyoutd[32]}},
					{2{copyoutd[16]}}, {2{copyoutd[0]}}};
		end
		else begin
			copywen <= 8'bx;
		end
	end
	else begin
		copywen <= 8'bx;
	end

//        rdprdepthd <= rdprdepth;   

rdprdepthd <= {(rdprdepth[17:4] & {14{rmwenreadz}}),
				rdprdepth[3:0] | ~{4{rmwenreadz}}};

//delay so c read is 2 clks later than z read

//LOAD input registers and alignment
//note:  for LOAD, we use z reads/zrbuf but we use cwmask;  fudge internally;
//latency:  same as rdp zread data (versus startspant0 received, that is...)

        loadsave <= loadsavein;
	rdpzrptrd <= rdpzrptr[2:0];

        if (!(load_dve)) begin
                loadsend <= copy_load;
        end
        else if (rdpzrptrd[2:0] == 'h0) begin
                if (!rmwloadtlut) begin
                        loadsend <= loadsave;
                end
                else begin
                        loadsend <= {4{loadsave[63:48]}};
                end
        end
        else if (rdpzrptrd[2:0] == 'h1) begin
                        loadsend <= {loadsave[55:0], loadsavein[63:56]};
        end
        else if (rdpzrptrd[2:0] == 'h2) begin
                if (!rmwloadtlut) begin
                        loadsend <= {loadsave[47:0], loadsavein[63:48]};
                end
                else begin
                        loadsend <= {4{loadsave[47:32]}};
                end
        end
        else if (rdpzrptrd[2:0] == 'h3) begin
                        loadsend <= {loadsave[39:0], loadsavein[63:40]};
        end
        else if (rdpzrptrd[2:0] == 'h4) begin
                if (!rmwloadtlut) begin
                        loadsend <= {loadsave[31:0], loadsavein[63:32]};
                end
                else begin
                        loadsend <= {4{loadsave[31:16]}};
                end
        end
        else if (rdpzrptrd[2:0] == 'h5) begin
                        loadsend <= {loadsave[23:0], loadsavein[63:24]};
        end
        else if (rdpzrptrd[2:0] == 'h6) begin
                if (!rmwloadtlut) begin
                        loadsend <= {loadsave[15:0], loadsavein[63:16]};
                end
                else begin
                        loadsend <= {4{loadsave[15:0]}};
                end
        end
        else if (rdpzrptrd[2:0] == 'h7) begin
                        loadsend <= {loadsave[7:0], loadsavein[63:8]};
        end

//for prop delay, the 3 lsb's of zrptr are constant for loads.  (tv won't know)
//**********not true for load tlut!!!*********************

//loadsavein is defined outside clock loop;  rdpzrptr loaded at stptzr-1.

//Z PIXEL EXTRACTION (to register rdprdepth):  18b per value

   if (rdprpixz) begin
        if (rdpzrptr[3:1] == 'h0) begin
                rdprdepth <= transp_zbufr[143:126];
        end
        else if (rdpzrptr[3:1] == 'h1) begin
                rdprdepth <= transp_zbufr[125:108];
        end
        else if (rdpzrptr[3:1] == 'h2) begin
                rdprdepth <= transp_zbufr[107:90];
        end
        else if (rdpzrptr[3:1] == 'h3) begin
                rdprdepth <= transp_zbufr[89:72];
        end
        else if (rdpzrptr[3:1] == 'h4) begin
                rdprdepth <= transp_zbufr[71:54];
        end
        else if (rdpzrptr[3:1] == 'h5) begin
                rdprdepth <= transp_zbufr[53:36];
        end
        else if (rdpzrptr[3:1] == 'h6) begin
                rdprdepth <= transp_zbufr[35:18];
        end
        else if (rdpzrptr[3:1] == 'h7) begin
                rdprdepth <= transp_zbufr[17:0];
        end
   end
   else if (!(rdprpixz)) begin
                rdprdepth <= rdprdepth;
   end
   else begin
                rdprdepth <= 18'bx;
   end
//C PIXEL EXTRACTION (to register rdprcolorin) part II

//32b case:  only take 8883 out of 8 10 8 10 fields
//first extract 36b field into cpixr, then do formatting into rdprcolorin
   if (rdprpixc) begin
        if (rmwcsize32) begin
                rdprcolorin <= {cpixr[35:20], cpixr[17:7]};
        end
//16b IA case:  only take 8 3 out of 8 10 and rep into 8 8 8 3
//extract 8 10 into cpixr[17:0], then format into rdprcolorin later
//16b RGB case:  similar except formatting step at end
        else if (rmwcsize16) begin
                if (!rmwrgbmode) begin
                rdprcolorin <= {cpixr[17:10], cpixr[17:10], cpixr[17:10],
                                cpixr[9:7]};
                end
                else if (rmwrgbmode) begin
                rdprcolorin <= {cpixr[17:13], 3'h0, cpixr[12:8], 3'h0,
                                cpixr[7:3], 3'h0, cpixr[2:0]};
                end
        end
        else begin
                rdprcolorin <= {cpixr[7:0], cpixr[7:0], cpixr[7:0],
                                3'h7};
        end
   end
   else if (!(rdprpixc)) begin
                rdprcolorin <= rdprcolorin;
   end
   else begin
                rdprcolorin <= 27'bx;
   end

end
end

//instantiated version of above, so we explicitly call for negedge DFF
//initial (reset) state can be arbitrary, we mod to high for simplicity of muxing OR

assign extfn = ((start & start4ms) & ~phaseinvert) || (~(start & start4ms) & ~extphaserd);

always @(posedge clock) begin
   if (reset_l == 1'b0) begin
      // resettable registers
	extphase <= low;
	phaseinvert <= low;
	extphaserd <= low;
	statec <= state_firstwr;
	encr<= high;
	enzr<= high;
	encw<= high;
	enzw<= high;
	stallrwen <= high;
//stallrwen is initially high, we use sm to temp reset after conflict resolved

      // nonresettable registers
//     	transp_cbufr <= 144'bx;
//     	transp_zbufr <= 144'bx;
//     	transp_cbufw <= 144'bx;
//     	transp_zbufw <= 144'bx;
      end
   else begin

	rdpdataw_d  <= rdpdataw;			//XXX

	extphaserd <= extphaser;

	if (phaseinvert) begin
		if (start) begin
			extphase <= low;
		end
		else begin
			extphase <= !extphase;
		end
	end
	else if (!phaseinvert) begin
		if (start) begin
			extphase <= high;
		end
		else begin
			extphase <= !extphase;
		end
	end

//check wmask formats after finish design of wmask logic
//native cwmask is in pixel byte order;  mirror within ea byte
// to get rdram format
//	via earlier always @ statement to cwmask3[0:63] <= cwmask2[63:0]

//created cwmask2 as a byte rotated function to align with start of span

	if (dma_read_en) begin
		rbdataio <= {dbus_din[63:48], ebus_din[7:6],
			dbus_din[47:32], ebus_din[5:4],
			dbus_din[31:16], ebus_din[3:2],
			dbus_din[15:0], ebus_din[1:0]};
	end
	else if (selcwmask || (wrcopymode & selzwmask)) begin
//		rbdataw <= {cwmask[7:0], cwmask[15:8],
//			2'h0, cwmask[23:16], cwmask[31:24],
//			2'h0, cwmask[39:32], cwmask[47:40],
//			2'h0, cwmask[55:48], cwmask[63:56], 2'h0};
//              rbdataw <= {cwmask2[0:15],
//			2'h0, cwmask2[16:31],
//			2'h0, cwmask2[32:47],
//			2'h0, cwmask2[48:63], 2'h0};
              rbdataio <= {cwmask3[63], cwmask3[62], cwmask3[61], cwmask3[60],
		cwmask3[59], cwmask3[58], cwmask3[57], cwmask3[56],
		cwmask3[55], cwmask3[54], cwmask3[53], cwmask3[52],
		cwmask3[51], cwmask3[50], cwmask3[49], cwmask3[48],
                        2'h0, cwmask3[47], cwmask3[46], cwmask3[45],
		cwmask3[44], cwmask3[43], cwmask3[42], cwmask3[41], cwmask3[40],
  		cwmask3[39], cwmask3[38], cwmask3[37], cwmask3[36], cwmask3[35],
		cwmask3[34], cwmask3[33], cwmask3[32], 
                        2'h0, cwmask3[31],  cwmask3[30],  cwmask3[29],
		cwmask3[28],  cwmask3[27],  cwmask3[26],  cwmask3[25],
		cwmask3[24], cwmask3[23],  cwmask3[22], cwmask3[21],
		cwmask3[20], cwmask3[19], cwmask3[18], cwmask3[17], cwmask3[16],
                        2'h0, cwmask3[15], cwmask3[14], cwmask3[13],
		cwmask3[12], cwmask3[11], cwmask3[10], cwmask3[9], cwmask3[8],
		cwmask3[7], cwmask3[6], cwmask3[5], cwmask3[4], cwmask3[3],
		cwmask3[2], cwmask3[1], cwmask3[0], 2'h0};
	end
	else if (selzwmask) begin
//		rbdataio <= {zwmask2[31], zwmask2[31], zwmask2[30],
//                  zwmask2[30], zwmask2[29], zwmask2[29], zwmask2[28], zwmask2[28],
//                2'h0, zwmask2[27], zwmask2[27], zwmask2[26],
//                  zwmask2[26], zwmask2[25], zwmask2[25], zwmask2[24], zwmask2[24],
//                zwmask2[23], zwmask2[23], zwmask2[22],
//                  zwmask2[22], zwmask2[21], zwmask2[21], zwmask2[20], zwmask2[20],
//                2'h0, zwmask2[19], zwmask2[19], zwmask2[18],
//                  zwmask2[18], zwmask2[17], zwmask2[17], zwmask2[16], zwmask2[16],
//                zwmask2[15], zwmask2[15], zwmask2[14],
//                  zwmask2[14], zwmask2[13], zwmask2[13], zwmask2[12], zwmask2[12],
//                2'h0, zwmask2[11], zwmask2[11], zwmask2[10],
//                  zwmask2[10], zwmask2[9], zwmask2[9], zwmask2[8], zwmask2[8],
//                zwmask2[7], zwmask2[7], zwmask2[6],
//                  zwmask2[6], zwmask2[5], zwmask2[5], zwmask2[4], zwmask2[4],
//                zwmask2[3], zwmask2[3], zwmask2[2],
//                  zwmask2[2], zwmask2[1], zwmask2[1], zwmask2[0], zwmask2[0]};


             rbdataio <= {zwmask2[28], zwmask2[28], zwmask2[29],
               zwmask2[29], zwmask2[30], zwmask2[30], zwmask2[31], zwmask2[31],
               zwmask2[24], zwmask2[24], zwmask2[25],
               zwmask2[25], zwmask2[26], zwmask2[26], zwmask2[27], zwmask2[27],
               2'h0, zwmask2[20], zwmask2[20], zwmask2[21],
               zwmask2[21], zwmask2[22], zwmask2[22], zwmask2[23], zwmask2[23],
               zwmask2[16], zwmask2[16], zwmask2[17],
               zwmask2[17], zwmask2[18], zwmask2[18], zwmask2[19], zwmask2[19],
               2'h0, zwmask2[12], zwmask2[12], zwmask2[13],
               zwmask2[13], zwmask2[14], zwmask2[14], zwmask2[15], zwmask2[15],
               zwmask2[8], zwmask2[8], zwmask2[9],
               zwmask2[9], zwmask2[10], zwmask2[10], zwmask2[11], zwmask2[11],
               2'h0, zwmask2[4], zwmask2[4], zwmask2[5],
               zwmask2[5], zwmask2[6], zwmask2[6], zwmask2[7], zwmask2[7],
               zwmask2[0], zwmask2[0], zwmask2[1],
               zwmask2[1], zwmask2[2], zwmask2[2], zwmask2[3], zwmask2[3],
               2'h0};

//		rbdataio <= {zwmask[0], zwmask[0], zwmask[1],
//                 zwmask[1], zwmask[2], zwmask[2], zwmask[3], zwmask[3],
//		zwmask[4], zwmask[4], zwmask[5],
//                 zwmask[5], zwmask[6], zwmask[6], zwmask[7], zwmask[7],
//		2'h0, zwmask[8], zwmask[8], zwmask[9],
//                 zwmask[9], zwmask[10], zwmask[10], zwmask[11], zwmask[11],
//     		zwmask[12], zwmask[12], zwmask[13],
//               zwmask[13], zwmask[14], zwmask[14], zwmask[15], zwmask[15],
//		2'h0, zwmask[16], zwmask[16], zwmask[17],
//                 zwmask[17], zwmask[18], zwmask[18], zwmask[19], zwmask[19],
//              zwmask[20], zwmask[20], zwmask[21],
//               zwmask[21], zwmask[22], zwmask[22], zwmask[23], zwmask[23],
//		2'h0, zwmask[24], zwmask[24], zwmask[25],
//                 zwmask[25], zwmask[26], zwmask[26], zwmask[27], zwmask[27],
//              zwmask[28], zwmask[28], zwmask[29],
//               zwmask[29], zwmask[30], zwmask[30], zwmask[31], zwmask[31],
//		2'h0};
//                rbdataio <= {zwmask[3], zwmask[3], zwmask[2],
//                  zwmask[2], zwmask[1], zwmask[1], zwmask[0], zwmask[0],
//                zwmask[7], zwmask[7], zwmask[6],
//                  zwmask[6], zwmask[5], zwmask[5], zwmask[4], zwmask[4],
//                2'h0, zwmask[11], zwmask[11], zwmask[10],
//                  zwmask[10], zwmask[9], zwmask[9], zwmask[8], zwmask[8],
//                zwmask[15], zwmask[15], zwmask[14],
//                  zwmask[14], zwmask[13], zwmask[13], zwmask[12], zwmask[12],
//                2'h0, zwmask[19], zwmask[19], zwmask[18],
//                  zwmask[18], zwmask[17], zwmask[17], zwmask[16], zwmask[16],
//                zwmask[23], zwmask[23], zwmask[22],
//                  zwmask[22], zwmask[21], zwmask[21], zwmask[20], zwmask[20],
//                2'h0, zwmask[27], zwmask[27], zwmask[26],
//                  zwmask[26], zwmask[25], zwmask[25], zwmask[24], zwmask[24],
//                zwmask[31], zwmask[31], zwmask[30],
//                  zwmask[30], zwmask[29], zwmask[29], zwmask[28], zwmask[28],
//                2'h0};
	end
	else if (wrfillmode) begin
		rbdataio <= {2{wrfillcolor[31:16], wrfillcolor[16], wrfillcolor[16],
			wrfillcolor[15:0], wrfillcolor[0], wrfillcolor[0]}};
        end
	else if ((addrxi)) begin
		rbdataio <= transp_doutd[143:72];
	end
	else if (~(addrxi)) begin
		rbdataio <= transp_doutd[71:0];
	end
	else begin
		rbdataio <= 72'bx;
	end

//must upgrade below for split addressing********************************

//the following is initialization, some variable time before xfer occurs
//but the assertion continues until a known time before xfer.

	if (selrbcr) begin
//		phaseinvert <= rdxdec ^ rdcxi[3];
		phaseinvert <= rdcxi[3];
                killwe1a <= start & !rbphase & rdxdec & rdcxi[3];
                killwe0a <= start & !rbphase & !rdxdec & !rdcxi[3];
                killwe0b <= start & rbphase & !rdxdec & rdcxi[3];
                killwe1b <= start & rbphase & rdxdec & !rdcxi[3];
		addrxdec <= rdxdec;
		addrxi <= rdcxi[3];
		rbaddr0 <= {1'b0, (rbcrptr[2:0] +
			{2'h0, start & rbphase & rdcxi[3] & !rdxdec})};
                rbaddr1 <= {1'b0, (rbcrptr[2:0] +
                        {2'h0, start & rbphase & !rdcxi[3] & rdxdec})};
	end
	else if (selrbzr) begin
//		phaseinvert <= rdxdec ^ rdzxi[3];
		phaseinvert <= rdzxi[3];
		killwe1a <= start & !rbphase & rdxdec & rdzxi[3];
		killwe0a <= start & !rbphase & !rdxdec & !rdzxi[3];
                killwe0b <= start & rbphase & !rdxdec & rdzxi[3];
                killwe1b <= start & rbphase & rdxdec & !rdzxi[3];
		addrxdec <= rdxdec;
		addrxi <= rdzxi[3];
		rbaddr0 <= {1'b1, (rbzrptr[2:0] +
                        {2'h0, start & rbphase & rdzxi[3] & !rdxdec})};
                rbaddr1 <= {1'b1, (rbzrptr[2:0] +
                        {2'h0, start & rbphase & !rdzxi[3] & rdxdec})};
	end
	else if (selrbcw & !(selcwmask || selzwmask)) begin
		phaseinvert <= wrxdec ^ wrcxi[3];
		addrxdec <= wrxdec;
		addrxi <= wrcxi[3];
		rbaddr0 <= {1'b0, (rbcwptr[2:0] +
                        {2'h0, start & rbphase & wrcxi[3] & !wrxdec})};
                rbaddr1 <= {1'b0, (rbcwptr[2:0] +
                        {2'h0, start & rbphase & !wrcxi[3] & wrxdec})};
        end
        else if (selrbzw & !(selcwmask || selzwmask)) begin
                phaseinvert <= wrxdec ^ wrzxi[3];
		addrxdec <= wrxdec;
		addrxi <= wrzxi[3];
		rbaddr0 <= {1'b1, (rbzwptr[2:0] +
                        {2'h0, start & rbphase & wrzxi[3] & !wrxdec})};
                rbaddr1 <= {1'b1, (rbzwptr[2:0] +
                        {2'h0, start & rbphase & !wrzxi[3] & wrxdec})};
        end
//****must modify below to increment at rbphase or whatever, not static***
	else begin
		killwe0a <= killwe0a;
		killwe1a <= killwe1a;
                killwe0b <= killwe0b;
                killwe1b <= killwe1b;
		addrxdec <= addrxdec;
		addrxi <= !addrxi;
		phaseinvert <= phaseinvert;
		rbaddr0 <= {rbaddr0[3], (rbaddr0[2:0] +
				{2'h0, rbphase & !(startd & addrxdec & addrxi)})};
                rbaddr1 <= {rbaddr1[3], (rbaddr1[2:0] +
				{2'h0, rbphase & !(startd & !addrxdec & !addrxi)})};
	end

	startd <= start;

//above, for split addressing, phaseinvert is used to modify extphase so that
//it correctly implies data ordering in/out muxing from/to rdram;  here we
//mod addresses so as to have split address cases, we init addresses as fn of
//xdec, xi[3], and whether start is aligned with rbphase.  if we have to init
//address to -1 (relative), we instead merely inhibit first increment, so that
//there is no issue of having to disable WE of underflowed address.  when we have
//to init it to +1, we do it above as initial value, and we still have to kill
//the WE early for that case alone, to be done.

//RDP SPANBUF ACCESS CONFLICT RESOLUTION STATE MACHINE

//note: the assumption here is that the first prioritized event in the conflict
//happens, during which stallrw is asserted. so, in this state
//machine we need to determine what this first event was, and then take it from
//there as needed, stalling 2 clocks per.
//priority is cw, zw, cr, zr (arbitrary, since clock is stopped and ptrs freeze)

//note that the actual arbitration mux transitions occur during rbphase,
//so as not to enter into critical path.  but the normal path is probably
//about the same--and of course timing analyzer isn't smart enuf to know diff.

	case (statec)
		state_firstwr : begin
//			stallrwen <= !stopgclock || stallrwen & rbphase;

			if (stallptr) begin
				statec <= state_firstwr;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= 1'b1 | firstwr_arcs;		    // A
`endif
// synopsys translate_on
				stallrwen <= stallrwen;
                                encw <= high;
                                enzw <= high;
                                encr <= high;
                                enzr <= high;
			end
			else if (stallrw & rdpreqcw & rdpreqzw & !rbphase) begin
				statec <= state_wrz;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 1'b0 } | firstwr_arcs;	    // B
`endif
// synopsys translate_on
				encw <= low;
			end
			else if (stallrw & rdpreqcw & rdpreqcr & !rbphase) begin
				statec <= state_rdc;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 2'b0 } | firstwr_arcs;	    // C
`endif
// synopsys translate_on
				encw <= low;
			end
			else if (stallrw & rdpreqcw & rdpreqzr & !rbphase) begin
				statec <= state_rdz;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 3'b0 } | firstwr_arcs;	    // D
`endif
// synopsys translate_on
				encw <= low;
			end
                        else if (stallrw & rdpreqzw & rdpreqcr & !rbphase) begin
                                statec <= state_rdc;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 4'b0 } | firstwr_arcs;	    // E
`endif
// synopsys translate_on
                                enzw <= low;
                        end
                        else if (stallrw & rdpreqzw & rdpreqzr & !rbphase) begin
                                statec <= state_rdz;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 5'b0 } | firstwr_arcs;	    // F
`endif
// synopsys translate_on
                                enzw <= low;
                        end
                        else if (stallrw & rdpreqcr & rdpreqzr & !rbphase) begin
                                statec <= state_rdz;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 6'b0 } | firstwr_arcs;	    // G
`endif
// synopsys translate_on
                                encr <= low;
                        end
                        else begin
                                statec <= state_firstwr;
// synopsys translate_off
`ifdef MSPAN_MON
firstwr_arcs <= { 1'b1, 7'b0 } | firstwr_arcs;	    // H
`endif
// synopsys translate_on
                        stallrwen <= !stopgclock || stallrwen & rbphase;
                                encw <= high;
                                enzw <= high;
                                encr <= high;
                                enzr <= high;
                        end
		end

		state_wrz : begin
			if (rdpreqcr & !rbphase) begin
                                statec <= state_rdc;
// synopsys translate_off
`ifdef MSPAN_MON
wrz_arcs <= 1'b1 | firstwr_arcs;		    // A
`endif
// synopsys translate_on
                                enzw <= low;
                        end
                        else if (rdpreqzr & !rbphase) begin
                                statec <= state_rdz;
// synopsys translate_off
`ifdef MSPAN_MON
wrz_arcs <= { 1'b1, 1'b0 } | firstwr_arcs;	    // B
`endif
// synopsys translate_on
                                enzw <= low;
                        end
                        else if (!rdpreqcr & !rdpreqzr & rbphase) begin
                                statec <= state_firstwr;
// synopsys translate_off
`ifdef MSPAN_MON
wrz_arcs <= { 1'b1, 2'b0 } | firstwr_arcs;	    // C
`endif
// synopsys translate_on
                                stallrwen <= low;
                        end
                        else begin
                                statec <= state_wrz;
// synopsys translate_off
`ifdef MSPAN_MON
wrz_arcs <= { 1'b1, 3'b0 } | firstwr_arcs;	    // D
`endif
// synopsys translate_on
                        end
                end

		state_rdc : begin
			if (rdpreqzr & !rbphase) begin
                                statec <= state_rdz;
// synopsys translate_off
`ifdef MSPAN_MON
rdc_arcs <= 1'b1 | firstwr_arcs;		    // A
`endif
// synopsys translate_on
                                encr <= low;
                        end
			else if (!rdpreqzr & rbphase) begin
				statec <= state_firstwr;
// synopsys translate_off
`ifdef MSPAN_MON
rdc_arcs <= { 1'b1, 1'b0 } | firstwr_arcs;	    // B
`endif
// synopsys translate_on
				stallrwen <= low;
			end
                        else begin
                                statec <= state_rdc;
// synopsys translate_off
`ifdef MSPAN_MON
rdc_arcs <= { 1'b1, 2'b0 } | firstwr_arcs;	    // C
`endif
// synopsys translate_on
                        end
                end

                state_rdz : begin
				statec <= state_firstwr;
				stallrwen <= low;
                end

		default :
				statec <= 'bx;
endcase
      end
   end
endmodule