// Module instances modified by /home/rws/workarea/rf/sw/bbplayer/tools/necprimfix 
//
//    1 instance of in01d5 changed to j_in01.
//    1 instance of ni01d5 changed to j_ni01.
//

 /************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: ms_sm.v,v 1.13 2003/01/24 23:07:37 berndt Exp $
//		rdram state machine for memspan
//	this module performs rdram request/activity/r/w/c/z for 
//	memspan;  attempts to minimize latency between requests;
//	clears requests and controls update flow of pointers/busy flags;
//	shortcuts for write cases of write masks c/z being zero.
//	generation of rbphase, being the rambus access phase to regfile.
//	address/pointer selection for memspan regfile address; rdram phase
//	write enable selection also, for rdram phase.
//	rdram writes into regfile (R) are terminated by finish line from io;
//	regfile writes into rdram (W) are terminated by counter compare here.
//	write requests (from writemask logic, another module) are reset as
//	soon as writemask is output to rdram, this allows unstalling of
//	writemask stall ASAP, overlapping accrual of next wmask with 
//	rdram write activity here.
//	the only use of rbphase here is to control write enable behavior
//	there is no use of stalls here, all rdram state machine activity
//	is non-stallable and should only connect to non-stallable
//	interfaces of other blocks.
//
//	notes:  reads are fn of enreadc/z;  writes implied by creqw/zreqw;
//
//	NOTES FOR JLSMITH:  protocol is READS:  0 delay, WRITES: 2 delay.

//	mods 10-7-94:  stay in wrctxt if (resetc/zreqw) set, and mod rp
//	  so that set c/zreqw has priority over reset;  this way we don't
//	  skip a write beat during reset req and ensure writes before reads.

//	mods 10-11-94:  place all stall inputs here and generate single one out
//		later put all sync stuff in here...and clock stoppage.
//	mods 10-19-94:  stb_sync_full, freeze_gclk, unfreeze_gclk, rel_sync_full
//	mod 10-20-94:  pipe_busy output
//	mod 10-26-94:  init wcount to 1;  add stallnxtwm
//	mod 10-27-94:  buffer rbcwincwr/rbzwincwr for wcount cmp:  wnum
//	11-1	eliminate state_rdcstart/rdzstart? (miss finish)
//		kill steprddone at rdctxt/loop if set
//	11-3   disallow read request until spanproc=0
//	11-14 outport finishd1/finishd2 for si killwe's;
//	11-16 advance selrbc/zw high a state for address init
//	11-23 add start_gclk output, = !stopgclock;  retain latter for my sim env
//	12-1  add steprbptrd1,d2 to delay rdramreq after rdptr update: rdspace
//	12-8  add 3 more states, for c/zwmzero rdram cycle bypass;
//	12-9  add 4th state, bug fix; also add ensteprbc/zwptr;
//	12-13 fix write bypass (sync reset*reqw/steprb*wptr, reset in bypass2);
//	12-16 fix 32b c zbuf case:  add zreqwbuf; fix cwmzero/!zwmzero case;
//	12-20 fix wrzdata-to-rdctxt clear of ensteprbcwptr (32b z tri bug);
//		cleanup state machine transitions
//	12-22 create reset_ld as delayed reset, to stopgclock generation;
//	12-28 create delayread to guarantee rbc/zrinc settling before dma read request;
//	1-4 add stopgclockd, output to ms_debug for observation;
//	1-10 reset to zero:  wnum, wcount for synthesis reasons;
//	1-12 add spanprocd register, to fix rdspace latency issue;
//		remove delayread, which was not sufficent solution.
//	2-2  generate/output start4ms for back-to-back dma fix;
//
//	hw2
//	
//	6-8 create 7b bus "start_gclk" for new gclk gating scheme;
//	6-9 add latch to above path;
//	6-12 add intermediate buffer between latch and 10x drivers;
//
//	bcp
//	10-31 replace stopgclk_lat with negedge DFF;

module ms_sm(clock, reset_l, rdspace, rdenreadc, rdenreadz,
	grant, start, finish,
	creqw, zreqw, cwmzero, zwmzero, rddone, smcwincwr, smzwincwr,
	stallphase, stallrw, stallrdctxt, stallwrctxt, stallptr,
	stallczwm, stb_sync_full, freeze_gclk, unfreeze_gclk, stallnxtwm,
	spanproc,

	steprddone, finishd1, finishd2,
	rdramreqcr, rdramreqzr, rdramreqcw, rdramreqzw,
	enrbwe, selrbcr, selrbzr, stopgclockd, start4ms,
	selrbcw, selrbzw, selcwmask, selzwmask, resetcreqw, resetzreqw,
	steprbcrptr, steprbzrptr, steprbcwptr, steprbzwptr, rbphase,
	start_gclock, stopgclock, rel_sync_full, pipe_busy);

`include "ms.vh"

input clock;					// system clock
input reset_l;					// system reset

input rdspace;					//space is avail for next dmard
input rdenreadc;				//rdctxt enrdcolor
input rdenreadz;				//rdctxt enrddepth 
input grant;					//dma grant
input start;					//dma valid (0/2 delay r/w)
input finish;					//dma last data cycle
input creqw;					//color write request
input zreqw;					//depth write request
input cwmzero;					//color wmask is all zero's
input zwmzero;					//depth wmask is all zero's
input rddone;
input [3:0] smcwincwr;				//number of regfile 36b entries
input [3:0] smzwincwr;				//per current spanlet 1-16 ??

input stallphase, stallrw, stallrdctxt, stallwrctxt;
input stallptr, stallczwm;
input stb_sync_full, freeze_gclk, unfreeze_gclk;
input stallnxtwm;
input spanproc;

output steprddone;
output finishd1, finishd2;
output rdramreqcr;                              //dma request
output rdramreqzr;                               //dma request
output rdramreqcw;                               //dma request
output rdramreqzw;                               //dma request
output enrbwe;					//regfile we for rdram activity
output selrbcr;					//sel rf addr for rdram c rd
output selrbzr;					//sel rf addr for rdram z rd
output selrbcw;                                 //sel rf addr for rdram c wr
output selrbzw;                                 //sel rf addr for rdram z wr
output selcwmask;
output selzwmask;
output resetcreqw;				//clear write request (color)
output resetzreqw;				//clear write request (depth)
output steprbcrptr;
output steprbzrptr;
output steprbcwptr;
output steprbzwptr;
output rbphase;

output start4ms;
output stopgclock;
output start_gclock;
output rel_sync_full;
output pipe_busy;
output stopgclockd;

// input/output registers

reg finishd1;
reg steprbcrptr;
reg steprbzrptr;
reg steprbcwptr;
reg steprbzwptr;
reg enrbwe;
reg rdramreqcr;
reg rdramreqzr;
reg rdramreqcw;
reg rdramreqzw;
reg steprddone;
reg selrbcr;
reg selrbzr;
reg selrbcw;
reg selrbzw;
reg selcwmask;
reg selzwmask;
reg resetcreqw;
reg resetzreqw;
reg rel_sync_full, rel_sync_fulld, freeze_gclkd;
reg fullsyncreq;

reg steprbptrd1, steprbptrd2;
reg ensteprbcwptr, ensteprbzwptr;
reg stopgclockd;

// internal registers
reg finishd2;
reg [3:0] wcount, wnum;
reg rbphase;
reg zreqwbuf;
reg reset_ld;
reg spanprocd;
reg start_gclock;

// pseudo registers

reg stopgclock;
reg pipe_busy;

// wires

wire start4ms;

//latch start_gclk via clk=low transparent latch, buffer noninverting
//then fanout=10 and buffer each output, utilize just lsb for 
//preexisting netlist e.g. start_gclk_bus[0] goes to global start_gclk
//until clock distribution netlist surgery occurs....

//lanfnb 
//stopgclk_lat(.en(clock), .d(stopgclock), .q(stopgclock_d));

always @(negedge clock) begin
   if (reset_l == 1'b0) begin
	start_gclock  	<=  	1'b1;
   end
   else begin
	start_gclock 	<=	~stopgclock;
   end
end

// rdram state machine
reg [21:0] state;
parameter

   state_rdctxt			= 22'h1,
   state_rdcreq			= 22'h2,
   state_rdcwait		= 22'h4,
   state_rdcdata		= 22'h10,
   state_rdzreq			= 22'h20,
   state_rdzwait		= 22'h40,
   state_rdzdata		= 22'h100,
   state_wrctxt			= 22'h200,
   state_wrcreq			= 22'h400,
   state_wrcwait		= 22'h800,
   state_wrcstart		= 22'h1000,
   state_wrcdata		= 22'h2000,
   state_wrzreq			= 22'h4000,
   state_wrzwait		= 22'h8000,
   state_wrzstart		= 22'h10000,
   state_wrzdata		= 22'h20000,
   state_bypass1		= 22'h40000,
   state_bypass2		= 22'h80000,
   state_bypass3		= 22'h100000,
   state_bypass4		= 22'h200000;

assign start4ms = ((state == state_rdcwait) || (state == state_rdzwait) ||
                        (state == state_wrcwait) ||
                        (state == state_wrzwait));
   
// synopsys translate_off
`ifdef MSPAN_MON
reg [6:0] rdctxt_arcs;
reg [3:0] rdcdata_arcs;
reg [2:0] rdzdata_arcs;

reg [9:0] wrctxt_arcs;
reg [3:0] wrcdata_arcs;
reg [1:0] wrzdata_arcs;
`endif
// synopsys translate_on

//stall OR'ing

always @(stallphase or stallrw or stallrdctxt or stallwrctxt or
  stallptr or stallczwm or freeze_gclkd or rel_sync_fulld or
		stallnxtwm or reset_ld) begin

	stopgclock <= (stallphase || stallrw || stallrdctxt || stallwrctxt ||
	  stallptr || stallczwm || freeze_gclkd || rel_sync_fulld ||
			stallnxtwm) & reset_ld;
end

always @(rel_sync_fulld) begin
	pipe_busy <= (!rel_sync_fulld);
end

always @(posedge clock) begin
   if (reset_l == 1'b0) begin
      // resettable registers
      enrbwe <= low;
      reset_ld <= low;
      rdramreqcr <= low;
      rdramreqzr <= low;
      rdramreqcw <= low;
      rdramreqzw <= low;
      	steprbptrd1 <= low;
      	steprbptrd2 <= low;
      steprbcrptr <= low;
      steprbzrptr <= low;
      steprbcwptr <= low;
      steprbzwptr <= low;
      steprddone <= low;
      state <= state_rdctxt;
	ensteprbcwptr <= low;
	ensteprbzwptr <= low;
      rbphase <= high;
      resetcreqw <= high;
      resetzreqw <= high;
      freeze_gclkd <= low;
      rel_sync_full <= low;
      rel_sync_fulld <= low;
      fullsyncreq <= low;
	selcwmask <= low;
	selzwmask <= low;
	selrbcr <= low;
	selrbzr <= low;
	selrbcw <= low;
	selrbzw <= low;
	zreqwbuf <= low;
	spanprocd <= low;
	stopgclockd <= low;
//nonresettable registers
	wcount <= 4'b0;
	wnum <= 4'b0;
// synopsys translate_off
`ifdef MSPAN_MON
	rdctxt_arcs <= 7'b0;
	rdcdata_arcs <= 4'b0;
	rdzdata_arcs <= 3'b0;
	wrctxt_arcs <= 10'b0;
	wrcdata_arcs <= 4'b0;
	wrzdata_arcs <= 2'b0;
`endif
// synopsys translate_on
      end
   else begin
	reset_ld <= high;
	stopgclockd <= stopgclock;
	steprbptrd2 <= steprbptrd1;
	steprbptrd1 <= (steprbcrptr || steprbzrptr);
	finishd2 <= finishd1;
	finishd1 <= finish;
	rbphase  <= !rbphase;
	freeze_gclkd <= freeze_gclk;
	rel_sync_fulld <= rel_sync_full;

      //strobe full sync state machine
if (stb_sync_full) begin
	fullsyncreq <= high;
end
else if (fullsyncreq & !(creqw || zreqw || resetcreqw || resetzreqw)) begin
        fullsyncreq <= low;
end
else begin
	fullsyncreq <= fullsyncreq;
end

if (fullsyncreq & !(creqw || zreqw || resetcreqw || resetzreqw)) begin
	rel_sync_full <= high;
end
else if (unfreeze_gclk) begin
	rel_sync_full <= low;
end
else begin
	rel_sync_full <= rel_sync_full;
end

	spanprocd <= spanproc;

      // rdram state machine
      case (state)

//				rdspace <= 1 iff space for both c/z read
//                               (if one plane, define both same size)
//					and reads enabled..
//				rddone <= 1 iff no span in rdctxt
//				 set init, and set when decomp last spanlet
//   tbd:  wrptrs must update during reads if no writes enabled;
//	therefore:  disable all stalls "not applicable".

// question:  are we cycling thru rdctxt even if write only, to make space?
//	answer:  no.  below, we define rdspace=0 for this case.
//	although...can just interlock with passing of address to rmwctxt...
//	and set rddone then if !(enreadc + enreadz), similar approach for wr.

//summary:  if load, then update wrptrs whenever update rdptrs;
//	cases:
//		read	write	crptr	zrptr	cwptr	zwptr
//			c	wc		wc
//			cz	wc	wz	wc	wz
//		c	c	rc		wc
//		c	cz	rc	wz	wc	wz	
//		z	c	wc	rz	wc	rz	
//		z	cz	wc	rz	wc	wz
//		cz	c	rc	rz	wc	rz
//		cz	cz	rc	rz	wc	wz
//		c		rc		rc	
//	also, if write only op, disable read stalls and update read ptrs
//	whenever we update write ptrs. etc. 
//		therefore "rdspace" is zero when no reads invoked
//	9/24/94:  actually the above solved instead by setting rddone at t4;
//		whereas creqw/zreqw never set for loads
//	9/24/94:  ...and also wrdone is set if no writes....also at startspan;
//	therefore must flush betw.  all c/z r/w mode changes.
//	9/24/94:  still true, because r,w pointer update slips pipe for w,r
//		only cases, respectively...

	state_rdctxt : begin
                        steprbcrptr <= low;
                        steprbzrptr <= low;
                        steprbcwptr <= low;
                        steprbzwptr <= low;
                        steprddone <= low;
			resetcreqw <= low;
			resetzreqw <= low;
	  if (spanproc || spanprocd || steprddone || steprbcrptr || steprbzrptr) begin
			state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { 1'b1 | rdctxt_arcs };		    // A
`endif
// synopsys translate_on
		end
                else if (creqw || zreqw) begin
                        state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { { 1'b1, 1'b0 } | rdctxt_arcs };    // B
`endif
// synopsys translate_on
                        end
		else if ((!rdspace || rddone) & ! (creqw || zreqw)) begin
			state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { { 1'b1, 2'b0 } | rdctxt_arcs };    // C
`endif
// synopsys translate_on
			end
		else if (rdspace & !rddone & rdenreadc & !(steprbptrd1 || steprbptrd2)) begin
			state <= state_rdcreq;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { { 1'b1, 3'b0 } | rdctxt_arcs };    // D
`endif
// synopsys translate_on
			rdramreqcr <= high;
		//	send out addr/len/dir/rw
			end
		else if (rdspace & !rddone & rdenreadz & !(steprbptrd1 || steprbptrd2)) begin
			state <= state_rdzreq;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { { 1'b1, 4'b0 } | rdctxt_arcs };    // E
`endif
// synopsys translate_on
			rdramreqzr <= high;
                //      send out addr/len/dir/rw
			end
		else if ((rdspace & !rddone) & !(rdenreadz || rdenreadc) &
		  ! (creqw || zreqw)) begin
                        state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { { 1'b1, 5'b0 } | rdctxt_arcs };    // F
`endif
// synopsys translate_on
                        end
		else begin
			state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdctxt_arcs <= { { 1'b1, 6'b0 } | rdctxt_arcs };    // G
`endif
// synopsys translate_on
			end
		end

	state_rdcreq : begin
		if (grant) begin
			state <= state_rdcwait;
			rdramreqcr <= low;
			selrbcr <= high;
			end
		else if (!grant) begin
			state <= state_rdcreq;
			end
		end

	state_rdcwait : begin
                if (start) begin
                        state <= state_rdcdata;
			enrbwe <= high;
			selrbcr <= low;
		//	rbaddr <= rbptrcr; 	
                        end
                else if (!start) begin
                        state <= state_rdcwait;
                        end
                end

	state_rdcdata : begin
                if ((rbphase & (finishd1 || finishd2)) & !rdenreadz & (creqw || zreqw)) begin
                        state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdcdata_arcs <= { 1'b1 | rdcdata_arcs };	    // A
`endif
// synopsys translate_on
			enrbwe <= low;
                        steprbcrptr <= high;
                        steprddone <= high;

        //      update read pointers
                        end
                else if ((rbphase & (finishd1 || finishd2)) & !rdenreadz & !(creqw || zreqw)) begin
                        state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdcdata_arcs <= { { 1'b1, 1'b0 } | rdcdata_arcs };  // B
`endif
// synopsys translate_on
                        enrbwe <= low;
                        steprbcrptr <= high;
                        steprddone <= high;

        //      update read pointers
                        end

		else if ((rbphase & (finishd1 || finishd2)) & rdenreadz) begin
			state <= state_rdzreq;
// synopsys translate_off
`ifdef MSPAN_MON
rdcdata_arcs <= { { 1'b1, 2'b0 } | rdcdata_arcs };  // C
`endif
// synopsys translate_on
                        enrbwe <= low;
			steprbcrptr <= high;
			rdramreqzr <= high;
                //      send out addr/len/dir/rw
			end
                else if (!(rbphase & (finishd1 || finishd2))) begin
                        state <= state_rdcdata;
// synopsys translate_off
`ifdef MSPAN_MON
rdcdata_arcs <= { { 1'b1, 3'b0 } | rdcdata_arcs };  // D
`endif
// synopsys translate_on
                        end
                end

	state_rdzreq : begin
			steprbcrptr <= low;
                if (grant) begin
                        state <= state_rdzwait;
			rdramreqzr <= low;
                        selrbzr <= high;
                        end
                else if (!grant) begin
                        state <= state_rdzreq;
                        end
                end

	state_rdzwait : begin
                if (start) begin
			selrbzr <= low;
                        state <= state_rdzdata;
			enrbwe <= high;
                        end
                else if (!start) begin
                        state <= state_rdzwait;
                        end
                end

	state_rdzdata : begin
                if (rbphase & (creqw || zreqw) & (finishd1 || finishd2))  begin
                        state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdzdata_arcs <= { 1'b1 | rdzdata_arcs };	    // A
`endif
// synopsys translate_on
                        enrbwe <= low;
                        steprbzrptr <= high;
                        steprddone <= high;

	//  	update read pointers
                        end
		else if (rbphase & !(creqw || zreqw) & (finishd1 || finishd2))  begin
                        state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
rdzdata_arcs <= { { 1'b1, 1'b0 } | rdzdata_arcs };  // B
`endif
// synopsys translate_on
                        enrbwe <= low;
                        steprbzrptr <= high;
                        steprddone <= high;

			end
                else if (!(rbphase & (finishd1 || finishd2))) begin
                        state <= state_rdzdata;
// synopsys translate_off
`ifdef MSPAN_MON
rdzdata_arcs <= { { 1'b1, 2'b0 } | rdzdata_arcs };  // C
`endif
// synopsys translate_on
                        end
                end

// note:  spanoverlap may need to handle 3 prims, as we might be able to
//read for span 3 while not yet written span 1 (primitive is 22 clks min)
//e.g. might have two prims in wrctxt wmask/addr bufs, and 2-3? in pipe ~21
//clks from ew to readz rdp...

	state_wrctxt : begin
                        steprbcrptr <= low;
                        steprbzrptr <= low;
                        steprbcwptr <= low;
                        steprbzwptr <= low;
                        steprddone <= low;
			resetcreqw <= low;
			resetzreqw <= low;
		if (resetcreqw || resetzreqw || steprbcwptr || steprbcrptr ||
		 steprbzwptr || steprbzrptr) begin
			state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { 1'b1 | wrctxt_arcs };		    // A
`endif
// synopsys translate_on
		end
		else if (creqw  & !cwmzero) begin
			state <= state_wrcreq;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 1'b0 } | wrctxt_arcs };    // B
`endif
// synopsys translate_on
			zreqwbuf <= zreqw;
			rdramreqcw <= high;
                //      send out addr/len/dir/rw
			end
		else if (creqw  & cwmzero & zreqw  & !zwmzero) begin
			state <= state_wrzreq;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 2'b0 } | wrctxt_arcs };    // C
`endif
// synopsys translate_on
			rdramreqzw <= high;
			ensteprbcwptr <= high;
			end
                else if ((creqw  & cwmzero & zreqw  & zwmzero)) begin
                        state <= state_bypass1;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 3'b0 } | wrctxt_arcs };    // D
`endif
// synopsys translate_on
                        ensteprbcwptr <= high;
                        ensteprbzwptr <= high;
                        end
                else if ((creqw  & cwmzero & !zreqw )) begin
                        state <= state_bypass1;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 4'b0 } | wrctxt_arcs };    // E
`endif
// synopsys translate_on
//                        resetcreqw <= high;
                        ensteprbcwptr <= high;
                        end
		else if (!creqw  & zreqw  & !zwmzero) begin
                        state <= state_wrzreq;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 5'b0 } | wrctxt_arcs };    // F
`endif
// synopsys translate_on
                        rdramreqzw <= high;
                        end
                else if ((!creqw  & zreqw  & zwmzero)) begin
                        state <= state_bypass1;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 6'b0 } | wrctxt_arcs };    // G
`endif
// synopsys translate_on
                        ensteprbzwptr <= high;
                        end             
                else if (!(creqw  || zreqw ) & (!rdspace || rddone)) begin
                        state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 7'b0 } | wrctxt_arcs };    // H
`endif
// synopsys translate_on
                        end
                else if (!(creqw  || zreqw ) & (rdspace & !rddone) &
				(rdenreadc || rdenreadz)) begin
                        state <= state_rdctxt;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 8'b0 } | wrctxt_arcs };    // I
`endif
// synopsys translate_on
                        end
		else begin
			state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
wrctxt_arcs <= { { 1'b1, 9'b0 } | wrctxt_arcs };    // J
`endif
// synopsys translate_on
		end
	end

	state_wrcreq : begin
		if (grant) begin
			state <= state_wrcwait;
			rdramreqcw <= low;
			selrbcw <= high;
			end
		else if (!grant) begin
			state <= state_wrcreq;
			end
		end

	state_wrcwait : begin
		if (start) begin
			state <= state_wrcstart;
			selcwmask <= high;
			wcount <= 4'h1;
			wnum <= smcwincwr;
			resetcreqw <= high;
			end
		else if (!start) begin
			state <= state_wrcwait;
			end
		end

	state_wrcstart : begin
			state <= state_wrcdata;
			selcwmask <= low;
			selrbcw <= low;
			resetcreqw <= low;
		end

	state_wrcdata : begin
		if ((wcount == wnum) & zreqwbuf  & !zwmzero) begin
			state <= state_wrzreq;
// synopsys translate_off
`ifdef MSPAN_MON
wrcdata_arcs <= { 1'b1 | wrcdata_arcs };	    // A
`endif
// synopsys translate_on
			steprbcwptr <= high;
                        rdramreqzw <= high;
                //      send out addr/len/dir/rw
                        end
		else if (((wcount == wnum) & zreqwbuf  & zwmzero)) begin
			state <= state_bypass1;
// synopsys translate_off
`ifdef MSPAN_MON
wrcdata_arcs <= { { 1'b1, 1'b0 } | wrcdata_arcs };  // B
`endif
// synopsys translate_on
			resetzreqw <= high;
                        steprbcwptr <= high;
                        steprbzwptr <= high;
			end
                else if (((wcount == wnum) & !zreqwbuf )) begin
                        state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
wrcdata_arcs <= { { 1'b1, 2'b0 } | wrcdata_arcs };  // C
`endif
// synopsys translate_on
                        steprbcwptr <= high;
                        end
		else if (!(wcount == wnum)) begin
			state <= state_wrcdata;
// synopsys translate_off
`ifdef MSPAN_MON
wrcdata_arcs <= { { 1'b1, 3'b0 } | wrcdata_arcs };  // D
`endif
// synopsys translate_on
			wcount <= wcount + 1;
			end
                end

	state_wrzreq : begin
			steprbcwptr <= low;
			resetcreqw <= low;
		if (grant) begin
			state <= state_wrzwait;
			rdramreqzw <= low;
			selrbzw <= high;
			end
		else if (!grant) begin
			state <= state_wrzreq;
			end
		end

	state_wrzwait : begin
		if (start) begin
			state <= state_wrzstart;
//			selrbzw <= high;
			selzwmask <= high;
			wcount <= 4'h1;
			wnum <= smzwincwr;
			resetzreqw <= high;
			resetcreqw <= ensteprbcwptr;
			end
		else if (!start) begin
			state <= state_wrzwait;
			end
		end			

	state_wrzstart : begin
			state <= state_wrzdata;
			selrbzw <= low;
			selzwmask <= low;
			resetzreqw <= low;
			resetcreqw <= low;
		end

	state_wrzdata : begin
		if ((wcount == wnum)) begin
			state <= state_wrctxt;
// synopsys translate_off
`ifdef MSPAN_MON
wrzdata_arcs <= { 1'b1 | wrzdata_arcs };	    // A
`endif
// synopsys translate_on
                        steprbzwptr <= high;
			steprbcwptr <= ensteprbcwptr;
			ensteprbcwptr <= low;
			end
		else if (!(wcount == wnum)) begin
			state <= state_wrzdata;
// synopsys translate_off
`ifdef MSPAN_MON
wrzdata_arcs <= { { 1'b1, 1'b0 } | wrzdata_arcs };  // B
`endif
// synopsys translate_on
			wcount <= wcount + 1;
			end
		end

//new states for write bypass, to ensure pointers settle before nxt stepping

	state_bypass1 : begin
			steprbzwptr <= ensteprbzwptr;
			steprbcwptr <= ensteprbcwptr;
			ensteprbzwptr <= low;
			ensteprbcwptr <= low;
			resetcreqw <= ensteprbcwptr;
			resetzreqw <= ensteprbzwptr;
			state <= state_bypass2;
		end
        state_bypass2 : begin
                        state <= state_bypass3;
                        steprbzwptr <= low;
                        steprbcwptr <= low;
                        resetcreqw <= low;
                        resetzreqw <= low;
                end
        state_bypass3 : begin
                        state <= state_bypass4;
                end
        state_bypass4 : begin
                        state <= state_wrctxt;
                end
	
		default :
			state <= 22'bx;

         endcase
      end
   end
endmodule