// pi.v v1 Frank Berndt
// pi top level;
// :set tabstop=4

// pi buffer address map, 256x64
//
//	  0..63		flash data 0, 512 bytes;
//	 64..127	flash data 1, 512 bytes;
//	128..129	flash ecc 0, 16 bytes;
//	130..131	flash ecc 1, 16 bytes;
//	132..153	aes expanded key, 44*4 bytes;
//	154..155	aes init vector, 16 bytes;
//	156..159	unused;
//	160..255	address translation buffer;

module pi (
	sysclk, rst_l, reset_l,
	secure,
	cbus_din, cbus_dout, cbus_error, cbus_select, cbus_command,
	cbus_write_enable, cbus_read_request, cbus_read_grant,
	dbus_din, dbus_dout, dbus_enable,
	dma_request, dma_grant, dma_start, dma_last,
	dma_intr, aes_intr, flc_intr, ide_intr, err_intr, err_trap,
	io_rst, io_in, io_ena, io_out, io_oe, io_ale,
	io_ior, io_iow, io_cs, io_dmarq, io_dmack, io_intr,
	fl_ce, fl_ale, fl_cle, fl_re, fl_we, fl_wp, fl_ryby, fl_md,
	lctrl_req, lctrl_val, lctrl_but,
	gpio_oe, gpio_out, gpio_in
);

`include "cbus.vh"

	// module io ports;

	input sysclk;				// system clock;
	input rst_l;				// pin reset;
	input reset_l;				// system reset;
	input secure;				// in secure mode;

	input [31:0] cbus_din;		// cbus data in;
	output [31:0] cbus_dout;	// cbus data out;
	output cbus_error;			// cbus error;
	input [1:0] cbus_select;	// cbus phase;
	input [2:0] cbus_command;	// cbus command;
	input cbus_write_enable;	// enable cbus output;
	output cbus_read_request;	// request cbus response cycle;
	input cbus_read_grant;		// response cycle granted;

	input [63:0] dbus_din;		// dbus data in;
	output [63:0] dbus_dout;	// dbus data out;
	input dbus_enable;			// enable dbus drivers;
	output dma_request;			// dma request;
	input dma_grant;			// dma granted;
	input dma_start;			// first dbus word valid;
	input dma_last;				// last dbus word valid;
	output dma_intr;			// dma interrupt;
	output aes_intr;			// aes controller interrupt;
	output flc_intr;			// flash controller interrupt;
	output ide_intr;			// flash controller interrupt;
	output err_intr;			// error interrupt on error;
	output err_trap;			// secure kernel trap on error;

	// generic io interface;

	output io_rst;				// io bus reset;
	input [15:0] io_in;			// io input data;
	output io_ena;				// io input clock enables;
	output [15:0] io_out;		// io output data;
	output [1:0] io_oe;			// io data output enables;
	output io_ale;				// io address latch enable;
	output io_ior;				// io read pulse;
	output io_iow;				// io write pulse;
	output [3:0] io_cs;			// io pio chip selects;
	input io_dmarq;				// io dma request;
	output io_dmack;			// io dma acknowledge;
	input io_intr;				// io device interrupt;

	// nand flash controls;

	output [3:0] fl_ce;			// chip enables;
	output fl_ale;				// address latch enable;
	output fl_cle;				// command latch enable;
	output fl_re;				// read eanble;
	output fl_we;				// write eanble;
	output fl_wp;				// write protect;
	input fl_ryby;				// ready/busy;
	input fl_md;				// module detect;

	// button interface to si;

	input lctrl_req;			// request button sample;
	output lctrl_val;			// button sample valid;
	output [13:0] lctrl_but;	// button data;

	// general purpose io;

	output [3:0] gpio_oe;		// output enables;
	output [3:0] gpio_out;		// output values;
	input [3:0] gpio_in;		// input values;

	// buffer system reset;

	reg reset;				// positive reset;
	reg sec_mode;			// in secure mode;
	wire [7:0] acc_ena;		// access enables;

	always @(posedge sysclk)
	begin
		sec_mode <= secure;
		reset <= ~reset_l;
	end

	// cbus interface;
	// cbus interface controls;
	// decode cbus commands;

	reg [2:0] cbus_cmd;		// cbus cmd register;
	reg [31:0] cbus_in;		// cbus read/write register;
	wire [31:0] cbus_out;	// cbus output data;
	reg [31:0] cbus_dout;	// cbus read/write register;
	wire error_out;			// error bit;
	reg cbus_error;			// cbus error;
	wire cbus_read;			// cbus read request;
	wire cbus_write;		// cbus write request;
	wire cbus_rw;			// cbus read or write request;

	always @(posedge sysclk)
	begin
		cbus_cmd <= cbus_command;
		cbus_in <= cbus_din;
		cbus_dout <= {32{cbus_write_enable}} & cbus_out;
		cbus_error <= cbus_write_enable & error_out;
	end

	assign cbus_read = (cbus_cmd == `CBUS_CMD_READ);
	assign cbus_write = (cbus_cmd == `CBUS_CMD_WRITE);
	assign cbus_rw = cbus_read | cbus_write;

	// pi responds in register and ram space 0x046x_xxxx;
	// pi responds in cartrige space 0x05xx_xxxx ... 0x7fff_ffff;
	// stop access if reset interfered;

	wire [11:0] cbus_id;	// cbus space id;
	wire cbus_pi;			// pi internal space, regs, buffer, ide;
	wire cbus_buf;			// pi buffer space;
	wire cbus_ifc;			// ide flow control space;
	wire cbus_ide;			// ide space;
	wire cbus_0x;			// cartrige space 0x0xxx_xxxx;
	wire cbus_xa;			// cartrige space 0xx500_0000..0xxfff_ffff;
	wire cbus_ya;			// cartrige space 0x1000_0000..0x7fff_ffff;
	wire cbus_io;			// all cartrige spaces;
	wire cbus_req;			// cbus read/write request;
	wire pi_read;			// pi read request;
	wire pi_write;			// pi write request;
	wire pi_rrgnt;			// read request grant;
	wire pi_busy;			// pi busy with dma or io;

	assign cbus_id = cbus_in[31:20];
	assign cbus_pi = (cbus_id == `CBUS_PI);
	assign cbus_buf = cbus_pi & ~cbus_in[19] & cbus_in[16];
	assign cbus_ifc = cbus_pi & ~cbus_in[19] & cbus_in[17];
	assign cbus_ide = cbus_pi & cbus_in[19];

	assign cbus_0x = (cbus_in[30:28] == 3'b000);
	assign cbus_xa = cbus_in[27]
		| (cbus_in[27:24] == 4'h5)
		| (cbus_in[27:24] == 4'h6)
		| (cbus_in[27:24] == 4'h7);
	assign cbus_ya = |cbus_in[30:28];
	assign cbus_io = ~cbus_in[31] & (cbus_ya | (cbus_0x & cbus_xa));

	assign cbus_req = cbus_rw & (cbus_pi | cbus_io);
	assign pi_read = cbus_pi & cbus_read;
	assign pi_write = cbus_pi & cbus_write;
	assign pi_rrgnt = reset | cbus_read_grant;

	// hold on to pio access type;
	// reset stops any register op in progress;
	// addr[5:2] address compatible registers;
	// addr[6] addresses new pi registers;
	// addr[16] addresses pi buffer ram;

	reg pio_ifc;			// pio flow control;
	reg pio_read;			// cbus pio read request;
	reg pio_ack;			// pio read acknowledge;
	reg pio_req;			// delayed cbus_req;
	reg [29:0] pio_addr;	// pio address; registers, ram or device space;
	reg [29:9] pio_laddr;	// previous pi address, for pio hit detection;
	reg pio_hit;			// pio page hit;
	reg pio_dev;			// pio to cartrige;
	reg pio_write;			// cbus pio write;
	wire pio_reg;			// pio access to registers;
	wire pio_buf;			// pio access to buffer;
	wire pio_ide;			// pio access to io bus;
	reg reg_write;			// write to register;
	wire [31:0] pio_wdata;	// pio write data;
	reg [2:0] io_done;		// io done pipe;
	wire ifc_rack;			// ide flow control ack;
	wire ide_stall;			// stall read response for flow control;
	wire ide_rack;			// ide read ack;
	wire rsp_req;			// request read response;

	assign ifc_rack = pio_ifc & ~ide_stall;
	assign rsp_req = pio_read | ide_rack | ifc_rack | io_done[2];

	always @(posedge sysclk)
	begin
		pio_ifc <= (ide_stall & pio_ifc) | (cbus_ifc & pi_read);
		pio_read <= ~(cbus_ide | cbus_ifc) & pi_read;
		pio_ack <= rsp_req;
		if(cbus_req) begin
			pio_addr <= cbus_in[29:0];
			pio_dev <= cbus_io;
			pio_write <= cbus_write;
		end
		pio_req <= cbus_req;
		if(pio_req) begin
			pio_hit <= (pio_addr[29:9] == pio_laddr);
			pio_laddr <= pio_addr[29:9];
		end
		reg_write <= ~reset & pi_write;
	end

	assign pio_wdata = cbus_in;
	assign pio_reg = ~pio_dev & ~pio_addr[19] & ~pio_addr[16];
	assign pio_buf = ~pio_dev & ~pio_addr[19] & pio_addr[16];
	assign pio_ide = ~pio_dev & pio_addr[19];

	// ide request control;
	// do not request io bus when access is disabled;
	// latch upper or lower write data, based on addr[1];

	wire ide_acc;			// access to ide spaces;
	reg ide_req;			// pio request to ide spaces;
	wire [15:0] ide_di;		// ide read data;

	assign ide_acc = pio_ide & acc_ena[6];

	always @(posedge sysclk)
	begin
		ide_req <= cbus_rw & cbus_ide;
	end

	// pio request control;
	// cache pio address to avoid flash reads for page hit;

	reg io_req;				// pio request to cartridge space;
	wire io_stop;			// stop io request;
	wire io_read;			// io read request;
	wire io_write;			// io write request;
	wire io_miss;			// io page miss;
	wire io_hit;			// io page hit;
	reg [31:0] io_wdata;	// captured io write data;
	reg io_pend;			// io read is pending;
	reg io_kick;			// kick processor for io read;
	reg io_err;				// io error;
	reg io_rbuf;			// read pi buffer for response data;

	assign io_read = io_req & ~pio_write;
	assign io_write = io_req & pio_write;
	assign io_stop = reset | io_done[0];
	assign io_miss = io_pend & ~pio_hit;
	assign io_hit = io_pend & pio_hit;
	assign error_out = pio_dev & io_err;

	always @(posedge sysclk)
	begin
		io_req <= cbus_rw & cbus_io;
		if(io_write)
			io_wdata <= pio_wdata;
		io_pend <= ~io_stop & (io_pend? pi_busy : io_req);
		io_kick <= io_miss & ~pi_busy & ~pio_write;
		io_rbuf <= ~pi_rrgnt & (io_rbuf | (io_done[0] & ~io_err));
	end

	// decode buffer regions for access control;

	wire [7:0] pio_baddr;	// pio buffer address;
	wire pio_batb;			// atb buffer range;
	wire pio_baes;			// aes buffer range;
	wire pio_bbuf;			// data buffer range;
	wire pio_bacc;			// buffer access enabled;

	assign pio_baddr = { pio_addr[10] & ~io_rbuf, pio_addr[9:3] };
	assign pio_batb = pio_addr[11] | pio_baddr[7] & (pio_baddr[6] | pio_baddr[5]);
	assign pio_baes = (pio_baddr[7:5] == 3'b100) & |pio_baddr[4:2];
	assign pio_bbuf = ~pio_batb & ~pio_baes;
	assign pio_bacc = (pio_batb & acc_ena[2])
		| (pio_baes & acc_ena[3])
		| (pio_bbuf & acc_ena[0]);

	// cbus access to pi buffer;
	// cbus request to buffer issued one clock after cbus address;
	// write data in cbus_in line up for write to pi buffer;
	// read data come out one clock later;
	// cbus request is dropped and buf_err set when dbus dma interfered;

	wire [2:0] pio_bufen;	// pio to upper atb, upper word or lower word;
	wire [2:0] io_bufen;	// buffer enables for io read response;

	assign pio_bufen[2] = pio_buf & pio_bacc & pio_addr[11];
	assign pio_bufen[1] = pio_buf & pio_bacc & ~pio_addr[11] & ~pio_addr[2];
	assign pio_bufen[0] = pio_buf & pio_bacc & ~pio_addr[11] & pio_addr[2];
	assign io_bufen[2] = 1'b0;
	assign io_bufen[1] = io_rbuf & ~pio_addr[2];
	assign io_bufen[0] = io_rbuf & pio_addr[2];

	// decode register addresses;
	// the new registers are access restricted;

	wire reg_comp;			// compatible registers;
	wire reg_new;			// new registers;
	wire [5:2] reg_addr;	// register address;
	wire [12:0] ra_reg;		// register index;

	assign reg_comp = pio_reg & ~pio_addr[6];
	assign reg_new = pio_reg & pio_addr[6];
	assign reg_addr = pio_addr[5:2];

	assign ra_reg[0] = (reg_addr == 4'h0);
	assign ra_reg[1] = (reg_addr == 4'h1);
	assign ra_reg[2] = (reg_addr == 4'h2);
	assign ra_reg[3] = (reg_addr == 4'h3);
	assign ra_reg[4] = (reg_addr == 4'h4);
	assign ra_reg[5] = (reg_addr == 4'h5);
	assign ra_reg[6] = (reg_addr == 4'h6);
	assign ra_reg[7] = (reg_addr == 4'h7);
	assign ra_reg[8] = (reg_addr == 4'h8);
	assign ra_reg[9] = (reg_addr == 4'h9);
	assign ra_reg[10] = (reg_addr == 4'ha);
	assign ra_reg[11] = (reg_addr == 4'hb);
	assign ra_reg[12] = (reg_addr == 4'hc);

	// decode compatible register addresses;
	// compatible registers are always accessible;

	wire ra_dma_addr;		// access PI_DRAM_ADDR;
	wire ra_dev_addr;		// access PI_DEV_ADDR;
	wire ra_dma_read;		// access PI_DMA_READ;
	wire ra_dma_write;		// access PI_DMA_WRITE;
	wire ra_status;			// access PI_STATUS;

	assign ra_dma_addr = reg_comp & ra_reg[0];
	assign ra_dev_addr = reg_comp & ra_reg[1];
	assign ra_dma_read = reg_comp & ra_reg[2];
	assign ra_dma_write = reg_comp & ra_reg[3];
	assign ra_status = reg_comp & ra_reg[4];

	// decode new register addresses;

	wire ra_atbu;			// access PI_ATBU;
	wire ra_error;			// access PI_ERROR;
	wire ra_fl_ctrl;		// access PI_FLASH_CTRL;
	wire ra_fl_conf;		// access PI_FLASH_CONF;
	wire ra_aes_ctrl;		// access PI_AES_CTRL;
	wire ra_access;			// access PI_ACCESS;
	wire ra_bread;			// access PI_DMA_BREAD;
	wire ra_bwrite;			// access PI_DMA_BWRITE;
	wire ra_gpio;			// access PI_GPIO;
	wire ra_ide_conf;		// access PI_IDE_CONF;
	wire ra_ide_ctrl;		// access PI_IDE_CTRL;
	wire ra_edata;			// access PI_EDATA;
	wire ra_fl_addr;		// access PI_FLASH_ADDR;

	assign ra_atbu = reg_new & ra_reg[0] & acc_ena[2];
	assign ra_error = reg_new & ra_reg[1] & acc_ena[7];
	assign ra_fl_ctrl = reg_new & ra_reg[2] & acc_ena[1];
	assign ra_fl_conf = reg_new & ra_reg[3] & acc_ena[1];
	assign ra_aes_ctrl = reg_new & ra_reg[4] & acc_ena[3];
	assign ra_access = reg_new & ra_reg[5];
	assign ra_bread = reg_new & ra_reg[6] & acc_ena[4];
	assign ra_bwrite = reg_new & ra_reg[7] & acc_ena[4];
	assign ra_gpio = reg_new & ra_reg[8] & acc_ena[5];
	assign ra_ide_conf = reg_new & ra_reg[9] & acc_ena[6];
	assign ra_ide_ctrl = reg_new & ra_reg[10] & acc_ena[6];
	assign ra_edata = reg_new & ra_reg[11];
	assign ra_fl_addr = reg_new & ra_reg[12] & acc_ena[1];

	// kick pi dma on writes to dma length registers;

	wire ra_dma_len;		// access any of the dma length registers;

	assign ra_dma_len = ra_dma_read | ra_dma_write | ra_bread | ra_bwrite;

	// request cbus for response;
	// immediatedly after read_requests is seen on cbus;
	// clear on grant and reset;

	reg cbus_read_request;	// request cbus response;

	always @(posedge sysclk)
	begin
		cbus_read_request <= ~pi_rrgnt & (cbus_read_request | rsp_req);
	end

	// compatible pi registers;
	// these registers are always accessible;

	reg [25:0] dma_addr;	// dma address;
	reg [29:0] dev_addr;	// device address;
	reg [23:0] dma_len;		// dma length;
	reg dma_read;			// dma read request, mem -> pi;
	reg dma_rwb;			// bdma request, mem <-> pibuf;
	reg dma_intr;			// dma interrupt, status[3];
	reg dma_err;			// dma error, status[2];
	reg io_busy;			// io busy, status[1];
	reg dma_busy;			// dma busy, status[0];
	wire dma_conflict;		// dma conflict;

	// decode writes to status register;
	// data[1]=1 clears interrupt;
	// data[0]=1 aborts current operation and resets error;
	// reset dma on missing module;

	wire sts_we;			// write to PI_STATUS;
	wire clr_intr;			// clear interrupt;
	wire dma_reset;			// abort operation, clear error;
	wire dma_stop;			// stop dma;
	wire dma_done;			// dma is done;

	assign sts_we = reg_write & ra_status;
	assign clr_intr = reset | (sts_we & pio_wdata[1]);
	assign dma_reset = reset | (sts_we & pio_wdata[0]);
	assign dma_stop = dma_reset | dma_done;

	// memory address;
	// must be 16-bit aligned for compatibility;
	// loaded with pio write write;
	// used for first dma block transfer to align;
	// then increments in blocks of 128 bytes;

	wire dma_addr_we;		// write dma address;
	wire dma_addr_ld;		// load dma address;
	wire dma_addr_inc;		// increment dma address;

	assign dma_addr_we = reg_write & ra_dma_addr;
	assign dma_addr_ld = ~dma_conflict & dma_addr_we;

	always @(posedge sysclk)
	begin
		if(dma_addr_ld)
			dma_addr <= { pio_wdata[25:1], 1'b0 };
		else if(dma_addr_inc)
			dma_addr <= { dma_addr[25:7] + 1, 7'd0 };
	end

	// device address;
	// virtual or physical address into device space;
	// compatibility requires 16-bit alignment;
	// however, bit 0 is needed for new functions;

	wire dev_addr_we;		// write device address;
	wire dev_addr_ld;		// load device address;
	wire dev_addr_inc;		// increment device address;

	assign dev_addr_we = reg_write & ra_dev_addr;
	assign dev_addr_ld = ~dma_conflict & dev_addr_we;

	always @(posedge sysclk)
	begin
		if(dev_addr_ld)
			dev_addr <= pio_wdata[29:0];
		else if(io_write)
			dev_addr <= pio_addr;
		else if(dev_addr_inc)
			dev_addr[29:3] <= dev_addr[29:3] + 1;
	end

	// dma length;
	// writing the dma length registers starts the dma;
	// starting a dma through PI_DMA_READ triggers error interrupt;
	// it is up to software to emulate the write;
	// one clock later, add lower addres bits for # of dw;
	// decremented by buffer dma for each double-word;
	// do not start dma when dma_len is 0, but issue done;

	wire dma_len_we;		// write to dma length;
	wire dma_len_ld;		// load dma_len;
	wire dma_proc;			// start write dma process;
	wire dma_trap;			// trap read dma;
	reg dma_kick;			// kick dma;
	wire dma_len_dec;		// decrement dma length;
	wire dma_len_nw0;		// # of dw is 0;
	reg dma_len_zero;		// dma length is 0;
	wire [23:0] dma_off;	// lower byte offset;

	assign dma_len_we = reg_write & ra_dma_len;
	assign dma_len_ld = ~dma_conflict & dma_len_we;
	assign dma_off = { 21'd0, dma_addr[2:1], 1'b0 };
	assign dma_len_nw0 = (dma_len[23:3] == 21'd0);

	always @(posedge sysclk)
	begin
		dma_kick <= dma_len_ld;
		if(dma_len_ld) begin
			dma_read <= ra_dma_read | ra_bread;
			dma_rwb <= ra_bread | ra_bwrite;
		end
		if(dma_len_ld)
			dma_len <= pio_wdata[23:0];
		else if(dma_kick)
			dma_len <= dma_len + dma_off;
		else if(dma_len_dec)
			dma_len[23:3] <= dma_len[23:3] - 1;
		if(io_kick)
			dma_len_zero <= 1'b0;
		else if(dma_kick)
			dma_len_zero <= &dma_len;
		else if(dma_len_dec)
			dma_len_zero <= dma_len_nw0;
	end

	assign dma_proc = dma_kick & ~dma_rwb & ~dma_read;
	assign dma_trap = dma_kick & ~dma_rwb & dma_read;

	// buffer dma busy flag;
	// set at start of buffer dma;

	reg bdma_start;			// start buffer dma;
	wire bdma_done;			// buffer dma is done;
	reg bdma_busy;			// buffer dma busy;

	assign bdma_done = dma_len_zero & (bdma_start | bdma_busy);

	always @(posedge sysclk)
	begin
		bdma_start <= dma_kick & dma_rwb;
		bdma_busy <= ~dma_stop & (bdma_busy | (bdma_start & ~dma_len_zero));
	end

	// dma burst length;
	// first burst aligns to 128-byte block;
	// a number of full 128-byte bursts may follow;
	// last burst moves the remaining bytes;

	wire bdma_ge128;		// dma_len >= 128;
	wire [6:3] bdma_dwib;	// # of dw in current burst;
	reg bdma_fill;			// fill current burst;
	reg [6:0] bdma_len;		// burst dma length;

	assign bdma_ge128 = |dma_len[23:7];
	assign bdma_dwib = ~dma_addr[6:3];

	always @(posedge sysclk)
	begin
		bdma_fill <= bdma_ge128 | (dma_len[6:3] > bdma_dwib);
		bdma_len <= bdma_fill? { bdma_dwib, 3'b111 } : dma_len[6:0];
	end

	// request dbus dma;

	reg bdma_aesp;			// aesp requests one burst dma;
	wire bdma_req;			// dma burst request;
	wire bdma_cyc_clr;		// clear bdma busy;
	reg bdma_cyc;			// bdma busy;
	wire bdma_req_clr;		// clear dma request;
	reg dma_request;		// dma request;
	reg bdma_ack;			// burst dma ack;
	reg bdma_ack2;
	reg bdma_ack3;

	assign bdma_cyc_clr = dma_stop | bdma_ack3;
	assign bdma_req_clr = dma_stop | dma_grant;
	assign bdma_req = dma_busy & ~dma_len_zero & ~bdma_cyc & (bdma_aesp | bdma_busy);

	always @(posedge sysclk)
	begin
		bdma_cyc <= ~bdma_cyc_clr & (bdma_cyc | bdma_req);
		dma_request <= ~bdma_req_clr & (dma_request | bdma_req);
		bdma_ack <= dma_last;
		bdma_ack2 <= bdma_ack;
		bdma_ack3 <= bdma_ack2;
	end

	// burst dma control;

	reg bdma_dph;			// burst dma phase;
	wire bdma_val;			// burst dma data valid;
	reg [1:0] bdma_dval;	// delayed valid;
	wire dbus_shr;			// data right shift;

	always @(posedge sysclk)
	begin
		bdma_dph <= bdma_cyc & ~dma_last & (bdma_dph | dma_start);
		bdma_dval <= { bdma_dval[0], bdma_val };
	end

	assign bdma_val = dma_start | bdma_dph;
	assign dma_len_dec = bdma_dval[0];
	assign dma_addr_inc = bdma_ack;
	assign dev_addr_inc = bdma_dval[0];

	// dma/io control;
	// writes to length registers start the pi dma;
	// if dma is busy then let the current dma complete and set dma error;
	// write to status register (any data) clears interrupt,
	// clears dma error bit and aborts current operation;

	wire dma_set_err;		// attempt to overwrite busy dma;

	assign pi_busy = dma_busy | io_busy;
	assign dma_set_err = pi_busy & (dma_addr_we | dev_addr_we | dma_len_we);
	assign dma_conflict = pi_busy;

	always @(posedge sysclk)
	begin
		dma_busy <= ~dma_stop & (dma_busy | dma_kick);
		io_busy <= ~io_stop & (io_busy | io_kick);
		dma_err <= ~dma_reset & (dma_err | dma_set_err);
		dma_intr <= ~clr_intr & (dma_intr | (dma_busy & dma_done));
	end

	// new pi registers;
	// access is controlled by PI_ACCESS register;

	// atb upper bits;
	// hold in register and joined for write of word;
	// write to PI_ATBU also invalidate the atb cache;

	wire atbu_we;			// write to atb upper bits;
	wire atb_inv;			// invalidate atb cache;
	reg [8:0] atbu;			// upper write bits of atb entry;

	assign atbu_we = reg_write & ra_atbu;
	assign atb_inv = dma_reset | atbu_we;

	always @(posedge sysclk)
	begin
		if(atbu_we)
			atbu <= pio_wdata[8:0];
	end

	// flash command register;
	// used directly for independent flash operations;
	// also used by pi dev processor for traditional pi dma;
	// don't start new command if controller is busy;
	// interrupt enable is cleared on reset;

	wire flc_addr_we;			// write flash address;
	reg [29:0] flc_addr;		// flash byte address;
	wire fl_ctrl_we;			// write flash cmd register;
	wire fl_ctrl_stop;			// stop flash controller;
	reg flc_wdph;				// write data phase;
	reg flc_rdph;				// read data phase;
	reg [3:0] flc_adph;			// address phase selects;
	reg [7:0] flc_cmd;			// flash command;
	reg flc_wrdy;				// wait for flash ready;
	reg flc_buf;				// data buffer to use for ctrl;
	wire flp_buf;				// data buffer to use for proc;
	reg flc_ecc;				// enable ecc detection/correction;
	reg flc_mcmd;				// multi-cycle command;
	reg [1:0] flc_dev;			// ctrl flash device;
	wire [1:0] flp_dev;			// proc flash device;
	reg [9:0] flc_size;			// size of data phase;
	reg flc_size_last;			// size reached last byte;
	wire flc_size_dec;			// decrement size;
	wire flc_nosize;			// do not use flc_size for dev proc;
	reg flc_start;				// ctrl start of flash operation;
	wire flp_start;				// proc start of flash operation;
	reg flc_stop;				// ctrl stop of flash operation;
	wire flp_stop;				// proc stop of flash operation;
	wire flc_busy;				// flash interface is busy;
	wire flc_done;				// flash operation done;
	reg flc_intr_en;			// flash interrupt enable;
	reg flc_intr;				// flash interrupt flag;
	wire flc_sbe;				// single-bit error;
	wire flc_dbe;				// double-bit error;
	wire [31:0] pi_fl_ctrl;		// pi aes control register;

	assign flc_addr_we = reg_write & ra_fl_addr & ~flc_busy;
	assign fl_ctrl_we = reg_write & ra_fl_ctrl & ~flc_busy;
	assign fl_ctrl_stop = reg_write & ra_fl_ctrl & ~pio_wdata[31];

	always @(posedge sysclk)
	begin
		if(reset)
			flc_intr_en <= 0;
		else if(fl_ctrl_we)
			flc_intr_en <= pio_wdata[30];
		if(fl_ctrl_we) begin
			flc_wdph <= pio_wdata[29];
			flc_rdph <= pio_wdata[28];
			flc_adph <= pio_wdata[27:24];
			flc_cmd <= pio_wdata[23:16];
			flc_wrdy <= pio_wdata[15];
			flc_buf <= pio_wdata[14];
			flc_dev <= pio_wdata[13:12];
			flc_ecc <= pio_wdata[11];
			flc_mcmd <= pio_wdata[10];
		end else if(flp_start) begin
			flc_buf <= flp_buf;
			flc_dev <= flp_dev;
		end
		if(fl_ctrl_we)
			flc_size <= pio_wdata[9:0];
		else if(~flc_nosize & flc_size_dec)
			flc_size <= flc_size - 1;
		flc_size_last <= ~flc_nosize & (flc_size == 10'd1);
		flc_start <= (fl_ctrl_we & pio_wdata[31]) | flp_start;
		flc_stop <= fl_ctrl_stop | flp_stop;
		flc_intr <= ~reset & flc_intr_en & (flc_intr | flc_done);
	end

	assign pi_fl_ctrl = { flc_busy, flc_intr,
		flc_wdph, flc_rdph, flc_adph, flc_cmd,
		flc_wrdy, flc_buf, flc_dev, flc_sbe, flc_dbe, flc_size };

	// flash config register;
	// controls timing for both the sm and module port;
	// default to slowest timing with enough setup/hold timing
	// that is enough for most older sm and nand flashes;
	//
	//	30..28	end of cycle time;
	//	26..24	read sample time;
	//	23..16	we active times;
	//	15..8	re active times;
	//	7..0	ale/cle active times;

	wire fl_conf_we;			// write flash config register;
	reg [31:0] flc_conf;		// flash config register;
	wire [31:0] flc_defc;		// default timing config;

	assign fl_conf_we = reg_write & ra_fl_conf;
	assign flc_defc = {
		1'b1,					// write protected;
		3'd7,					// 8 clock cycle;
		1'b0,					// unused;
		3'd5,					// read sample time;
		8'b00111110,			// ale/cle to re; setup 1, hold 2 clks;
		8'b00111110,			// ale/cle to we; setup 1, hold 2 clks;
		8'b11111111 };			// 8 clock cycle;

	always @(posedge sysclk)
	begin
		if(reset)
			flc_conf <= flc_defc;
		else if(fl_conf_we)
			flc_conf <= pio_wdata;
	end

	// aes control register;
	// used directly for independent aes operations;
	// also used by pi dev processor for traditional pi dma;
	// interrupt enable is cleared on reset;

	wire aes_ctrl_we;			// write to aes ctrl register;
	wire aesp_we;				// proc cmd issue;
	reg [7:1] aes_ia;			// ctrl buffer address of cbc init vector;
	reg [7:1] aesp_ia;			// proc init vector;
	reg aes_hc;					// ctrl hardware chaining;
	reg aesp_hc;				// proc hardware chaining;
	reg [7:1] aes_da;			// ctrl buffer address of data;
	wire [7:1] aesp_da;			// proc buffer address of data;
	reg [5:0] aes_size;			// ctrl # of 128-bit words to decrypt;
	wire [5:0] aesp_size;		// proc # of 128-bit words to decrypt;
	reg aes_start;				// start an aes operation;
	wire aesp_start;			// start proc aes operation;
	reg aes_stop;				// stop aes operation in progress;
	wire aesp_stop;				// stop proc aes operation;
	reg aes_intr_en;			// aes interrupt enable;
	reg aes_intr;				// aes interrupt flag;
	wire aes_busy;				// aes core is busy;
	wire aes_done;				// aes operation done;
	wire [31:0] pi_aes_ctrl;	// pi aes control register;
	wire aes_dw;				// aes double word done;

	assign aes_ctrl_we = reg_write & ra_aes_ctrl;

	always @(posedge sysclk)
	begin
		if(reset)
			aes_intr_en <= 0;
		else if(aes_ctrl_we)
			aes_intr_en <= pio_wdata[30];
		if(aes_ctrl_we) begin
			aes_size <= pio_wdata[21:16];
			aes_da <= pio_wdata[15:9];
			aes_ia <= pio_wdata[7:1];
			aes_hc <= pio_wdata[0];
		end else if(aesp_we) begin
			aes_size <= aesp_size;
			aes_da <= aesp_da;
			aes_ia <= aesp_ia;
			aes_hc <= aesp_hc;
		end
		aes_start <= (aes_ctrl_we & pio_wdata[31]) | aesp_start;
		aes_stop <= (aes_ctrl_we & ~pio_wdata[31]) | aesp_stop;
		aes_intr <= ~reset & aes_intr_en & (aes_intr | aes_done);
	end

	assign pi_aes_ctrl = { aes_busy, aes_intr, 6'd0,
		2'd0, aes_size, aes_da, 1'b0, aes_ia, aes_hc };

	// ide registers;
	// software must take io bus out of reset;
	// set defaults to pio mode 2 at 62.5MHz;

	wire ide_conf_we;			// write to ide config register;
	reg io_rst;					// io bus reset;
	reg [30:0] ide_conf;		// ide timing config register;
	wire [31:0] pi_ide_conf;	// value returned on reads;

	assign ide_conf_we = reg_write & ra_ide_conf;

	always @(posedge sysclk)
	begin
		if(reset) begin
			io_rst <= 1'b1;
			ide_conf <= { 5'd8, 5'd7, 5'd2, 6'd9, 5'd8, 5'd1 };
		end else if(ide_conf_we) begin
			io_rst <= pio_wdata[31];
			ide_conf <= pio_wdata[30:0];
		end
	end

	assign pi_ide_conf = { io_rst, ide_conf };

	// ide dma control register;
	// XXX

	// ioc gpio register;
	// latch id bits from io bus on rising edge of pin reset;
	// set gpio[1:0] to drive out 0 at falling edge of pin reset;
	// set gpio[3:2] to inputs at falling edge of pin reset;
	// sample id during pin reset only;
	// soft reset is too short for weak pull resistors to drive;

	wire gpio_we;				// write to gpio register;
	reg [15:0] ioc_id;			// id bits latched during reset;
	reg [3:0] gpio_oe;			// gpio configuration;
	reg [3:0] gpio_out;			// gpio output values;
	wire [31:0] pi_gpio;		// gpio read value;
	reg id_ena;					// sample id bits;

	assign gpio_we = reg_write & ra_gpio;

	always @(posedge sysclk)
	begin
		if(rst_l == 1'b0) begin
			gpio_oe <= 4'b0011;
			gpio_out <= 4'b0000;
		end else if(gpio_we) begin
			gpio_oe <= pio_wdata[7:4];
			gpio_out <= pio_wdata[3:0];
		end
		id_ena <= ~rst_l;
		if(id_ena)
			ioc_id <= io_in;
	end

	assign pi_gpio = { ioc_id, 8'd0, gpio_oe, gpio_in };

	// access control register;
	// all bits are writable in secure mode;
	// right can only be taken away in non-secure mode;

	reg [7:0] acc_ctrl;		// access control register;
	wire [31:0] pi_access;

	always @(posedge sysclk)
	begin
		if(reset)
			acc_ctrl <= 8'd0;
		else if(reg_write & ra_access)
			acc_ctrl <= pio_wdata[7:0] & acc_ena;
	end

	assign acc_ena = {8{sec_mode}} | acc_ctrl;
	assign pi_access = { 24'd0, acc_ctrl };

	// pi error register;
	// fatal error handling;
	// detect changes in module presense;

	wire wr_trap;			// write trap;
	wire [3:2] error_ecc;	// cor/unc ecc error;
	wire [1:0] error_atb;	// atb errors;
	reg error_sk;			// secure kernel trap on error;
	reg error_int;			// error interrupt on error;
	reg [4:0] error;		// error status bits;
	wire error_we;			// write PI_ERROR;
	wire error_loga;		// errors for which to log virtual address;
	reg error_aden;			// capture error address;
	reg [29:8] error_addr;	// error address;
	wire error_val;			// valid error, unc ecc or atb;
	wire [29:8] proc_addr;	// process device address;
	wire [31:0] pi_error;	// read value;

	assign error_we = reg_write & ra_error;
	assign wr_trap = dma_trap | io_write;

	always @(posedge sysclk)
	begin
		if(reset) begin
			error_sk <= 1'b0;
			error_int <= 1'b0;
			error[4:0] <= 5'd0;
		end else if(error_we) begin
			error_sk <= pio_wdata[31];
			error_int <= pio_wdata[30];
			error <= pio_wdata[4:0];
		end else
			error <= error | { wr_trap, error_ecc, error_atb };
		error_aden <= (error[3:0] == 4'd0) & error_loga;
		if(error_aden)
			error_addr <= proc_addr;
	end

	assign error_loga = |{ error_ecc, error_atb };
	assign error_val = |{ error[4], error[2:0] };
	assign err_trap = error_sk & error_val;
	assign err_intr = error_int & error_val;
	assign pi_error = { error_sk, error_int, error_addr, 3'd0, error };

	// pi buffer sram;
	// this is the core of the data paths;
	// synchronous single-port 256xN bits, writable in N/2 units;
	// can be accessed from both the cbus and dbus;
	// dbus cycles have highest priority and preempt everything else;
	// register buufer read data for atb and io logic;

	wire buf_ena;			// enable buffer read/write;
	wire [7:0] buf_addr;	// buffer word address;
	wire [40:0] buf_doh;	// upper buffer read data;
	wire [40:0] buf_dol;	// lower buffer read data;
	wire [40:0] buf_dih;	// upper buffer write data;
	wire [40:0] buf_dil;	// lower buffer write data;
	wire [1:0] buf_we;		// buffer write enables;

	pi_buf pibuf (
		.clk(sysclk),
		.csb(~buf_ena),
		.addr(buf_addr),
		.dih(buf_dih),
		.dil(buf_dil),
		.web(~buf_we),
		.doh(buf_doh),
		.dol(buf_dol)
	);

	// dbus read interface requires 16-bit barrel shifter;
	// placed between sram and register, there is enough time;
	// shifts only enabled for dbus reads;

	reg [1:0] buf_shl;		// # of barrel left shifts;
	wire [63:0] buf_dor;	// data read from pi buffer;
	wire [63:0] buf_doa;	// output of first row muxes;
	wire [63:0] buf_dob;	// output of second row muxes;
	reg [40:0] buf_rdoh;	// registered upper buffer read data;
	reg [40:0] buf_rdol;	// registered lower buffer read data;

	assign buf_dor = { buf_doh[31:0], buf_dol[31:0] };
	assign buf_doa[63:48] = buf_shl[0]? buf_dor[47:32] : buf_dor[63:48];
	assign buf_doa[47:32] = buf_shl[0]? buf_dor[31:16] : buf_dor[47:32];
	assign buf_doa[31:16] = buf_shl[0]? buf_dor[15:0]  : buf_dor[31:16];
	assign buf_doa[15:0]  = buf_shl[0]? buf_dor[63:48] : buf_dor[15:0];
	assign buf_dob[63:48] = buf_shl[1]? buf_doa[31:16] : buf_doa[63:48];
	assign buf_dob[47:32] = buf_shl[1]? buf_doa[15:0]  : buf_doa[47:32];
	assign buf_dob[31:16] = buf_shl[1]? buf_doa[63:48] : buf_doa[31:16];
	assign buf_dob[15:0]  = buf_shl[1]? buf_doa[47:32] : buf_doa[15:0];

	always @(posedge sysclk)
	begin
		buf_rdoh <= { buf_doh[40:32], buf_dob[63:32] };
		buf_rdol <= { buf_dol[40:32], buf_dob[31:0] };
	end

	// dbus data path;
	// buffer incoming data in register;
	// output data path has 16-bit piped barrel shifter for alignment;
	// 16-bit words because old pi had this alignment;
	// both dbus_shl and dbus_byp are constant for entire dma;
	// mem->pibuf dma must be aligned on 8-byte addresses;
	// pibuf->mem dma can use barrel shifter;

	reg [63:0] dbus_in;		// dbus input register;
	wire [63:0] dbus_rdo;	// registered & shifted buffer read data;
	reg [63:0] dbus_out;	// dbus output data;
	reg [2:0] dbus_shl;		// # of barrel left shifts;
	wire [3:0] dbus_byp;	// bypass selects;
	wire [6:0] dbus_addr;	// dbus buffer address;

	assign dbus_rdo = { buf_rdoh[31:0], buf_rdol[31:0] };

	always @(posedge sysclk)
	begin
		if(dma_kick)
			dbus_shl <= { 1'b0, dev_addr[2:1] } - { 1'b0, dma_addr[2:1] };
		dbus_in <= dbus_din;
		dbus_out[63:48] <= dbus_byp[3]? buf_dob[63:48] : dbus_rdo[63:48];
		dbus_out[47:32] <= dbus_byp[2]? buf_dob[47:32] : dbus_rdo[47:32];
		dbus_out[31:16] <= dbus_byp[1]? buf_dob[31:16] : dbus_rdo[31:16];
		dbus_out[15:0]  <= dbus_byp[0]? buf_dob[15:0]  : dbus_rdo[15:0];
	end

	assign dbus_dout = {64{dbus_enable}} & dbus_out;
	assign dbus_byp[0] = dbus_shl[1] | dbus_shl[0];
	assign dbus_byp[1] = dbus_shl[1];
	assign dbus_byp[2] = dbus_shl[1] & dbus_shl[0];
	assign dbus_byp[3] = 1'b0;
	assign dbus_shr = dbus_shl[2];
	assign dbus_addr = dbus_shr? dev_addr[9:3] - 1 : dev_addr[9:3];

	// pi buffer arbitration;
	// requestors are cbus, dbus, and device side;
	// dbus is highest priority and preempts cbus and device side;
	// longest dbus burst is 128 bytes, 16 dbus cycles;
	// cbus requests fail if dma interferes;
	// software can avoid conflict or check buf_err; //XXX
	// device side stalls during dbus accesses;
	// buf_win: 00=device, 01=dbus, 10=cbus;

	wire buf_dbus_req;			// dbus requesting buffer;
	wire buf_cbus_req;			// cbus requesting buffer;
	wire buf_dev_req;			// device side requesting buffer;
	wire buf_dev_ack;			// device side won buffer;
	reg [2:0] buf_win;			// winner of buffer arbitration;

	assign buf_dbus_req = bdma_val | (bdma_dval[0] & |dbus_shl);
	assign buf_cbus_req = (cbus_rw & cbus_buf) | io_rbuf;

	always @(posedge sysclk)
	begin
		buf_win[0] <= ~reset & buf_dbus_req;
		buf_win[1] <= ~reset & ~buf_dbus_req & buf_cbus_req;
		buf_win[2] <= ~reset & (buf_dbus_req | buf_cbus_req | buf_dev_req);
		buf_shl <= {2{buf_win[0]}} & dbus_shl;
	end

	assign buf_ena = buf_win[2];
	assign buf_dev_ack = (buf_win == 3'b100);

	// pi buffer address mux;
	// select dbus address, cbus address or device address;

	wire [7:0] buf_dbus_addr;	// pibuf dbus address;
	wire [7:0] buf_cbus_addr;	// pibuf cbus address;
	wire [8:0] buf_dev_addr;	// pibuf device address;

	assign buf_dbus_addr = { 1'b0, dbus_addr };
	assign buf_cbus_addr = pio_baddr;

	assign buf_addr = buf_win[0]? buf_dbus_addr
		: buf_win[1]? buf_cbus_addr
		: buf_dev_addr[8:1];

	// pi buffer write enable mux;
	// select write enable from dbus, cbus or device side;
	// atb never writes;
	// devices write 32-bit words;

	wire buf_dev_write;			// device write cycle;
	wire [1:0] buf_dev_we;		// device side write enables;

	assign buf_dev_we[1] = buf_dev_write & ~buf_dev_addr[0];
	assign buf_dev_we[0] = buf_dev_write & buf_dev_addr[0];

	assign buf_we = buf_win[0]? {2{dma_read}}
		: buf_win[1]? {2{pio_write}} & pio_bufen[1:0]
		: buf_dev_we;

	// pi buffer write data mux;
	// atb is never written by the device side;
	// always stick upper atb bits into all write data;

	wire [31:0] buf_dev_wdata;	// device write data;
	wire [31:0] buf_dix;		// device or pio write data;

	assign buf_dix = buf_win[1]? pio_wdata : buf_dev_wdata;
	assign buf_dih = { atbu, buf_win[0]? dbus_in[63:32] : buf_dix };
	assign buf_dil = { atbu, buf_win[0]? dbus_in[31:0] : buf_dix };

	// register buffer read data for atb block;
	// mux and register read data for io devices;

	reg buf_sel;			// 32-bit read word select;
	reg [31:0] buf_rdo;		// read data for io devices;
	wire [31:0] buf_dou;	// upper read bits of atb pair;

	always @(posedge sysclk)
	begin
		buf_sel <= buf_win[2] & buf_dev_addr[0];
		buf_rdo <= buf_sel? buf_dol[31:0] : buf_doh[31:0];
	end

	assign buf_dou = { 7'd0, buf_doh[40:32], 7'd0, buf_dol[40:32] };

	// cbus response data mux;

	reg [31:0] reg_data;		// register response data;
	reg [2:0] rsp_sel;			// response word selects;
	reg [31:0] rsp_data;		// read response data;
	wire [3:0] pi_status;		// pi status;

	assign pi_status = { dma_intr, dma_err, io_busy, dma_busy };

	always @(posedge sysclk)
	begin
		reg_data <= ({32{ra_dev_addr}} & { 2'd0, dev_addr })
			| ({32{ra_dma_len}} & { 8'd0, dma_len })
			| ({32{ra_status}} & { 24'd0, 4'd0, pi_status })
			| ({32{ra_fl_ctrl}} & pi_fl_ctrl)
			| ({32{ra_fl_conf}} & flc_conf)
			| ({32{ra_fl_addr}} & { 2'd0, flc_addr })
			| ({32{ra_aes_ctrl}} & pi_aes_ctrl)
			| ({32{ra_access}} & pi_access)
			| ({32{ra_gpio}} & pi_gpio)
			| ({32{ra_ide_conf}} & pi_ide_conf)
			| ({32{ra_error}} & pi_error)
			| ({32{ra_edata}} & io_wdata);
		rsp_sel <= pio_bufen | io_bufen;
		if(pio_ack) begin
			rsp_data <= reg_data
				| { 2 {{16{ide_acc}} & ide_di}}
				| ({32{rsp_sel[2]}} & buf_dou)
				| ({32{rsp_sel[1]}} & buf_doh[31:0])
				| ({32{rsp_sel[0]}} & buf_dol[31:0]);
		end
	end

	// cbus write data mux;
	// selects dma address, read length, write length or response data;
	// default to response data, because they toggle the least;

	wire cbus_sel_addr;		// cbus wants dma address;
	wire cbus_sel_len;		// cbus wants dma length;
	wire cbus_sel_data;		// cbus wants response data;
	wire cbus_out_addr;		// cbus wants dma_addr as response;
	wire [7:0] dma_delay;	// fixed in ri;

	assign cbus_sel_addr = (cbus_select == `CBUS_SEL_ADDR);
	assign cbus_sel_len = (cbus_select == `CBUS_SEL_LEN);
	assign cbus_sel_data = (cbus_select == `CBUS_SEL_DATA);
	assign cbus_out_addr = cbus_sel_addr | (cbus_sel_data & ra_dma_addr);
	assign dma_delay = 8'd0;

	assign cbus_out = cbus_out_addr? { 6'd0, dma_addr }
		: cbus_sel_len? { `CBUS_DEV_PI, dma_delay, dma_read, bdma_len }
		: rsp_data;

	// device side buffer arbitration;
	// aes needs back-to-back access for performance;
	// atb, flash and ide are in the delayed arbitration path;
	// reason for delayed device arbitration is logic depth of main arbiter;
	//
	// requestors (in order or priority) are:
	//		aes		read, write
	//		flash	read, write
	//		atb		read
	//		ide		read, write

	wire [8:0] flb_addr;		// flash buffer address;
	wire flb_req;				// flash buffer request;
	wire flb_write;				// flash buffer write;
	wire flb_ack;				// flash buffer ack;
	wire [31:0] flb_wdata;		// flash write data;

	wire [8:0] aes_addr;		// aes buffer address;
	wire aes_req;				// aes buffer request;
	wire aes_write;				// aes buffer write;
	wire aes_ack;				// aes acknowledge;
	wire [31:0] aes_wdata;		// aes write data;

	wire [7:0] atb_addr;		// atb buffer address;
	wire atb_req;				// atb buffer request;
	wire atb_ack;				// atb acknowledge;

	reg [2:1] darb_req;			// delayed requestors;
	reg [2:0] darb_win;			// device arbitration winner;
	reg [8:0] darb_addr;		// delayed device address;
	reg darb_write;				// delayed device write enables;

	always @(posedge sysclk)
	begin
		darb_req[1] <= flb_req & ~flb_ack;
		darb_req[2] <= atb_req & ~atb_ack;
		darb_win[0] <= aes_req;
		darb_win[1] <= ~aes_req & darb_req[1];
		darb_win[2] <= ~aes_req & ~darb_req[1] & darb_req[2];
		darb_addr <= darb_req[1]? flb_addr : { atb_addr, 1'b0 };
		darb_write <= darb_req[1]? flb_write : 1'b0;
	end

	assign buf_dev_req = aes_req | (darb_req[1] & ~flb_ack) | (darb_req[2] & ~atb_ack);
	assign aes_ack = buf_dev_ack & darb_win[0];
	assign flb_ack = buf_dev_ack & darb_win[1];
	assign atb_ack = buf_dev_ack & darb_win[2];

	// device buffer address mux;
	// device buffer write mux;

	assign buf_dev_addr = darb_win[0]? aes_addr : darb_addr;
	assign buf_dev_wdata = darb_win[0]? aes_wdata : flb_wdata;
	assign buf_dev_write = darb_win[0]? aes_write : darb_write;

	// instantiate address translation module;
	// maps virtual dma address to physical device address;

	reg atb_start;			// start atb lookup;
	wire atb_stop;			// stop atb operation;
	wire atb_map;			// do virtual to physical mapping;
	wire atb_done;			// atb lookup done or error;
	reg [29:0] atb_vaddr;	// address to map;
	wire [1:0] atb_udev;	// unmapped device;
	wire atb_pio;			// pio access;
	wire [29:0] atb_paddr;	// mapped address;
	wire [1:0] atb_pdev;	// mapped device;
	wire atb_piv;			// use buffer iv;
	wire atb_err;			// atb mapping/access error;

	assign atb_udev = 2'd0;
	assign atb_map = 1;
	assign atb_pio = io_busy;

	pi_atb atb (
		.sysclk(sysclk),
		.reset(reset),
		.atb_start(atb_start),
		.atb_stop(atb_stop),
		.atb_vaddr(atb_vaddr[29:14]),
		.atb_udev(atb_udev),
		.atb_pio(atb_pio),
		.atb_map(atb_map),
		.atb_inv(atb_inv),
		.atb_done(atb_done),
		.atb_paddr(atb_paddr[29:14]),
		.atb_pdev(atb_pdev),
		.atb_piv(atb_piv),
		.atb_err(atb_err),
		.atb_addr(atb_addr),
		.atb_req(atb_req),
		.atb_ack(atb_ack),
		.atb_h(buf_rdoh),
		.atb_l(buf_rdol)
	);

	assign atb_paddr[13:0] = atb_vaddr[13:0];

	// instantiate io bus controller;
	// protocol identical to ide, except for address output;

	wire flc_breq;			// flash io bus request;
	wire flc_bgnt;			// io bus granted to flash;
	wire flc_bre;			// flash io bus read enable;
	wire flc_brd;			// flash read from io bus;
	wire [15:0] flc_out;	// flash write data;

	pi_ioc ioc (
		.sysclk(sysclk),
		.reset(reset),
		.io_in(io_in),
		.io_ena(io_ena),
		.io_out(io_out),
		.io_oe(io_oe),
		.io_ale(io_ale),
		.io_ior(io_ior),
		.io_iow(io_iow),
		.io_cs(io_cs),
		.io_dmarq(io_dmarq),
		.io_dmack(io_dmack),
		.io_intr(io_intr),
		.flc_breq(flc_breq),
		.flc_bgnt(flc_bgnt),
		.flc_bre(flc_bre),
		.flc_brd(flc_brd),
		.flc_out(flc_out),
		.but_req(lctrl_req),
		.but_val(lctrl_val),
		.ide_conf(ide_conf),
		.ide_stall(ide_stall),
		.ide_acc(ide_acc),
		.ide_req(ide_req),
		.ide_addr(pio_addr[18:1]),
		.ide_write(pio_write),
		.ide_rack(ide_rack),
		.ide_do(pio_wdata),
		.ide_di(ide_di),
		.ide_intr(ide_intr)
	);

	assign lctrl_but = io_in[13:0];

	// instantiate nand flash controller;
	// executes flash commands between pi buffer and interface;
	// handles ecc calculation, correction and detection;

	pi_flash flc (
		.sysclk(sysclk),
		.reset(reset),
		.flc_conf(flc_conf),
		.flc_start(flc_start),
		.flc_stop(flc_stop),
		.flc_busy(flc_busy),
		.flc_done(flc_done),
		.flc_addr(flc_addr),
		.flc_dev(flc_dev),
		.flc_ecc(flc_ecc),
		.flc_mcmd(flc_mcmd),
		.flc_buf(flc_buf),
		.flc_cmd(flc_cmd),
		.flc_adph(flc_adph),
		.flc_rdph(flc_rdph),
		.flc_wdph(flc_wdph),
		.flc_wrdy(flc_wrdy),
		.flc_breq(flc_breq),
		.flc_bgnt(flc_bgnt),
		.flc_bre(flc_bre),
		.flc_in(io_in),
		.flc_brd(flc_brd),
		.flc_out(flc_out),
		.flc_size_dec(flc_size_dec),
		.flc_size_last(flc_size_last),
		.flc_sbe(flc_sbe),
		.flc_dbe(flc_dbe),
		.flb_addr(flb_addr),
		.flb_req(flb_req),
		.flb_write(flb_write),
		.flb_ack(flb_ack),
		.flb_in(buf_rdo),
		.flb_out(flb_wdata),
		.fl_ce(fl_ce),
		.fl_ale(fl_ale),
		.fl_cle(fl_cle),
		.fl_re(fl_re),
		.fl_we(fl_we),
		.fl_wp(fl_wp),
		.fl_ryby(fl_ryby)
	);

	// instantiate aes cbc decryption module;
	// handles data decryption in pi buffer in place;
	// expanded key is stored in pi buffer;

	pi_aes aes (
		.sysclk(sysclk),
		.reset_l(reset_l),
		.aes_start(aes_start),
		.aes_stop(aes_stop),
		.aes_busy(aes_busy),
		.aes_ia(aes_ia),
		.aes_hc(aes_hc),
		.aes_da(aes_da),
		.aes_size(aes_size),
		.aes_done(aes_done),
		.aes_addr(aes_addr),
		.aes_req(aes_req),
		.aes_write(aes_write),
		.aes_ack(aes_ack),
		.aes_in({ buf_rdoh[31:0], buf_rdol[31:0] }),
		.aes_out(aes_wdata),
		.aes_dw(aes_dw)
	);

	// device side processor;
	// handles both traditional dma and buffer dma;
	// state graph;
	//
	//	atb read aes dma rblk
	//	 |
	//	 |---0
	//	     0
	//	     0
	//	 |---0----0-------0
	//	 |        0   0   0
	//	 |---1    0       0
	//	     1    0---0   0
	//	     1        0   0
	//	 |---1----1
	//	 |        1
	//	 |---0    1
	//	     0    1---1
	//	     0        1
	//
	// stop process at reset or when mem dma length has reached 0;
	// stop when flash module is detected missing;
	// a dma length of 0 completes immediatedly without data movement;

	reg proc_start;			// start dev processor;
	wire proc_done;			// dev processor is done;
	wire proc_stop;			// stop device side;
	reg proc_busy;			// dev processor busy;
	wire proc_rblk;			// block next read while aes/bdma is busy;

	assign proc_done = dma_len_zero & (proc_start | proc_busy);
	assign proc_stop = dma_reset | proc_done | io_done[0] | (proc_busy & fl_md);
	assign dma_done = proc_done | bdma_done;

	always @(posedge sysclk)
	begin
		proc_start <= dma_proc | io_kick;
		proc_busy <= ~proc_stop & (proc_busy | proc_start);
	end

	// atb process;
	// start lookup on start of dma;
	// start lookup after error-free completion of flash read;
	// atb lookup runs parallel to aes decryption;
	// stop on any atb error;

	wire atb_lookup;		// do an atb lookup;
	wire atb_inc;			// start next atb lookup;
	wire atb_fin;			// atb finished;
	wire atb_ok;			// atb finished without error;
	reg atb_badiv;			// illegal iv location;
	wire atb_fail;			// atb lookup failed;

	assign atb_stop = proc_stop;
	assign atb_lookup = proc_start | atb_inc;

	always @(posedge sysclk)
	begin
		atb_start <= ~proc_stop & atb_lookup;
		if(dma_proc)
			atb_vaddr <= dev_addr - 30'd16;
		else if(io_kick)
			atb_vaddr <= { pio_addr[29:9], 9'd0 } - 30'd16;
		else if(atb_inc)
			atb_vaddr <= { atb_vaddr[29:9] + 1, 9'd0 };
		atb_badiv <= (atb_vaddr[13:4] != 10'h3ff);
	end

	assign atb_fin = proc_busy & atb_done;
	assign atb_fail = (atb_piv & atb_badiv) | atb_err;
	assign atb_ok = atb_fin & ~atb_fail;
	assign proc_addr = atb_vaddr[29:8];
	assign error_atb[1] = atb_fin & atb_fail & dma_busy;
	assign error_atb[0] = atb_fin & atb_fail & io_busy;

	// flash read process;
	// start flash read after successful atb lookup;
	// align flash address to 256-byte blocks, due to ecc checking;

	reg flp_stall;			// wait with aes until bdma is done;
	wire flp_fin;			// flash request finished;
	reg flp_ok;				// flash request finished without error;

	assign flp_start = atb_ok & ~atb_piv;
	assign flp_stop = proc_stop;
	assign flp_buf = atb_paddr[9];
	assign flp_dev = atb_pdev;
	assign flc_nosize = proc_busy;

	always @(posedge sysclk)
	begin
		if(proc_busy)
			flc_addr <= { atb_paddr[29:8], 8'h00 };
		else if(flc_addr_we)
			flc_addr <= pio_wdata[29:0];
		flp_stall <= proc_busy & ((proc_rblk & flp_stall) | flp_fin);
		flp_ok <= (atb_ok & atb_piv) | (~proc_rblk & flp_stall & ~flc_dbe);
	end

	assign flp_fin = proc_busy & flc_done;
	assign atb_inc = flp_ok;
	assign error_ecc[3] = flp_fin & flc_sbe;
	assign error_ecc[2] = flp_fin & flc_dbe;

	// aes process;
	// start after successful flash read;
	// data address is 256-byte aligned, in buffer 0 or 1;
	// decrypt only the involved 16-byte blocks;
	// use hardware cbc chaining after first block;
	// determine # of aes blocks to decrypt;
	// do not start aes if init vector is only block in buffer;

	reg aesp_first;			// first proc aes request;
	wire [5:0] aesp_ioff;	// iv offset in buffer;
	wire aesp_ionly;		// only iv at end of buffer;
	reg aesp_zoff;			// zero data offset;
	reg [5:0] aesp_doff;	// data offset in buffer;

	assign aesp_ioff = atb_paddr[9:4];
	assign aesp_ionly = aesp_ia[7] | (aesp_ia[5:1] == 5'd31);

	always @(posedge sysclk)
	begin
		aesp_first <= ~proc_stop & ~aesp_we & (aesp_first | proc_start);
		if(aesp_first)
			aesp_ia <= atb_piv? 7'd77 : { 1'b0, aesp_ioff };
		aesp_hc <= ~proc_start & (aesp_hc | aes_done);
		aesp_zoff <= aesp_hc | aesp_ionly;
		aesp_doff <= aesp_zoff? aesp_ioff : (aesp_ioff + 1);
	end

	assign aesp_we = flp_ok;
	assign aesp_start = flp_ok & ~(aesp_first & aesp_ionly);
	assign aesp_stop = proc_stop;
	assign aesp_da = { 1'b0, aesp_doff };
	assign aesp_size = { 1'b0, ~aesp_doff[4:0] };

	// pio completion;
	// on atb errors, ecc errors, or module removal;
	// after aes has decrypted entire 512-byte flash block;

	wire io_err_set;		// pio aborted due to errors;

	assign io_err_set = error_atb[0] | error_ecc[2] | fl_md;

	always @(posedge sysclk)
	begin
		io_err <= ~io_kick & (io_err | io_err_set);
		io_done[0] <= io_hit | (io_busy & (io_err | aes_done));
		io_done[2:1] <= io_done[1:0];
	end

	// aes data count;
	// amount of data that has passed the aes process;
	// kick burst dma when enough data to fill a dma cycle;

	wire dev_off_nz;		// dev_addr not aligned to aes blocks;
	reg [10:1] aesp_cnt;	// data count;
	wire aesp_cnt_inc;		// aes done with another double-word;
	wire aesp_cnt_dec;		// bdma moved another word;

	assign dev_off_nz = (dev_addr[3:1] != 3'd0);

	always @(posedge sysclk)
	begin
		if(proc_start) begin
			aesp_cnt[10:4] <= {7{dev_off_nz}};
			aesp_cnt[3:1] <= (~dev_addr[3:1] + 1);
		end if(aesp_cnt_inc & ~aesp_cnt_dec)
			aesp_cnt <= aesp_cnt + 4;
		else if(aesp_cnt_dec & ~aesp_cnt_inc)
			aesp_cnt <= aesp_cnt - 4;
		bdma_aesp <= proc_busy & ~aesp_cnt[10]
			& (aesp_cnt[9:1] > { 3'd0, bdma_len[6:1] });
	end

	assign aesp_cnt_inc = aes_dw;
	assign aesp_cnt_dec = bdma_dval[0];
	assign proc_rblk = ~aesp_cnt[10] & |aesp_cnt[9:8];

	// assertions;
	// synopsys translate_off

	always @(posedge sysclk)
	begin
		if(proc_busy & aesp_cnt[10] & aesp_cnt_dec)
			$display("ERROR: %t: %M: bdma overran aes", $time);
	end

	// synopsys translate_on

endmodule