// BankAddr.v v1 Doug Solomon

module BankAddr (
	memclk,
	Reset,
	NextAddr,
	NextI,
	NextM,
	NextD,
	NextDevice,
	NextRead,
	NextLength,
	NextM36,
	Pr0StB0,
	Bk0RAS,
	Bk1RAS,

	Bk0Addr,
	Bk0MAddr,
	Bk0I,
	Bk0M,
	Bk0D,
	Bk0Device,
	Bk0Read,
	Bk0Length,
	Bk0M36,
	Bk1Addr,
	Bk1MAddr,
	Bk1I,
	Bk1M,
	Bk1D,
	Bk1Device,
	Bk1Read,
	Bk1Length,
	Bk1M36,
	Pr0I,
	Pr0D,
	Pr0Device,
	Pr0Addr,
	Pr0Length,
	Pr0M36

);

	input		memclk;
	input		Reset;
	input	[27:0]	NextAddr;
	input		NextI;
	input		NextM;
	input		NextD;
	input	[3:0]	NextDevice;
	input		NextRead;
	input	[6:0]	NextLength;
	input		NextM36;
	input	[3:0]	Pr0StB0;
	input		Bk0RAS;
	input		Bk1RAS;

	output	[27:0]	Bk0Addr;
	output	[3:0]	Bk0MAddr;
	output		Bk0I;
	output		Bk0M;
	output		Bk0D;
	output	[3:0]	Bk0Device;
	output		Bk0Read;
	output	[6:0]	Bk0Length;
	output		Bk0M36;
	output	[27:0]	Bk1Addr;
	output	[3:0]	Bk1MAddr;
	output		Bk1I;
	output		Bk1M;
	output		Bk1D;
	output	[3:0]	Bk1Device;
	output		Bk1Read;
	output	[6:0]	Bk1Length;
	output		Bk1M36;
	output		Pr0I;
	output		Pr0D;
	output	[3:0]	Pr0Device;
	output	[6:3]	Pr0Addr;
	output	[6:0]	Pr0Length;
	output		Pr0M36;

	reg	Bk0RAS_del;
	always @(posedge memclk) 
			Bk0RAS_del <= Bk0RAS;
	reg	Bk1RAS_del;
	always @(posedge memclk) 
			Bk1RAS_del <= Bk1RAS;

	// Bank0 Address Register

	reg	[27:0]	hld_Bk0Addr;
	reg	[27:0]	hld_Bk1Addr;

	wire	[21:7]	inc_Bk1Addr_L =  Pr0D ? (hld_Bk1Addr[20:7] - 14'h1)
					      : (hld_Bk1Addr[20:7] + 14'h1);

	wire	[27:0]	inc_Bk1Addr   = {hld_Bk1Addr[27:21],
				         inc_Bk1Addr_L[20:7],
					 hld_Bk1Addr[6:0]};

	wire	[27:0]	adv_Bk0Addr = Pr0StB0[0] ?     NextAddr 
					         : inc_Bk1Addr;

	wire	[27:0]	Bk0Addr = Bk0RAS ? adv_Bk0Addr
					 : hld_Bk0Addr;
	
	wire	[3:0]	Bk0MAddr = Bk0RAS_del ? adv_Bk0Addr[3:0]
					      : hld_Bk0Addr[3:0];
	
	always @(posedge memclk) 
			hld_Bk0Addr <= Bk0Addr;

	// Bank0 Length Register
	
	reg		hld_Bk0I;
	reg		hld_Bk0M;
	reg		hld_Bk0D;
	reg	[3:0]	hld_Bk0Device;
	reg		hld_Bk0Read;
	reg	[6:0]	hld_Bk0Length;
	reg		hld_Bk0M36;

	reg		hld_Bk1I;
	reg		hld_Bk1M;
	reg		hld_Bk1D;
	reg	[3:0]	hld_Bk1Device;
	reg		hld_Bk1Read;
	reg	[6:0]	hld_Bk1Length;
	reg		hld_Bk1M36;

	// Capture and present relevant signals contained in the length
	// cycle one clock later that the address (RAS_del)

	wire		Bk0D = Bk0RAS_del ? (Pr0StB0[1] ? NextD : hld_Bk1D) 
					  :  hld_Bk0D;

	wire	[3:0]	Bk0Device = Bk0RAS_del ? (Pr0StB0[1] ? NextDevice 
						             : hld_Bk1Device) 
					    :  hld_Bk0Device;

	wire		Bk0Read   = Bk0RAS_del ? (Pr0StB0[1] ? NextRead 
						             : hld_Bk1Read) 
					    :  hld_Bk0Read;

	wire		Bk0I = Bk0RAS_del ? (Pr0StB0[1] ? NextI : hld_Bk1I) 
					  :  hld_Bk0I;

	wire		Bk0M = Bk0RAS_del ? (Pr0StB0[1] ? NextM : hld_Bk1M) 
					  :  hld_Bk0M;

	wire	[6:0]	Bk0Length = Bk0RAS_del ? (Pr0StB0[1] ? NextLength 
						             : hld_Bk1Length) 
					       :  hld_Bk0Length;

	wire		Bk0M36 = Bk0RAS_del ? (Pr0StB0[1] ? NextM36 
							  : hld_Bk1M36) 
					    :  hld_Bk0M36;

	always @(posedge memclk) 
	if (Reset) 
		begin
			hld_Bk0I <= 1'b0;
			hld_Bk0M <= 1'b0;
			hld_Bk0D <= 1'b0;
			hld_Bk0Device <= 4'b0;
			hld_Bk0Read   <= 1'b0;
			hld_Bk0Length <= 7'b0;
			hld_Bk0M36 <= 1'b0;
		end
	else	begin
			hld_Bk0I <= Bk0I;
			hld_Bk0M <= Bk0M;
			hld_Bk0D <= Bk0D;
			hld_Bk0Device <= Bk0Device;
			hld_Bk0Read   <= Bk0Read;
			hld_Bk0Length <= Bk0Length;
			hld_Bk0M36 <= Bk0M36;
		end

	// Bank1 Address Register

	wire	[21:7]	inc_Bk0Addr_L =  Pr0D ? (hld_Bk0Addr[20:7] - 14'h1)
					      : (hld_Bk0Addr[20:7] + 14'h1);

	wire	[27:0]	inc_Bk0Addr   = {hld_Bk0Addr[27:21],
				         inc_Bk0Addr_L[20:7],
					 hld_Bk0Addr[6:0]};

	wire	[27:0]	adv_Bk1Addr = Pr0StB0[2] ?     NextAddr 
					         : inc_Bk0Addr;

	wire	[27:0]	Bk1Addr = Bk1RAS ? adv_Bk1Addr
					 : hld_Bk1Addr;
	
	wire	[3:0]	Bk1MAddr = Bk1RAS_del ? adv_Bk1Addr[3:0]
					      : hld_Bk1Addr[3:0];
	
	always @(posedge memclk) 
			hld_Bk1Addr <= Bk1Addr;

	// Bank1 Length Register
	
	wire		Bk1D = Bk1RAS_del ? (Pr0StB0[3] ? NextD : hld_Bk0D) 
					  :  hld_Bk1D;

	wire	[3:0]	Bk1Device = Bk1RAS_del ? (Pr0StB0[3] ? NextDevice 
							     : hld_Bk0Device) 
					        :  hld_Bk1Device;

	wire		Bk1Read   = Bk1RAS_del ? (Pr0StB0[3] ? NextRead 
							     : hld_Bk0Read) 
					        :  hld_Bk1Read;

	wire		Bk1I = Bk1RAS_del ? (Pr0StB0[3] ? NextI : hld_Bk0I) 
					  :  hld_Bk1I;

	wire		Bk1M = Bk1RAS_del ? (Pr0StB0[3] ? NextM : hld_Bk0M) 
					  :  hld_Bk1M;

	wire	[6:0]	Bk1Length = Bk1RAS_del ? (Pr0StB0[3] ? NextLength 
							     : hld_Bk0Length) 
					       :  hld_Bk1Length;

	wire		Bk1M36 = Bk1RAS_del ? (Pr0StB0[3] ? NextM36 
							  : hld_Bk0M36) 
					    :  hld_Bk1M36;

	always @(posedge memclk) 
	if (Reset) 
		begin
			hld_Bk1I <= 1'b0;
			hld_Bk1M <= 1'b0;
			hld_Bk1D <= 1'b0;
			hld_Bk1Device <= 4'b0;
			hld_Bk1Read   <= 1'b0;
			hld_Bk1Length <= 7'b0;
			hld_Bk1M36 <= 1'b0;
		end
	else	begin
			hld_Bk1I <= Bk1I;
			hld_Bk1M <= Bk1M;
			hld_Bk1D <= Bk1D;
			hld_Bk1Device <= Bk1Device;
			hld_Bk1Read   <= Bk1Read;
			hld_Bk1Length <= Bk1Length;
			hld_Bk1M36 <= Bk1M36;
		end

	// Bank Pair 0 1 Multi-Bank Operation register

	wire	Pr0En = Pr0StB0[3] & (Bk0RAS_del | Bk1RAS_del);

	reg		hld_Pr0I;
	wire		Pr0I = Pr0En ? NextI : hld_Pr0I;

	reg		hld_Pr0D;
	wire		Pr0D = Pr0En ? NextD : hld_Pr0D;

	reg	[3:0]	hld_Pr0Device;
	wire	[3:0]	Pr0Device = Pr0En ? NextDevice : hld_Pr0Device;

	reg	[6:3]	hld_Pr0Addr;
	wire	[6:3]	Pr0Addr = Pr0En ? NextAddr[6:3] : hld_Pr0Addr;

	reg	[6:0]	hld_Pr0Length;
	wire	[6:0]	Pr0Length = Pr0En ? NextLength : hld_Pr0Length;

	reg		hld_Pr0M36;
	wire		Pr0M36 = Pr0En ? NextM36 : hld_Pr0M36;

	always @(posedge memclk) begin
			hld_Pr0I       <= Pr0I;
			hld_Pr0D       <= Pr0D;
			hld_Pr0Device  <= Pr0Device;
			hld_Pr0Addr    <= Pr0Addr;
			hld_Pr0Length  <= Pr0Length;
			hld_Pr0M36     <= Pr0M36;
	end

endmodule