module BankCtrl (
	memclk,
	Reset,
	AnyNextCMD,
	OtherCAS,
	OtherDCAS,
	Match,
	CASMatch,
	NAE,
	AllCCR,
	AllCCW,
	AllDone,
	P62p5,
	OtherStAi,
	OtherStA2,
	OtherStA3,
	OtherLastStA3,
	StB0,
	OtherStB0,
	StB1,
	nxt_StB1,
	MB1stAct,
	MBAct,
	Device,
	Read,
	Length,
	Addr,
	I,
	D,
	M,
	StRi,
	SBSel,
	TCL2,
	TCL3,
	TCL4,
	TRCD4,
	TRASp2,
	TRP4,
	Twdel,
	Trdel,
	M36,
	OtherWriteDone,
	OtherReadDone,
	MB1stRAS,
	APrechrg,

	StAi,
	StA2,
	StA3,
	LastStA3,
	XCnt,
	NextCMD,
	WCAS,
	RCAS,
	DCAS,
	PRAS,
	APCAS,
	RAS,
	StM0,
	ReadEn,
	CCR,
	nxt_Start,
	pre_start,
	nxt_Last,
	nxt_Done,
	Pend,
	BlockRdy,
	LastCAS,
	nxt_StRS0,
	WriteDone,
	ReadDone,
	DBusInEn,
	MB1stRASout,
	LastWCAS,
	StWS1
);
	
	input	memclk;
	input	Reset;
	input	AnyNextCMD;	// Next CMD for any bank
	input	OtherCAS;	// CAS from other bank (in the pair)
	input	OtherDCAS;	
	input	Match;		// cbus address matches bank
	input	CASMatch;	// Next CAS fifo matches bank
	input	NAE;		// Next Address Enable
	input	AllCCR;		// Cycle Complete Ready for Read
	input	AllCCW;		// Cycle Complete Ready for Write
	input	AllDone;
	input	P62p5;		// Phase of 62.5MHz clock
	input	OtherStAi;	// Other Bank (of pair) idle
	input	OtherStA2;	// Other Bank State A2
	input	OtherStA3;
	input	OtherLastStA3;
	input	StB0;		// Bank pair not engaged in a multi-bank op
	input	OtherStB0;	// B0 of other bank pair
	input	StB1;		// First part of multi-bank operation
	input	nxt_StB1;	// First part of multi-bank operation
	input	MB1stAct;	// 1st multi-bank activate
	input	MBAct;		// 1st, 2nd, 3rd or 4th multi-bank activate
	input	[3:0]	Device;
	input		Read;
	input	[6:3]	Length;
	input	[6:3]	Addr;	
	input		I;
	input		D;
	input		M;
	input		StRi;
	input		SBSel;
	input		TCL2;
	input		TCL3;
	input		TCL4;
	input		TRCD4;
	input		TRASp2;
	input		TRP4;
	input	[2:0]	Trdel;
	input	[2:0]	Twdel;
	input		M36;
	input		OtherWriteDone;
	input		OtherReadDone;
	input		MB1stRAS;
	input		APrechrg;

	output		StAi;
	output		StA2;
	output		StA3;
	output		LastStA3;
	output	[3:0]	XCnt;
	output		NextCMD;
	output		WCAS;
	output		RCAS;
	output		DCAS;
	output		PRAS;
	output		APCAS;
	output		RAS;
	output		StM0;
	output		ReadEn;
	output		CCR;
	output		nxt_Start;
	output		pre_start;
	output		nxt_Last;
	output		nxt_Done;
	output		Pend;
	output		BlockRdy;
	output		LastCAS;
	output		nxt_StRS0;
	output		WriteDone;
	output		ReadDone;
	output		DBusInEn;
	output		MB1stRASout;
	output		LastWCAS;
	output		StWS1;

	wire	[3:0]	BrstLen;

	reg		StA1_del;

	`define		DEV_SP		(Device==4'h0)	// rsp   
	`define		DEV_CMD		(Device==4'h1)	// rsp
	`define		DEV_SPAN	(Device==4'h2)	// rdp
	`define		DEV_MI		(Device==4'h3)
	`define		DEV_VI		(Device==4'h4)
	`define		DEV_SI		(Device==4'h5)
	`define		DEV_PI		(Device==4'h6)
	`define		DEV_RI		(Device==4'h7)
	`define		DEV_AI		(Device==4'h8)
	`define		DEV_MEM		(Device==4'h9)	// rsp
	`define		DEV_UI		(Device==4'hA)

	// Main Bank Control State Machine

	reg	StAi;		// Idle
	reg	StA0;		// Bounce here if another bank CAS, Precharge
	reg	StA1;		// RAS, Activate Bank
	reg	StAw;		
	reg	StA2;		
	reg	StAC;		
	reg	StAD;		
	reg	StA3;		// Wait here until CAS can occur
	reg	StM1,StM0;	// Aquire Write Mask from DBus
	reg	StRF,StWF;	// CAS
	reg	StRE,StWE;
	reg	StRWF,StWWF;	// Wait Cycle for M64
	reg	StRWE,StWWE;
	reg	StRD,StWD;	// CAS
	reg	StRC,StWC;
	reg	StRWD,StWWD;	// Wait Cycle for M64
	reg	StRWC,StWWC;
	reg	StRB,StWB;	// CAS
	reg	StRA,StWA;
	reg	StRWB,StWWB;	// Wait Cycle for M64
	reg	StRWA,StWWA;
	reg	StR9,StW9;	// CAS
	reg	StR8,StW8;	
	reg	StRW9,StWW9;	// Wait Cycle for M64
	reg	StRW8,StWW8;
	reg	StR7,StW7;	// CAS
	reg	StR6,StW6;
	reg	StRW7,StWW7;	// Wait Cycle for M64
	reg	StRW6,StWW6;
	reg	StR5,StW5;	// CAS
	reg	StR4,StW4;
	reg	StRW5,StWW5;	// Wait Cycle for M64
	reg	StRW4,StWW4;
	reg	StR3,StW3;	// CAS
	reg	StR2,StW2;
	reg	StRW3,StWW3;	// Wait Cycle for M64
	reg	StRW2,StWW2;
	reg	StR1,StW1;	// CAS
	reg	StR0,StW0;
	reg	StRW1,StWW1;	// Wait Cycle for M64
	reg	StRW0,StWW0;


	reg	     StWR0;
	reg	     StWR1;
	reg	     StWR2;
	reg	     StWR3;
	reg	StPC;
	reg	StPD;
	reg	StPE;
	reg	StPF;
	reg	StP0;
	reg	StP1;		// Issue manual precharge if unable to auto
	reg	StP2;		
	reg	StP3;
	reg	StP4;
	reg	StP5;
	reg	StP6;		// Final precharge, back to Ai

	reg	StRDi;
	reg	StRDH;
	reg	StRDG;
	reg	StRDF;
	reg	StRDE;
	reg	StRDD;
	reg	StRDC;
	reg	StRDB;
	reg	StRDA;
	reg	StRD9;
	reg	StRD8;
	reg	StRD7;
	reg	StRD6;
	reg	StRD5;
	reg	StRD4;
	reg	StRD3;
	reg	StRD2;
	reg	StRD1;
	reg	StRD0;

	reg	StWDi;
	reg	StWDD;
	reg	StWDC;
	reg	StWDB;
	reg	StWDA;
	reg	StWD9;
	reg	StWD8;
	reg	StWD7;
	reg	StWD6;
	reg	StWD5;
	reg	StWD4;
	reg	StWD3;
	reg	StWD2;
	reg	StWD1;
	reg	StWD0;

	reg	StWSi;
	reg	StWS0;
	reg	StWS1;
	reg	StWS2;
	reg	StWS3;
	reg	StWS4;
	reg	StWS5;

	reg	StAP0;
	reg	StAP1;
	reg	StAP2;
	reg	StAP3;
	reg	StAP4;
	reg	StAP5;
	reg	StAP6;

	reg	MPend;

	reg	StRSi;
	reg	StRS7;
	reg	StRS6;
	reg	StRS5;
	reg	StRS4;
	reg	StRS3;
	reg	StRS2;
	reg	StRS1;
	reg	StRS0;	// Read Start 

	reg	MB1stRASC;
	reg	MB1stRASD0;
	reg	MB1stRASD1;

	wire	TRD2 = (Trdel==3'b010);
	wire	TRD3 = (Trdel==3'b011);
	wire	TRD4 = (Trdel==3'b100);
	wire	TRD5 = (Trdel==3'b101);

	wire	TWD0 = (Twdel==3'b000);
	wire	TWD1 = (Twdel==3'b001);
	wire	TWD2 = (Twdel==3'b010);
	wire	TWD3 = (Twdel==3'b011);
	wire	TWD4 = (Twdel==3'b100);
	wire	TWD5 = (Twdel==3'b101);
	wire	TWD6 = (Twdel==3'b110);
	wire	TWD7 = (Twdel==3'b111);

	wire	BankBusy = ~(StAi & StB0 & OtherStB0 & 
			     StRi & StRSi & StRDi & StWSi);

	wire	Activate = NAE & Match & ~BankBusy
			 |       Pend  & ~BankBusy
			 |  MPend;


	wire	MBi	= StB0 				// single bank or the
			| StB1 & (TRCD4 | OtherStAi);	// the first of a multi
						   	// bank and the other 
						   	// bank is idle


	reg	d1AllDone;
	always @(posedge memclk) 
		d1AllDone <= AllDone;
	wire	StartRdDly = StA3 &  Read & AllCCR & CASMatch & MBi 
			   & d1AllDone &  P62p5 & StRDi;

	// synopsys translate_off
	wire	nxt_bugcheck3 = StA3 &  Read & AllCCR & CASMatch & MBi 
			      & ~AllDone & d1AllDone &  P62p5 & StRDi;
	reg	bugcheck3;
	always @(posedge memclk)
		bugcheck3 <= nxt_bugcheck3 & ~Reset;
	always @(bugcheck3) 
	if (bugcheck3) begin
	$display("ERROR: %t: %M: StartRdDly bug", $time);
	repeat (20) @(posedge memclk);
	$finish;
	end
	// synopsys translate_on

	wire	StartWrDly = StA3 & ~Read & AllCCW & CASMatch & MBi;

	wire	RdDlyDone =  `DEV_VI ? StRDA : StartRdDly;

	wire	WrDlyDone =  StWS0;

	wire	StartRdCmd = RdDlyDone & P62p5 		     // 1st
			   |  Read & ~(StB0 | StB1) & OtherReadDone; // 2nd-5th
	wire	StartWrCmd = WrDlyDone &  P62p5
			   | ~Read & ~(StB0 | StB1) & OtherWriteDone;

	wire	Mask = M & (StB0 | StB1);

	wire	nxt_StAi =          StP6 
			 |          StAi & ~Activate & ~MB1stAct
			 |  Reset;

	wire	nxt_StA0 = ~Reset & StAi &  Activate &  AnyNextCMD;

	wire	nxt_StA1 = ~Reset & StA0 
			 | ~Reset & StAi &  Activate & ~AnyNextCMD;

	wire	nxt_StAw = ~Reset & StA1 &  OtherStA3 & ~OtherLastStA3
			 | ~Reset & StAw & ~OtherLastStA3;

	wire	nxt_StA2 = ~Reset & StA1 & ~OtherStA3
			 | ~Reset & StA1 &  OtherLastStA3
			 | ~Reset & StAw &  OtherLastStA3
			 | ~Reset & StA1 & ~StB0
			 | ~Reset & StAi &  MB1stAct;

	wire	nxt_StAC = 
			   ~Reset & StA2 &  TRCD4 &  nxt_StB1
			 | ~Reset & StAC &  TRCD4 & ~OtherStAi;

	wire	nxt_StAD = 
			   ~Reset & StA2 &  TRCD4 & ~nxt_StB1 &  StB0
			 | ~Reset & StAC &  TRCD4 & OtherStAi & ~MB1stRASC;

	wire	nxt_StA3 = 
			   ~Reset & StA2 &  TRCD4 & ~nxt_StB1 & ~StB0
			 | ~Reset & StA2 & ~TRCD4
			 | ~Reset & StAC &  TRCD4 & OtherStAi &  MB1stRASC
			 | ~Reset & StAD &  TRCD4
			 | ~Reset & StA3 & ~StartWrCmd & ~StartRdCmd;

	wire	nxt_StRF = ~Reset & StA3 & (BrstLen==4'hf) & StartRdCmd;

	wire	nxt_StRE = ~Reset & StRF;

	wire	nxt_StRWF = ~Reset & StRE & ~M36
			  | ~Reset & StA3 & (BrstLen==4'he) & StartRdCmd;

	wire	nxt_StRWE = ~Reset & StRWF;

	wire	nxt_StRD = ~Reset & StA3 & (BrstLen==4'hd) & StartRdCmd
			 | ~Reset & StRE &  M36
			 | ~Reset & StRWE;

	wire	nxt_StRC = ~Reset & StRD;

	wire	nxt_StRWD = ~Reset & StRC & ~M36
			  | ~Reset & StA3 & (BrstLen==4'hc) & StartRdCmd;

	wire	nxt_StRWC = ~Reset & StRWD;

	wire	nxt_StRB = ~Reset & StA3 & (BrstLen==4'hb) & StartRdCmd
			 | ~Reset & StRC &  M36
			 | ~Reset & StRWC;

	wire	nxt_StRA = ~Reset & StRB;

	wire	nxt_StRWB = ~Reset & StRA & ~M36
			  | ~Reset & StA3 & (BrstLen==4'ha) & StartRdCmd;

	wire	nxt_StRWA = ~Reset & StRWB;

	wire	nxt_StR9 = ~Reset & StA3 & (BrstLen==4'h9) & StartRdCmd
			 | ~Reset & StRA &  M36
			 | ~Reset & StRWA;

	wire	nxt_StR8 = ~Reset & StR9;

	wire	nxt_StRW9 = ~Reset & StR8 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h8) & StartRdCmd;

	wire	nxt_StRW8 = ~Reset & StRW9;

	wire	nxt_StR7 = ~Reset & StA3 & (BrstLen==4'h7) & StartRdCmd
			 | ~Reset & StR8 &  M36
			 | ~Reset & StRW8;

	wire	nxt_StR6 = ~Reset & StR7;

	wire	nxt_StRW7 = ~Reset & StR6 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h6) & StartRdCmd;
	wire	nxt_StRW6 = ~Reset & StRW7;

	wire	nxt_StR5 = ~Reset & StA3 & (BrstLen==4'h5) & StartRdCmd
			 | ~Reset & StR6 &  M36
			 | ~Reset & StRW6;

	wire	nxt_StR4 = ~Reset & StR5;

	wire	nxt_StRW5 = ~Reset & StR4 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h4) & StartRdCmd;
	wire	nxt_StRW4 = ~Reset & StRW5;

	wire	nxt_StR3 = ~Reset & StA3 & (BrstLen==4'h3) & StartRdCmd
			 | ~Reset & StR4 &  M36
			 | ~Reset & StRW4;

	wire	nxt_StR2 = ~Reset & StR3;

	wire	nxt_StRW3 = ~Reset & StR2 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h2) & StartRdCmd;
	wire	nxt_StRW2 = ~Reset & StRW3;

	wire	nxt_StR1 = ~Reset & StA3 & (BrstLen==4'h1) & StartRdCmd
			 | ~Reset & StR2 &  M36
			 | ~Reset & StRW2;

	wire	nxt_StR0 = ~Reset & StR1;

	wire	nxt_StRW1 = ~Reset & StR0 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h0) & StartRdCmd;

	wire	nxt_StRW0 = ~Reset & StRW1;

	wire	nxt_StM0 = ~Reset & StA3 & StartWrCmd & Mask;

	wire	nxt_StM1 = ~Reset & StM0;

	wire	nxt_StWF = ~Reset & StA3 & (BrstLen==4'hf) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'hf);

	wire	nxt_StWE = ~Reset & StWF;

	wire	nxt_StWWF = ~Reset & StWE & ~M36
			  | ~Reset & StA3 & (BrstLen==4'he) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'he);

	wire	nxt_StWWE = ~Reset & StWWF;

	wire	nxt_StWD = ~Reset & StA3 & (BrstLen==4'hd) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'hd)
			 | ~Reset & StWE &  M36
			 | ~Reset & StWWE;

	wire	nxt_StWC = ~Reset & StWD;

	wire	nxt_StWWD = ~Reset & StWC & ~M36
			  | ~Reset & StA3 & (BrstLen==4'hc) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'hc);

	wire	nxt_StWWC = ~Reset & StWWD;

	wire	nxt_StWB = ~Reset & StA3 & (BrstLen==4'hb) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'hb)
			 | ~Reset & StWC &  M36
			 | ~Reset & StWWC;

	wire	nxt_StWA = ~Reset & StWB;

	wire	nxt_StWWB = ~Reset & StWA & ~M36
			  | ~Reset & StA3 & (BrstLen==4'ha) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'ha);

	wire	nxt_StWWA = ~Reset & StWWB;

	wire	nxt_StW9 = ~Reset & StA3 & (BrstLen==4'h9) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'h9)
			 | ~Reset & StWA &  M36
			 | ~Reset & StWWA;

	wire	nxt_StW8 = ~Reset & StW9;

	wire	nxt_StWW9 = ~Reset & StW8 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h8) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'h8);

	wire	nxt_StWW8 = ~Reset & StWW9;

	wire	nxt_StW7 = ~Reset & StA3 & (BrstLen==4'h7) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'h7)
			 | ~Reset & StW8 &  M36
			 | ~Reset & StWW8;

	wire	nxt_StW6 = ~Reset & StW7;

	wire	nxt_StWW7 = ~Reset & StW6 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h6) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'h6);

	wire	nxt_StWW6 = ~Reset & StWW7;

	wire	nxt_StW5 = ~Reset & StA3 & (BrstLen==4'h5) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'h5)
			 | ~Reset & StW6 &  M36
			 | ~Reset & StWW6;

	wire	nxt_StW4 = ~Reset & StW5;

	wire	nxt_StWW5 = ~Reset & StW4 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h4) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'h4);

	wire	nxt_StWW4 = ~Reset & StWW5;

	wire	nxt_StW3 = ~Reset & StA3 & (BrstLen==4'h3) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'h3)
			 | ~Reset & StW4 &  M36
			 | ~Reset & StWW4;

	wire	nxt_StW2 = ~Reset & StW3;

	wire	nxt_StWW3 = ~Reset & StW2 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h2) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'h2);

	wire	nxt_StWW2 = ~Reset & StWW3;

	wire	nxt_StW1 = ~Reset & StA3 & (BrstLen==4'h1) & StartWrCmd & ~Mask
			 | ~Reset & StM1 & (BrstLen==4'h1)
			 | ~Reset & StW2 &  M36
			 | ~Reset & StWW2;

	wire	nxt_StW0 = ~Reset & StW1;

	wire	nxt_StWW1 = ~Reset & StW0 & ~M36
			  | ~Reset & StA3 & (BrstLen==4'h0) & StartWrCmd & ~Mask
			  | ~Reset & StM1 & (BrstLen==4'h0);

	wire	nxt_StWW0 = ~Reset & StWW1;

	wire	nxt_StWR0= ~Reset & StW0 &  M36
			 | ~Reset & StWW0;

	wire	nxt_StWR1= ~Reset & StWR0;

	wire	nxt_StWR2= ~Reset &  TRASp2 & StWR1;

	wire	nxt_StWR3= ~Reset &  TRASp2 & StWR2;

	wire	nxt_StPC = ~Reset &  TRASp2 & ~StAP0 & (M36 ? StR0 : StRW0);

	wire	nxt_StPD = ~Reset &  TRASp2 & StPC;

	wire	nxt_StPE = ~Reset & ~TRASp2 & ~StAP0 & (M36 ? StR0 : StRW0)
			 | ~Reset &  TRASp2 & StPD;

	wire	nxt_StPF = ~Reset &  StPE;

	wire	nxt_StP0 = ~Reset &  StPF;

	wire	nxt_StP1 = ~Reset &  StAP0 & (M36 ? StR0 : StRW0)
			 | ~Reset &  StP0;

	wire	TRP3 = ~TRP4;

	wire	nxt_StP2 = ~Reset & StP1 &  StAP0 &  TCL4 & TRP4
			 | ~Reset & ~TRASp2 & StWR1 & TRP4
			 | ~Reset &  TRASp2 & StWR3 & TRP4;
	wire	nxt_StP3 = ~Reset & StP2
			 | ~Reset & StP1 &  StAP0 & (TCL3 & TRP4 | TCL4 & TRP3)
			 | ~Reset & ~TRASp2 & StWR1 & TRP3
			 | ~Reset &  TRASp2 & StWR3 & TRP3;
	wire	nxt_StP4 = ~Reset & StP3
			 | ~Reset & StP1 &  StAP0 & (TCL2 & TRP4 | TCL3 & TRP3)
			 | ~Reset & StP1 & ~StAP0 &  TRP4;
	wire	nxt_StP5 = ~Reset & StP4
			 | ~Reset & StP1 &  StAP0 & (              TCL2 & TRP3)
			 | ~Reset & StP1 & ~StAP0 &  TRP3;
	wire	nxt_StP6 = ~Reset & StP5;

	always @(posedge memclk) begin
		StAi <= nxt_StAi;
		StA0 <= nxt_StA0;
		StA1 <= nxt_StA1;
		StAw <= nxt_StAw;
		StA2 <= nxt_StA2;
		StAC <= nxt_StAC;
		StAD <= nxt_StAD;
		StA3 <= nxt_StA3;
		StM0 <= nxt_StM0;
		StM1 <= nxt_StM1;
		StRF <= nxt_StRF; StWF <= nxt_StWF;
		StRE <= nxt_StRE; StWE <= nxt_StWE;
		StRD <= nxt_StRD; StWD <= nxt_StWD;
		StRC <= nxt_StRC; StWC <= nxt_StWC;
		StRB <= nxt_StRB; StWB <= nxt_StWB;
		StRA <= nxt_StRA; StWA <= nxt_StWA;
		StR9 <= nxt_StR9; StW9 <= nxt_StW9;
		StR8 <= nxt_StR8; StW8 <= nxt_StW8;
		StR7 <= nxt_StR7; StW7 <= nxt_StW7;
		StR6 <= nxt_StR6; StW6 <= nxt_StW6;
		StR5 <= nxt_StR5; StW5 <= nxt_StW5;
		StR4 <= nxt_StR4; StW4 <= nxt_StW4;
		StR3 <= nxt_StR3; StW3 <= nxt_StW3;
		StR2 <= nxt_StR2; StW2 <= nxt_StW2;
		StR1 <= nxt_StR1; StW1 <= nxt_StW1;
		StR0 <= nxt_StR0; StW0 <= nxt_StW0;

		StRWF <= nxt_StRWF; StWWF <= nxt_StWWF;
		StRWE <= nxt_StRWE; StWWE <= nxt_StWWE;
		StRWD <= nxt_StRWD; StWWD <= nxt_StWWD;
		StRWC <= nxt_StRWC; StWWC <= nxt_StWWC;
		StRWB <= nxt_StRWB; StWWB <= nxt_StWWB;
		StRWA <= nxt_StRWA; StWWA <= nxt_StWWA;
		StRW9 <= nxt_StRW9; StWW9 <= nxt_StWW9;
		StRW8 <= nxt_StRW8; StWW8 <= nxt_StWW8;
		StRW7 <= nxt_StRW7; StWW7 <= nxt_StWW7;
		StRW6 <= nxt_StRW6; StWW6 <= nxt_StWW6;
		StRW5 <= nxt_StRW5; StWW5 <= nxt_StWW5;
		StRW4 <= nxt_StRW4; StWW4 <= nxt_StWW4;
		StRW3 <= nxt_StRW3; StWW3 <= nxt_StWW3;
		StRW2 <= nxt_StRW2; StWW2 <= nxt_StWW2;
		StRW1 <= nxt_StRW1; StWW1 <= nxt_StWW1;
		StRW0 <= nxt_StRW0; StWW0 <= nxt_StWW0;

		                  StWR0<= nxt_StWR0;
				  StWR1<= nxt_StWR1;
				  StWR2<= nxt_StWR2;
				  StWR3<= nxt_StWR3;
		StPC <= nxt_StPC;
		StPD <= nxt_StPD;
		StPE <= nxt_StPE;
		StPF <= nxt_StPF;
		StP0 <= nxt_StP0;
		StP1 <= nxt_StP1;
		StP2 <= nxt_StP2;
		StP3 <= nxt_StP3;
		StP4 <= nxt_StP4;
		StP5 <= nxt_StP5;
		StP6 <= nxt_StP6;
	end

	reg	BCnt0;
	reg	BCnt1;
	reg	BCnt2;

	// De-assert dma_ready on the departure from StAi only for
	// the first bank access.
	// Re-assert prior to asserting Start

	wire	StartRS;
	wire	StartWS;
	wire	nxt_WrStart;
	reg	WrStart;

	// Assert dma_ready one clock before the dma_start is asserted
	// to match the rcp

	reg	BlockRdy;

	wire	nxt_BlockRdy = ~BlockRdy & StA1 & ~MPend
			     |  BlockRdy & ~StRS0 & ~nxt_WrStart;

	always @(posedge memclk) 
		BlockRdy <= ~Reset & nxt_BlockRdy;

	always @(posedge memclk) 
		StA1_del <= ~Reset & StA1;

	reg	AnyCMD;
	always @(posedge memclk)
		AnyCMD <= ~Reset & AnyNextCMD;

	wire	LastStA3 = StA3 & (StartWrCmd | StartRdCmd);

	wire	WriteDone = M36 ? StW0 : StWW0;
	wire	ReadDone  = M36 ? StR0 : StRW0;

	// The following generates RAS for the first
	// activate to the opposite bank in a multi-bank
	// operation.   States AC and AD were added to
	// for increasing Trcd=4.

	wire	nxt_MB1stRASC  = ~StB0 & StAC & OtherStAi & ~AnyNextCMD;
	wire	nxt_MB1stRASD0 = ~StB0 & StAC & OtherStAi &  AnyNextCMD;

	always @(posedge memclk) begin
		MB1stRASC  <= ~Reset & nxt_MB1stRASC;
		MB1stRASD0 <= ~Reset & nxt_MB1stRASD0;
		MB1stRASD1 <= ~Reset & MB1stRASD0;
	end

	wire	MB1stRASout = MB1stRASC | MB1stRASD1;

	wire	nxt_bugcheck2 = MB1stRASout & AnyCMD;
	reg	bugcheck2;
	always @(posedge memclk)
		bugcheck2 <= nxt_bugcheck2 & ~Reset;
	// synopsys translate_off
	always @(bugcheck2) 
	if (bugcheck2) begin
	$display("ERROR: %t: %M: command overlap", $time);
	repeat (20) @(posedge memclk);
	$finish;
	end
	// synopsys translate_on

	// Auto-Precharge Detection State Machine
	// Determines whether an READA can be issued
	// based on whether Tras has been satisfied
	// Tras=7clocks if TRASp2=0
	// Tras=9clocks if TRASp2=1

	wire	RAS;

	wire	nxt_StAP0 =  StAP0 & ~RAS
			  |  StAP6 & ~(StP0 | StPC  | StPD |
					      StPE  | StPF |
				      (M36 ? (StR1  | StR0)
				           : (StRW1 | StRW0)))
			  |  Reset;

	wire	nxt_StAP1 = ~Reset & StAP0 & RAS;

	wire	nxt_StAP2 = ~Reset & StAP1;
	wire	nxt_StAP3 = ~Reset & StAP2;
	wire	nxt_StAP4 = ~Reset & StAP3 &  TRASp2;
	wire	nxt_StAP5 = ~Reset & StAP4;

	wire	nxt_StAP6 = ~Reset & StAP3 & ~TRASp2
			  | ~Reset & StAP5
			  | ~Reset & StAP6 & (StP0 | StPC  | StPD |
						     StPE  | StPF |
					     (M36 ? (StR1  | StR0)
						  : (StRW1 | StRW0)));

	always @(posedge memclk) begin
		StAP0 <= nxt_StAP0;
		StAP1 <= nxt_StAP1;
		StAP2 <= nxt_StAP2;
		StAP3 <= nxt_StAP3;
		StAP4 <= nxt_StAP4;
		StAP5 <= nxt_StAP5;
		StAP6 <= nxt_StAP6;
	end

	// Bank Pending - CBus Address tried to access, but the bank 
	// 		  is busy or a multibank operation is ongoing

	reg	Pend;

	wire	nxt_Pend =   ~Reset & ~Pend & NAE & Match & BankBusy
			   | ~Reset &  Pend & ~StA1
			   | ~Reset &  Pend & MPend;

	always @(posedge memclk) 
		Pend <= nxt_Pend;

	// Multi-Bank Pending
	//		An operation is pending due to a subsequent
	//  (i.e. not the first) activate of a multi-bank operation

	wire	MB234Act = MBAct & ~MB1stAct;

	wire	nxt_MPend = ~Reset & ~MPend & MB234Act
			  | ~Reset &  MPend & ~StA1;

	always @(posedge memclk) 
		MPend <= nxt_MPend;

	// Read Delay State Machine

	wire	nxt_StRDi = StRDi & ~(StartRdDly)
			  | StRD0;
	wire	nxt_StRDH = StRDi &  StartRdDly & `DEV_VI;
	wire	nxt_StRDG = StRDH;
	wire	nxt_StRDF = StRDG;
	wire	nxt_StRDE = StRDF;
	wire	nxt_StRDD = StRDE;
	wire	nxt_StRDC = StRDD;
	wire	nxt_StRDB = StRDC;
	wire	nxt_StRDA = StRDB;
	wire	nxt_StRD9 = StRDi &  StartRdDly & TRD5 & ~(`DEV_VI)
			  | StRDA &               TRD5;
	wire	nxt_StRD8 = StRD9;
	wire	nxt_StRD7 = StRD8
			  | StRDi &  StartRdDly & TRD4 & ~(`DEV_VI)
			  | StRDA &               TRD4;
	wire	nxt_StRD6 = StRD7;
	wire	nxt_StRD5 = StRD6
			  | StRDi &  StartRdDly & TRD3 & ~(`DEV_VI)
			  | StRDA &               TRD3;
	wire	nxt_StRD4 = StRD5;
	wire	nxt_StRD3 = StRD4
			  | StRDi &  StartRdDly & TRD2 & ~(`DEV_VI)
			  | StRDA &               TRD2;
	wire	nxt_StRD2 = StRD3;
	wire	nxt_StRD1 = StRD2;
	wire	nxt_StRD0 = StRD1;
	
	always @(posedge memclk) begin
		StRDi <= nxt_StRDi |  Reset;
		StRDH <= nxt_StRDH & ~Reset;
		StRDG <= nxt_StRDG & ~Reset;
		StRDF <= nxt_StRDF & ~Reset;
		StRDE <= nxt_StRDE & ~Reset;
		StRDD <= nxt_StRDD & ~Reset;
		StRDC <= nxt_StRDC & ~Reset;
		StRDB <= nxt_StRDB & ~Reset;
		StRDA <= nxt_StRDA & ~Reset;
		StRD9 <= nxt_StRD9 & ~Reset;
		StRD8 <= nxt_StRD8 & ~Reset;
		StRD7 <= nxt_StRD7 & ~Reset;
		StRD6 <= nxt_StRD6 & ~Reset;
		StRD5 <= nxt_StRD5 & ~Reset;
		StRD4 <= nxt_StRD4 & ~Reset;
		StRD3 <= nxt_StRD3 & ~Reset;
		StRD2 <= nxt_StRD2 & ~Reset;
		StRD1 <= nxt_StRD1 & ~Reset;
		StRD0 <= nxt_StRD0 & ~Reset;
	end

	// Read Start State Machine

	// Pipeline state machine, so the we return to StRSi when
	// entering StRS0.  Need to make sure that VI cycle doesn't
	// cause problems XXX

	assign	StartRS =  StRDA &   `DEV_VI
			|  StRD0 & ~(`DEV_VI);

	wire	nxt_StRSi = StRSi & ~StartRS
			  | StRS0 & ~P62p5
			  | StRS1
			  | Reset;

	wire	nxt_StRS7 = ~Reset & StRSi &  StartRS & `DEV_SI
			  | ~Reset & StRSi &  StartRS & `DEV_AI
			  | ~Reset & StRSi &  StartRS & `DEV_PI
			  | ~Reset & StRSi &  StartRS & `DEV_SP
			  | ~Reset & StRSi &  StartRS & `DEV_CMD
			  | ~Reset & StRSi &  StartRS & `DEV_SPAN
			  | ~Reset & StRSi &  StartRS & `DEV_UI
			  | ~Reset & StRSi &  StartRS & `DEV_VI &  TRD5;

	wire	nxt_StRS6 = ~Reset & StRS7;

	wire	nxt_StRS5 = ~Reset & StRSi &  StartRS & `DEV_MI  
			  | ~Reset & StRSi &  StartRS & `DEV_VI &  TRD4
			  | ~Reset & StRS6;

	wire	nxt_StRS4 = ~Reset & StRS5;
	wire	nxt_StRS3 = ~Reset & StRS4
			  | ~Reset & StRSi &  StartRS & `DEV_VI &  TRD3;
	wire	nxt_StRS2 = ~Reset & StRS3;
	wire	nxt_StRS1 = ~Reset & StRS2
			  | ~Reset & StRSi &  StartRS & `DEV_VI &  TRD2;
	wire	nxt_StRS0 = ~Reset & StRS1
			  | ~Reset & StRS0 & P62p5;

	always @(posedge memclk) begin
		StRSi <= nxt_StRSi;
		StRS0 <= nxt_StRS0;
		StRS1 <= nxt_StRS1;
		StRS2 <= nxt_StRS2;
		StRS3 <= nxt_StRS3;
		StRS4 <= nxt_StRS4;
		StRS5 <= nxt_StRS5;
		StRS6 <= nxt_StRS6;
		StRS7 <= nxt_StRS7;
	end

        // Write Delay State Machine

	wire	nxt_StWDi = StWDi & ~(StartWrDly)
			  | StWDi &  P62p5
			  | StWDi & ~P62p5 & StartWrDly & TWD0
			  | StWDi & ~StWSi
			  | StWD0;

	wire	nxt_StWDD = StWDi & StWSi & ~P62p5 & StartWrDly & TWD7;
	wire	nxt_StWDC = StWDD;
	wire	nxt_StWDB = StWDC
			  | StWDi & StWSi & ~P62p5 & StartWrDly & TWD6;
	wire	nxt_StWDA = StWDB;
	wire	nxt_StWD9 = StWDA
			  | StWDi & StWSi & ~P62p5 & StartWrDly & TWD5;
	wire	nxt_StWD8 = StWD9;
	wire	nxt_StWD7 = StWD8
			  | StWDi & StWSi & ~P62p5 & StartWrDly & TWD4;
	wire	nxt_StWD6 = StWD7;
	wire	nxt_StWD5 = StWD6
			  | StWDi & StWSi & ~P62p5 & StartWrDly & TWD3;
	wire	nxt_StWD4 = StWD5;
	wire	nxt_StWD3 = StWD4
			  | StWDi & StWSi & ~P62p5 & StartWrDly & TWD2;
	wire	nxt_StWD2 = StWD3;
	wire	nxt_StWD1 = StWD2
			  | StWDi & StWSi & ~P62p5 & StartWrDly & TWD1;
	wire	nxt_StWD0 = StWD1;

	always @(posedge memclk) begin
		StWDi <= nxt_StWDi |  Reset;
		StWDD <= nxt_StWDD & ~Reset;
		StWDC <= nxt_StWDC & ~Reset;
		StWDB <= nxt_StWDB & ~Reset;
		StWDA <= nxt_StWDA & ~Reset;
		StWD9 <= nxt_StWD9 & ~Reset;
		StWD8 <= nxt_StWD8 & ~Reset;
		StWD7 <= nxt_StWD7 & ~Reset;
		StWD6 <= nxt_StWD6 & ~Reset;
		StWD5 <= nxt_StWD5 & ~Reset;
		StWD4 <= nxt_StWD4 & ~Reset;
		StWD3 <= nxt_StWD3 & ~Reset;
		StWD2 <= nxt_StWD2 & ~Reset;
		StWD1 <= nxt_StWD1 & ~Reset;
		StWD0 <= nxt_StWD0 & ~Reset;
	end

	// Write Start State Machine
	// start signal occurs x number of clocks before 
	// the device is able to provide data where:
	//	Device	x
	//	MI	1
	//	SI	2
	//	SPAN	2
	//	PI	4
	//	SP	5

	assign	StartWS = StartWrDly & StWSi & StWDi &  TWD0
			|	       StWSi & StWD0 & ~TWD0;

	wire	nxt_StWSi =  StWSi & ~StartWS
			  |  StWSi &  P62p5
			  |  StWS0 & ~P62p5
			  |  Reset;

	wire	nxt_StWS0 = ~Reset & StWS1 & ~P62p5 
			  | ~Reset & StWS0 &  P62p5;

	wire	nxt_StWS1 = ~Reset & StWSi & ~P62p5 & StartWS & `DEV_MI
			  | ~Reset & StWSi & ~P62p5 & StartWS & `DEV_UI
			  | ~Reset & StWS2 & ~P62p5
			  | ~Reset & StWS1 &  P62p5;

	wire	nxt_StWS2 = ~Reset & StWSi & ~P62p5 & StartWS & `DEV_SPAN
			  | ~Reset & StWSi & ~P62p5 & StartWS & `DEV_SI
			  | ~Reset & StWS3 & ~P62p5
			  | ~Reset & StWS2 &  P62p5;

	wire	nxt_StWS3 = ~Reset & StWS4 & ~P62p5
			  | ~Reset & StWS3 &  P62p5;

	wire	nxt_StWS4 = ~Reset & StWSi & ~P62p5 & StartWS & `DEV_PI
			  | ~Reset & StWS5 & ~P62p5
			  | ~Reset & StWS4 &  P62p5;

	wire	nxt_StWS5 = ~Reset & StWSi & ~P62p5 & StartWS & `DEV_SP
			  | ~Reset & StWS5 &  P62p5;

	always @(posedge memclk) begin
		StWSi <= nxt_StWSi;
		StWS0 <= nxt_StWS0;
		StWS1 <= nxt_StWS1;
		StWS2 <= nxt_StWS2;
		StWS3 <= nxt_StWS3;
		StWS4 <= nxt_StWS4;
		StWS5 <= nxt_StWS5;
	end

	// CBus Start Signal for DMA Read/Write Operations

	reg	Start;

	assign	nxt_WrStart =  ~Reset & ~WrStart & StartWS & ~P62p5 
			    |  ~Reset &  WrStart & P62p5;

	wire	nxt_Start = nxt_WrStart | nxt_StRS0;

	wire	pre_start =  nxt_WrStart 
			  | (TRD2 ? nxt_StRS0 : (nxt_StRS2 | nxt_StRS1));

	always @(posedge memclk) begin
		WrStart <= nxt_WrStart;
		Start   <= nxt_Start;
	end

	// CBus Last Signal for DMA Read/Write Operations

	reg		Last;
	reg		Done;
	reg	[4:0]	DWCnt;
	reg	[4:0]	InitCnt;

	wire	[4:0]	nxt_InitCnt = 
			Reset ? 5'b0 
			      : StA1_del ? (Length[6:3] + {3'b0, M})
					 : InitCnt;

	// InitCnt is pipelined due to Length going away in StA2
	// XXX need to go over this carefully and maybe have seperate
	// InitCnt for WrStart and RdStart

	always @(posedge memclk) 
			InitCnt <= nxt_InitCnt;


	wire	[4:0]	nxt_DWCnt = 
			    Reset ? 5'b0
				  : P62p5 ? DWCnt
					  : nxt_Start ? InitCnt
						      : Done ? 5'b0
							     : DWCnt - 5'b1;

	wire	nxt_Done = nxt_DWCnt==5'h00;

	wire	nxt_Last = ~Reset & ~P62p5 & (nxt_DWCnt==5'h00) & ~Done
			 | ~Reset & ~P62p5 & (nxt_DWCnt==5'h00) &  nxt_Start
			 | ~Reset &  P62p5 &  Last;

	always @(posedge memclk) begin
		Last    <= nxt_Last;
		Done    <= nxt_Done;
		DWCnt   <= nxt_DWCnt;
	end

	// Generate Burst Length for each bank access

	wire	AnyStA2 = StA2 | OtherStA2;

	// BCnt (0,1,2) keep track of which bank access
	// is currently is the A3 branch point

	wire	nxt_BCnt0 = BCnt0 & ~(AnyStA2 & ~StB0)
			  | BCnt1 &   AnyStA2 &  StB0
			  | BCnt2 &   AnyStA2 &  StB0
			  | Reset;

	wire	nxt_BCnt1 = ~Reset & BCnt0 &  AnyStA2 & ~StB0
			  | ~Reset & BCnt1 & ~AnyStA2;

	wire	nxt_BCnt2 = ~Reset & BCnt1 &  AnyStA2 & ~StB0
			  | ~Reset & BCnt2 & ~AnyStA2;

	always @(posedge memclk) begin
		BCnt0 <= nxt_BCnt0;
		BCnt1 <= nxt_BCnt1;
		BCnt2 <= nxt_BCnt2;
	end

	// For M36:
	// Bnum[7:6] = number of bank accesses (lenght + starting
	//	    address double word offset into bank (i.e. 64 byte 
	//	    alligned block)
	// EA[5:3] = ending adddress double word offset
	// For M64:
	// Bnum[7]   = number of bank accesses (128 byte alligned block)
	// EA[6:3] = ending adddress double word offset

	// add a pipeline stage for timing

	reg	[6:3]	d1Addr;	

	always @(posedge memclk)
		d1Addr <= Addr;

	wire	[7:3]	EAup =  Length[6:3] + (I ? 4'b0
					         : (M36 ? {1'b0,d1Addr[6:4]}
						        :       d1Addr[6:3]));

	wire	[7:3]	EAdn = ~Length[6:3] +  4'b1 + (M36 ? {1'b0,d1Addr[6:4]}
						           :       d1Addr[6:3]);

	wire	[7:3]	EA   = D ? EAdn : EAup;

	wire	[7:6]	Bnum = D ? {(EAdn[7] ^ EAdn[6]),EAdn[6]} : EAup[7:6];

	wire	SingleBank = M36 ? (Bnum[7:6]==2'h0)
				 : (Bnum[7]==1'b0);

	wire	LastBank   = M36 ? ((Bnum[7:6]==2'h0) & BCnt0
			          | (Bnum[7:6]==2'h1) & BCnt1
			          | (Bnum[7:6]==2'h2) & BCnt2)
				 : ((Bnum[7]==1'b0)   & BCnt0
				  | (Bnum[7]==1'b1)   & BCnt1);

	wire	[2:0]	M36BrstLen = 
		(I ? Length[5:3]
		   : BCnt0 ? (SingleBank ? Length[5:3]
					 : (D ?  d1Addr[6:4] : ~d1Addr[6:4]))
			   : (~LastBank  ? 3'b111
					 : (D ? ~EA[5:3] : EA[5:3])));
	wire	[3:0]	M64BrstLen =
	    	(I ? Length[6:3]
		   : BCnt0 ? (SingleBank ? Length[6:3]
					 : (D ?  d1Addr[6:3] : ~d1Addr[6:3]))
			   : (D ?  ~EA[6:3] : EA[6:3]));

	assign	BrstLen = M36 ? {M36BrstLen,1'b1} : M64BrstLen;

	// Transfer count = the number of double words CAS'ed
	// used to generate A[5:3] and the Byte Mask

	wire	RCAS;
	wire	WCAS;
	wire	DCAS;

	wire	CAS = RCAS | WCAS | DCAS;

	reg	[3:0]	XCnt;

	wire	IncXCnt =  SBSel &  CAS 		// Single Bank
			| ~SBSel & (CAS | OtherCAS 
					| OtherDCAS);	// Multi  Bank

	// OtherCAS can occur in state A2, which means that Length
	// needs to be available in A2

	wire	LastDW  = (Length[6:3]==XCnt);

	wire	[3:0]	nxt_XCnt =  IncXCnt ? (LastDW ? 4'h0 : XCnt + 4'h1)
					    :  XCnt;

	always @(posedge memclk)
	if (Reset)	XCnt <= 4'b0000;
	else		XCnt <= nxt_XCnt;

	// Generate signal indicating that a non-Activate command
	// will issue in the next clock which will prevent other banks
	// from issuing an activate command at the same time

	wire	NextCMD = nxt_StRF  | nxt_StRD  | nxt_StRB  | nxt_StR9
			| nxt_StR7  | nxt_StR5  | nxt_StR3  | nxt_StR1
			| nxt_StRWF | nxt_StRWD | nxt_StRWB | nxt_StRW9
			| nxt_StRW7 | nxt_StRW5 | nxt_StRW3 | nxt_StRW1
			| nxt_StWF  | nxt_StWD  | nxt_StWB  | nxt_StW9 
			| nxt_StW7  | nxt_StW5  | nxt_StW3  | nxt_StW1 
			| nxt_StWWF | nxt_StWWD | nxt_StWWB | nxt_StWW9 
			| nxt_StWW7 | nxt_StWW5 | nxt_StWW3 | nxt_StWW1 
			| (nxt_StP1 & ~nxt_StAP0 & ~APrechrg);

	// Generate preliminary DRAM controls

	assign	WCAS = StWF  | StWD  | StWB  | StW9
		     | StW7  | StW5  | StW3  | StW1
		     | StWWF | StWWD | StWWB | StWW9
		     | StWW7 | StWW5 | StWW3 | StWW1;

	assign	RCAS = StRF  | StRD  | StRB  | StR9
		     | StR7  | StR5  | StR3  | StR1
		     | StRWF | StRWD | StRWB | StRW9
		     | StRW7 | StRW5 | StRW3 | StRW1;

	assign	DCAS = StWWF | StWWD | StWWB | StWW9
		     | StWW7 | StWW5 | StWW3 | StWW1
		     | StRWF | StRWD | StRWB | StRW9
		     | StRW7 | StRW5 | StRW3 | StRW1;

	// Changed design to always issue auto precharge read commands (READA)

	wire	PRAS = ~APrechrg & StP1 & ~StAP0;	// Assert PRAS to 
							// issue Manual-Pre

	wire	APRCAS = (M36 ? (StR1  & (StAP0 | APrechrg))
			      : (StRW1 & (StAP0 | APrechrg)));

	wire	APWCAS = (M36 ? StW1 : StWW1);

	wire	APCAS = APRCAS | APWCAS;

	assign	RAS = StA1 | (TRCD4 ? MB1stRAS : (StAi & MB1stAct));

	wire	nxt_bugcheck1 = ~StAi & MB1stAct;
	reg	bugcheck1;
	always @(posedge memclk)
		bugcheck1 <= nxt_bugcheck1 & ~Reset;
	// synopsys translate_off
	always @(bugcheck1) 
	if (bugcheck1) begin
	$display("ERROR: %t: %M: (~StAi & MB1stAct)=1", $time);
	repeat (20) @(posedge memclk);
	$finish;
	end
	// synopsys translate_on

	wire	LastWCAS = (M36 ? StW1 : StWW1);

	wire	LastCAS = (M36 ? StW1 : StWW1)
			| (M36 ? StR1 : StRW1);

	// Generate Read Data Path control signals

	// CCR - Cycle Complete ready for a Read
	// Indicates when the next Read cycle can start 
	// Extended when manual precharge occurs (StAP0)

	reg	CCR;

	wire	nxt_CCR =  CCR & ~LastStA3
			| ~CCR & (StWR1 | (StAP0 ? (M36 ? StR1 : StRW1)
						 :  StP1))
			|  Reset;

	always @(posedge memclk)
		CCR <= nxt_CCR;

	// Initiates read Data Path
	wire	DBusInEn = StartWrCmd | StM1 
			 | StWE  | StWC  | StWA  | StW8
			 | StW6  | StW4  | StW2  | StW0 & ~M36
			 | StWWE | StWWC | StWWA | StWW8
			 | StWW6 | StWW4 | StWW2;

	reg	ReadEn;

	wire	M36ReadEn  = ~Reset & ~ReadEn & (StRF | StRD | StRB |  StR9
					      |  StR7 | StR5 | StR3 |  StR1)
			   | ~Reset &  ReadEn & (StRD | StRB | StR9 |  StR7
					      |  StR5 | StR3 | StR1 |  P62p5);

	wire	M64ReadEn  = ~Reset & (StRF  | StRD  | StRB  | StR9
				    |  StR7  | StR5  | StR3  | StR1
				    |  StRWF | StRWD | StRWB | StRW9
				    |  StRW7 | StRW5 | StRW3 | StRW1);

	always @(posedge memclk) 
		ReadEn <= M36 ? M36ReadEn : M64ReadEn;

endmodule