// ri.v v1 Doug Solomon
// ddR memory Interface;

module ri (
	sysclk, 		
	memclk, 
	pll_bypass,
	reset_l,
	cbus_read_enable, 
	cbus_write_enable, 
	cbus_command,
	cbus_din, 
	cbus_dout, 
	cbus_read_request, 
	cbus_read_grant,
	dbus_din, 
	dbus_dout, 
	ebus_din,
	ebus_dout,
	dma_ready, 
	start_read, 
	mi_dma_start,
	mi_dma_last,
	sp_dma_start,
	sp_dma_last,
	span_dma_start,
	span_dma_last,
	pi_dma_start,
	pi_dma_last,
	si_dma_start,
	si_dma_last,
	ai_dma_start,
	ai_dma_last,
	vi_dma_start,
	vi_dma_last,
	ui_dma_start,
	mi_dbus_read_enable, 
	mi_dbus_write_enable,
	sp_dbus_read_enable, 
	sp_dbus_write_enable,
	span_dbus_read_enable, 
	span_dbus_write_enable,
	pi_dbus_write_enable,
	si_dbus_write_enable,
	ui_dbus_read_enable, 
	ui_dbus_write_enable,
	mcke, 
	maddr, 
	mbank,
	mdin, 
	mdin_ena, 
	mdout, 
	mdout_ena,
	strobe_rev,
	mras, 
	mcas, 
	mwe, 
	mdqm
	);


	// global signals;
	// sysclk and memclk are rising edge aligned;
	// reset_l is synchronous to memclk, active 64 for memclk;

	input sysclk;		// system clock;
	input memclk;		// memory clock;
	input pll_bypass;
	input reset_l;		// system reset;

	input cbus_read_enable;	// cbus interface;
	input cbus_write_enable;
	input [2:0] cbus_command;
	input [31:0] cbus_din;
	output [31:0] cbus_dout;

	input [63:0] dbus_din;		// dbus, ebus;
	output [63:0] dbus_dout;	// dbus, ebus;
	input [7:0] ebus_din;
	output [7:0] ebus_dout;

	output	cbus_read_request;
	input	cbus_read_grant;

	output dma_ready;
	output start_read;
	output sp_dma_start;	// seperate start and last per device
	output span_dma_start;
	output mi_dma_start;
	output vi_dma_start;
	output ui_dma_start;
	output si_dma_start;
	output pi_dma_start;
	output ai_dma_start;
	output sp_dma_last;
	output span_dma_last;
	output mi_dma_last;
	output vi_dma_last;
	output si_dma_last;
	output pi_dma_last;
	output ai_dma_last;

	output mi_dbus_read_enable;	// device controls
	output mi_dbus_write_enable;
	output sp_dbus_read_enable;
	output sp_dbus_write_enable;
	output span_dbus_read_enable;
	output span_dbus_write_enable;
	output pi_dbus_write_enable;
	output si_dbus_write_enable;
	output ui_dbus_read_enable;	
	output ui_dbus_write_enable;

	// memory interface;
	// the registered io cells are in the pad layer;

	output		mcke;		// clock enables;
	output	[12:0]	maddr;		// row/col address;
	output	[1:0]	mbank;		// bank address;
	input	[63:0]	mdin;		// input data;
	output		mdin_ena;	// input register enables;
	output	[63:0]	mdout;		// output data;
	output		mdout_ena;	// output register enables;
	output	[4:0]	strobe_rev;	// reverse strobe polarity;
	output		mras;		// command;
	output		mcas;		// command;
	output		mwe;		// command;
	output	[7:0]	mdqm;		// byte enables;

	wire		Bk0CASMatch;
	wire		Bk1CASMatch;
	wire		Bk2CASMatch;
	wire		Bk3CASMatch;

	wire	[27:0]	Bk0Addr;
	wire	[3:0]	Bk0MAddr;
	wire		Bk0I;
	wire		Bk0M;
	wire		Bk0D;
	wire	[3:0]	Bk0Device;
	wire		Bk0Read;
	wire	[6:0]	Bk0Length;
	wire	[27:0]	Bk1Addr;
	wire	[3:0]	Bk1MAddr;
	wire		Bk1I;
	wire		Bk1M;
	wire		Bk1D;
	wire	[3:0]	Bk1Device;
	wire		Bk1Read;
	wire	[6:0]	Bk1Length;
	wire		Pr0I;
	wire		Pr0D;
	wire	[3:0]	Pr0Device;
	wire	[6:3]	Pr0Addr;
	wire	[6:0]	Pr0Length;

	wire	[27:0]	Bk2Addr;
	wire	[3:0]	Bk2MAddr;
	wire		Bk2I;
	wire		Bk2M;
	wire		Bk2D;
	wire	[3:0]	Bk2Device;
	wire		Bk2Read;
	wire	[6:0]	Bk2Length;
	wire	[27:0]	Bk3Addr;
	wire	[3:0]	Bk3MAddr;
	wire		Bk3I;
	wire		Bk3M;
	wire		Bk3D;
	wire	[3:0]	Bk3Device;
	wire		Bk3Read;
	wire	[6:0]	Bk3Length;
	wire		Pr1I;
	wire		Pr1D;
	wire	[3:0]	Pr1Device;
	wire	[6:3]	Pr1Addr;
	wire	[6:0]	Pr1Length;

	wire	[7:0]	Pr0StB0;
	wire		Pr0StB1;
	wire		Pr0nxt_StB1;
	wire		Pr0StB2;
	wire		Pr0StB5;
	wire		Bk0MBAct;
	wire		Bk1MBAct;
	wire		Bk0MB1stAct;
	wire		Bk1MB1stAct;

	wire	[7:0]	Pr1StB0;
	wire		Pr1StB1;
	wire		Pr1nxt_StB1;
	wire		Pr1StB2;
	wire		Pr1StB5;
	wire		Bk2MBAct;
	wire		Bk3MBAct;
	wire		Bk2MB1stAct;
	wire		Bk3MB1stAct;

	wire		Bk0CAS;
	wire		Bk1CAS;
	wire		Bk2CAS;
	wire		Bk3CAS;

	wire		Bk0StAi;
	wire		Bk0StA2;
	wire		Bk0StA3;
	wire		Bk0LastStA3;
	wire	[3:0]	Bk0XCnt;
	wire		Bk0NextCMD;
	wire		Bk0WCAS;
	wire		Bk0RCAS;
	wire		Bk0PRAS;
	wire		Bk0RAS;
	wire		Bk0StM0;
	wire		Bk0CCR;
	wire		Bk0ReadEn;
	wire		Bk0nxt_Start;
	wire		Bk0pre_start;
	wire		Bk0nxt_Last;
	wire		Bk0nxt_Done;
	wire		Bk0Pend;
	wire		Bk0BlockRdy;
	wire		Bk0LastCAS;
	wire		Bk0nxt_StRS0;
	wire		Bk0WriteDone;
	wire		Bk0ReadDone;
	wire		Bk0DBusInEn;
	wire		Bk0MB1stRAS;
	wire		Bk0LastWCAS;
	wire		Bk0StWS1;
	assign		Bk0CAS = Bk0WCAS | Bk0RCAS;

	wire		Bk1StAi;
	wire		Bk1StA2;
	wire		Bk1StA3;
	wire		Bk1LastStA3;
	wire	[3:0]	Bk1XCnt;
	wire		Bk1NextCMD;
	wire		Bk1WCAS;
	wire		Bk1RCAS;
	wire		Bk1PRAS;
	wire		Bk1RAS;
	wire		Bk1StM0;
	wire		Bk1CCR;
	wire		Bk1ReadEn;
	wire		Bk1nxt_Start;
	wire		Bk1pre_start;
	wire		Bk1nxt_Last;
	wire		Bk1nxt_Done;
	wire		Bk1Pend;
	wire		Bk1BlockRdy;
	wire		Bk1LastCAS;
	wire		Bk1nxt_StRS0;
	wire		Bk1WriteDone;
	wire		Bk1ReadDone;
	wire		Bk1DBusInEn;
	wire		Bk1MB1stRAS;
	wire		Bk1LastWCAS;
	wire		Bk1StWS1;
	assign		Bk1CAS = Bk1WCAS | Bk1RCAS;

	wire		Bk2StAi;
	wire		Bk2StA2;
	wire		Bk2StA3;
	wire		Bk2LastStA3;
	wire	[3:0]	Bk2XCnt;
	wire		Bk2NextCMD;
	wire		Bk2WCAS;
	wire		Bk2RCAS;
	wire		Bk2PRAS;
	wire		Bk2RAS;
	wire		Bk2StM0;
	wire		Bk2CCR;
	wire		Bk2ReadEn;
	wire		Bk2nxt_Start;
	wire		Bk2pre_start;
	wire		Bk2nxt_Last;
	wire		Bk2nxt_Done;
	wire		Bk2Pend;
	wire		Bk2BlockRdy;
	wire		Bk2LastCAS;
	wire		Bk2nxt_StRS0;
	wire		Bk2WriteDone;
	wire		Bk2ReadDone;
	wire		Bk2DBusInEn;
	wire		Bk2MB1stRAS;
	wire		Bk2LastWCAS;
	wire		Bk2StWS1;
	assign		Bk2CAS = Bk2WCAS | Bk2RCAS;

	wire		Bk3StAi;
	wire		Bk3StA2;
	wire		Bk3StA3;
	wire		Bk3LastStA3;
	wire	[3:0]	Bk3XCnt;
	wire		Bk3NextCMD;
	wire		Bk3WCAS;
	wire		Bk3RCAS;
	wire		Bk3PRAS;
	wire		Bk3RAS;
	wire		Bk3StM0;
	wire		Bk3CCR;
	wire		Bk3ReadEn;
	wire		Bk3nxt_Start;
	wire		Bk3pre_start;
	wire		Bk3nxt_Last;
	wire		Bk3nxt_Done;
	wire		Bk3Pend;
	wire		Bk3BlockRdy;
	wire		Bk3LastCAS;
	wire		Bk3nxt_StRS0;
	wire		Bk3WriteDone;
	wire		Bk3ReadDone;
	wire		Bk3DBusInEn;
	wire		Bk3MB1stRAS;
	wire		Bk3LastWCAS;
	wire		Bk3StWS1;
	assign		Bk3CAS = Bk3WCAS | Bk3RCAS;

	wire	[7:0]	MaskOut;

	wire	[12:0]	RA;
	wire	[1:0]	BA;
	wire		CS;
	wire		RAS;
	wire		CAS;
	wire		WE;

	reg	[63:0]	CBusMask;
	wire		AllCCW;
	wire		AllCCR;
	wire		Init_Ref;
	wire		Init_Pre;
	wire		Init_Mod;
	reg		StRi;
	reg		StR0;
	reg		StR1;
	reg		StR2;
	reg	[31:0]	CDataIn;


	//	cbus commands

	`define		CMD_IDLE	3'h0
	`define		CMD_DMA		3'h1
	`define		CMD_WRITE	3'h2
	`define		CMD_READ	3'h3
	`define		CMD_RESPONSE	3'h4
	`define		CMD_REFRESH	3'h5


	//	cbus device identifiers

	`define		ID_SP		4'h0
	`define		ID_CMD		4'h1
	`define		ID_SPAN		4'h2
	`define		ID_MI		4'h3
	`define		ID_VI		4'h4
	`define		ID_SI		4'h5
	`define		ID_PI		4'h6
	`define		ID_RI		4'h7
	`define		ID_AI		4'h8
	`define		ID_MEM		4'h9
	`define		ID_UI		4'hA

	//	ri register space

	`define		BUS_ADDRESS_RI	12'h047		// Address[31:20]

	`define		MODE_SET	16'h0_002	// Address[19:4]
	`define		TREF_SET	16'h0_003
	`define		TMPR_SET	16'h0_004
	`define		XMEM_SET	16'h0_005
	`define		SREV_SET	16'h0_006
	`define		AUTO_SET	16'h0_008

	// Buffer reset_l with flip-flop

	reg	Reset;
	always	 @(posedge sysclk)
		Reset <= ~reset_l;

	wire	TRCD4;
	wire	TRASp2;
	wire	TRP4;

	reg	delsysclk;
	reg	P62p5;

	always	 @(negedge memclk)
		delsysclk <= ~sysclk;

	wire	pll_bypass;

	always	 @(posedge memclk)
		P62p5 <= pll_bypass ? ~sysclk : delsysclk;

	//  Next Address Enable and Next Length Enable State Machine

	reg	NAE;
	reg	NLE;

	wire	nxt_NAE = ~NAE & P62p5 & (cbus_command==`CMD_DMA) & ~Reset;

	always @(posedge memclk) begin
		NAE <= nxt_NAE;
		NLE <=     NAE;
	end

	// add pipe-line reg to cbus_din for timing

	reg	[31:0]	CBusDataIn;

	always   @(posedge memclk)
		CBusDataIn <= cbus_din;

	// Generate Bank Match directly from cbus

	wire	Bk0Match = (CBusDataIn[31:24]==8'h00) 
			 ? (~CBusDataIn[20] & ~CBusDataIn[6]) & NAE
			 : (~CBusDataIn[21] & ~CBusDataIn[7]) & NAE;

	wire	Bk1Match = (CBusDataIn[31:24]==8'h00) 
			 ? (~CBusDataIn[20] &  CBusDataIn[6]) & NAE
			 : (~CBusDataIn[21] &  CBusDataIn[7]) & NAE;

	wire	Bk2Match = (CBusDataIn[31:24]==8'h00) 
			 ? ( CBusDataIn[20] & ~CBusDataIn[6]) & NAE
			 : ( CBusDataIn[21] & ~CBusDataIn[7]) & NAE;

	wire	Bk3Match = (CBusDataIn[31:24]==8'h00) 
			 ? ( CBusDataIn[20] &  CBusDataIn[6]) & NAE
			 : ( CBusDataIn[21] &  CBusDataIn[7]) & NAE;

	//	Addr Path Logic

	// Capture unalligned address from cbus

	reg	[31:0]	NextUAddr;	

	wire	[31:0]	nxt_NextUAddr = NAE ? cbus_din : NextUAddr;

	always @(posedge memclk)
			NextUAddr <= nxt_NextUAddr;

	// Allign address if M36

	wire		nxt_NextM36 = (nxt_NextUAddr[31:24]==8'h00);

	reg	NextM36;
	always @(posedge memclk)
			NextM36 <= nxt_NextM36;

	wire	[24:0]	M36Addr = {NextUAddr[23:2],1'b0,NextUAddr[1:0]};

	wire	[27:0]	M64Addr =  NextUAddr[31] ? NextUAddr[27:0]
						 : {3'b000,
						    ~NextUAddr[24],
						     NextUAddr[23:0]};

	wire	[27:0]	NextAddr = NextM36 ? {3'b0,M36Addr}
					   : M64Addr;

	wire	[1:0]	BankAddr = {NextAddr[21],NextAddr[7]};

	// Capture Length etc from cbus


	reg		NextI;		// Interleaved
	reg		NextM;		// Masked
	reg		NextD;		// Down (for SPAN/M36 only)
	reg	[3:0]	NextDevice;
	reg		NextRead;
	reg	[6:0]	NextLength;

	wire		nxt_NextI      = NLE ? cbus_din[23]    : NextI;	
	wire		nxt_NextM      = NLE ? cbus_din[22]    : NextM;
	wire		nxt_NextD      = NLE ? cbus_din[21]    : NextD;
	wire	[3:0]	nxt_NextDevice = NLE ? cbus_din[19:16] : NextDevice;
	wire		nxt_NextRead   = NLE ? cbus_din[7]     : NextRead;
	wire	[6:0]	nxt_NextLength = NLE ? cbus_din[6:0]   : NextLength;

	always @(posedge memclk) begin
			NextI       <= nxt_NextI;
			NextM       <= nxt_NextM;
			NextD       <= nxt_NextD;
			NextDevice  <= nxt_NextDevice;
			NextRead    <= nxt_NextRead;
			NextLength  <= nxt_NextLength;
	end
	
	wire	AnyNextCMD = Bk0NextCMD | Bk1NextCMD
			   | Bk2NextCMD | Bk3NextCMD;

	assign	AllCCR = Bk0CCR & Bk1CCR & Bk2CCR & Bk3CCR;

	wire	pre_start = Bk0pre_start | Bk1pre_start 
			  | Bk2pre_start | Bk3pre_start;

	wire	dma_start = Bk0nxt_Start | Bk1nxt_Start 
			  | Bk2nxt_Start | Bk3nxt_Start;

	wire	dma_last  = Bk0nxt_Last  | Bk1nxt_Last  
			  | Bk2nxt_Last  | Bk3nxt_Last;

	wire	AllDone   = Bk0nxt_Done  & Bk1nxt_Done  
			  & Bk2nxt_Done  & Bk3nxt_Done;

	wire		start_write  = Bk0nxt_Start & ~Bk0Read
				     | Bk1nxt_Start & ~Bk1Read
				     | Bk2nxt_Start & ~Bk2Read
				     | Bk3nxt_Start & ~Bk3Read;

	wire	[3:0]	start_device = {4{Bk0nxt_Start}} & Bk0Device
				     | {4{Bk1nxt_Start}} & Bk1Device
				     | {4{Bk2nxt_Start}} & Bk2Device
				     | {4{Bk3nxt_Start}} & Bk3Device;

	wire		nxt_start_read   = Bk0nxt_StRS0
				         | Bk1nxt_StRS0
				         | Bk2nxt_StRS0
				         | Bk3nxt_StRS0;

	wire	nxt_sp_dma_start   = dma_start & (start_device==`ID_SP);
	wire	nxt_cmd_dma_start  = dma_start & (start_device==`ID_CMD);
	wire	nxt_span_dma_start = dma_start & (start_device==`ID_SPAN);
	wire	nxt_mi_dma_start   = dma_start & (start_device==`ID_MI);
	wire	nxt_vi_dma_start   = dma_start & (start_device==`ID_VI);
	wire	nxt_ui_dma_start   = dma_start & (start_device==`ID_UI);
	wire	nxt_si_dma_start   = dma_start & (start_device==`ID_SI);
	wire	nxt_pi_dma_start   = dma_start & (start_device==`ID_PI);
	wire	nxt_ai_dma_start   = dma_start & (start_device==`ID_AI);

	reg	sp_dma_start;
	reg	span_dma_start;
	reg	mi_dma_start;
	reg	vi_dma_start;
	reg	ui_dma_start;
	reg	si_dma_start;
	reg	pi_dma_start;
	reg	ai_dma_start;
	reg	start_read;
	
	always @(posedge sysclk) begin
		sp_dma_start   <= ~Reset & nxt_sp_dma_start 
				| ~Reset & nxt_cmd_dma_start;
		span_dma_start <= ~Reset & nxt_span_dma_start;
		mi_dma_start   <= ~Reset & nxt_mi_dma_start;
		vi_dma_start   <= ~Reset & nxt_vi_dma_start;
		vi_dma_start   <= ~Reset & nxt_vi_dma_start;
		ui_dma_start   <= ~Reset & nxt_ui_dma_start;
		si_dma_start   <= ~Reset & nxt_si_dma_start;
		pi_dma_start   <= ~Reset & nxt_pi_dma_start;
		ai_dma_start   <= ~Reset & nxt_ai_dma_start;
		start_read     <= ~Reset & nxt_start_read;
	end

	reg	[3:0]	hld_last_device;
	wire	[3:0]	last_device = dma_start ? start_device
						: hld_last_device;
	always @(posedge memclk)
	if (Reset)	hld_last_device <= 4'h0;
	else		hld_last_device <= last_device;

	wire	nxt_sp_dma_last   = dma_last & (last_device==`ID_SP);
	wire	nxt_cmd_dma_last  = dma_last & (last_device==`ID_CMD);
	wire	nxt_span_dma_last = dma_last & (last_device==`ID_SPAN);
	wire	nxt_mi_dma_last   = dma_last & (last_device==`ID_MI);
	wire	nxt_vi_dma_last   = dma_last & (last_device==`ID_VI);
	wire	nxt_si_dma_last   = dma_last & (last_device==`ID_SI);
	wire	nxt_pi_dma_last   = dma_last & (last_device==`ID_PI);
	wire	nxt_ai_dma_last   = dma_last & (last_device==`ID_AI);

	reg	sp_dma_last;
	reg	span_dma_last;
	reg	mi_dma_last;
	reg	vi_dma_last;
	reg	si_dma_last;
	reg	pi_dma_last;
	reg	ai_dma_last;

	always @(posedge sysclk) begin
		sp_dma_last    <= ~Reset & nxt_sp_dma_last 
				| ~Reset & nxt_cmd_dma_last;
		span_dma_last  <= ~Reset & nxt_span_dma_last ;
		mi_dma_last    <= ~Reset & nxt_mi_dma_last ;
		vi_dma_last    <= ~Reset & nxt_vi_dma_last ;
		si_dma_last    <= ~Reset & nxt_si_dma_last ;
		pi_dma_last    <= ~Reset & nxt_pi_dma_last ;
		ai_dma_last    <= ~Reset & nxt_ai_dma_last ;
	end

	reg	APrechrg;
	reg	XMem;
	reg	DBusOE;
	wire	TCL2;
	wire	TCL3;
	wire	TCL4;
	wire	TCL6;
	wire	M36WD0;
	reg	[2:0]	Trdel;
	reg	[2:0]	Twdel;

	wire	TRD2 = (Trdel==3'b010);
	wire	TRD3 = (Trdel==3'b011);
	wire	TRD4 = (Trdel==3'b100);
	wire	TRD5 = (Trdel==3'b101);

	reg	StDR0;
	reg	StDR1;
	reg	StDR2;
	reg	StDR3;

	wire	nxt_StDR0 = ~Reset & StDR1 & (NAE | NLE)
			  | ~Reset & StDR0 & ~pre_start;

	wire	nxt_StDR1 = StDR0 &  pre_start & ~start_write
			  | StDR1 & ~(NAE | NLE)
			  | StDR3
			  | Reset;

	wire	nxt_StDR2 = ~Reset & StDR0 &  pre_start &  start_write;

	wire	nxt_StDR3 = ~Reset & StDR2;

	always @(posedge sysclk) begin
		StDR0   <= nxt_StDR0;
		StDR1   <= nxt_StDR1;
		StDR2   <= nxt_StDR2;
		StDR3   <= nxt_StDR3;
	end

	wire	dma_ready = StDR1;

CASFifo		CASFifo (
			.memclk		(memclk),
			.Reset		(Reset),
			.BankAddr	(BankAddr),
			.NLE		(NLE),
			.Pr0StB0	(Pr0StB0[4]),
			.Pr1StB0	(Pr1StB0[4]),
			.Pr0StB5	(Pr0StB5),
			.Pr1StB5	(Pr1StB5),
			.Bk0LastStA3	(Bk0LastStA3),
			.Bk1LastStA3	(Bk1LastStA3),
			.Bk2LastStA3	(Bk2LastStA3),
			.Bk3LastStA3	(Bk3LastStA3),

			.Bk0CASMatch	(Bk0CASMatch),
			.Bk1CASMatch	(Bk1CASMatch),
			.Bk2CASMatch	(Bk2CASMatch),
			.Bk3CASMatch	(Bk3CASMatch)
			);

BankAddr	BankAddr01 (
			.memclk		(memclk),
			.Reset		(Reset),
			.NextAddr	(NextAddr),
			.NextI		(NextI),
			.NextM		(NextM),
			.NextD		(NextD),
			.NextDevice	(NextDevice),
			.NextRead	(NextRead),
			.NextLength	(NextLength),
			.NextM36	(NextM36),
			.Pr0StB0	(Pr0StB0[3:0]),
			.Bk0RAS		(Bk0RAS),
			.Bk1RAS		(Bk1RAS),

			.Bk0Addr	(Bk0Addr),
			.Bk0MAddr	(Bk0MAddr),
			.Bk0I		(Bk0I),
			.Bk0M		(Bk0M),
			.Bk0D		(Bk0D),
			.Bk0Device	(Bk0Device),
			.Bk0Read	(Bk0Read),
			.Bk0Length	(Bk0Length),
			.Bk0M36		(Bk0M36),
			.Bk1Addr	(Bk1Addr),
			.Bk1MAddr	(Bk1MAddr),
			.Bk1I		(Bk1I),
			.Bk1M		(Bk1M),
			.Bk1D		(Bk1D),
			.Bk1Device	(Bk1Device),
			.Bk1Read	(Bk1Read),
			.Bk1Length	(Bk1Length),
			.Bk1M36		(Bk1M36),
			.Pr0I		(Pr0I),
			.Pr0D		(Pr0D),
			.Pr0Device	(Pr0Device),
			.Pr0Addr	(Pr0Addr),
			.Pr0Length	(Pr0Length),
			.Pr0M36		(Pr0M36)
			);

BankAddr	BankAddr23 (
			.memclk		(memclk),
			.Reset		(Reset),
			.NextAddr	(NextAddr),
			.NextI		(NextI),
			.NextM		(NextM),
			.NextD		(NextD),
			.NextDevice	(NextDevice),
			.NextRead	(NextRead),
			.NextLength	(NextLength),
			.NextM36	(NextM36),
			.Pr0StB0	(Pr1StB0[3:0]),
			.Bk0RAS		(Bk2RAS),
			.Bk1RAS		(Bk3RAS),

			.Bk0Addr	(Bk2Addr),
			.Bk0MAddr	(Bk2MAddr),
			.Bk0I		(Bk2I),
			.Bk0M		(Bk2M),
			.Bk0D		(Bk2D),
			.Bk0Device	(Bk2Device),
			.Bk0Read	(Bk2Read),
			.Bk0Length	(Bk2Length),
			.Bk0M36		(Bk2M36),
			.Bk1Addr	(Bk3Addr),
			.Bk1MAddr	(Bk3MAddr),
			.Bk1I		(Bk3I),
			.Bk1M		(Bk3M),
			.Bk1D		(Bk3D),
			.Bk1Device	(Bk3Device),
			.Bk1Read	(Bk3Read),
			.Bk1Length	(Bk3Length),
			.Bk1M36		(Bk3M36),
			.Pr0I		(Pr1I),
			.Pr0D		(Pr1D),
			.Pr0Device	(Pr1Device),
			.Pr0Addr	(Pr1Addr),
			.Pr0Length	(Pr1Length),
			.Pr0M36		(Pr1M36)
			);

MBCtrl		MBCtrl0 (
			.memclk		(memclk),
			.Reset		(Reset),
			.Length		(Pr0Length),
			.Addr		(Pr0Addr[6:3]),
			.I		(Pr0I),
			.D		(Pr0D),
			.M36		(Pr0M36),
			.Bk0StA2	(Bk0StA2),
			.Bk1StA2	(Bk1StA2),
			.Bk0LastStA3	(Bk0LastStA3),
			.Bk1LastStA3	(Bk1LastStA3),
			.Bk0LastCAS	(Bk0LastCAS),
			.Bk1LastCAS	(Bk1LastCAS),

			.StB0		(Pr0StB0),
			.StB1		(Pr0StB1),
			.nxt_StB1	(Pr0nxt_StB1),
			.StB2		(Pr0StB2),
			.StB5		(Pr0StB5),
			.Bk0MBAct	(Bk0MBAct),
			.Bk1MBAct	(Bk1MBAct),
			.Bk0MB1stAct	(Bk0MB1stAct),
			.Bk1MB1stAct	(Bk1MB1stAct),
			.SBSel		(Pr0SBSel)
			);

MBCtrl		MBCtrl1 (
			.memclk		(memclk),
			.Reset		(Reset),
			.Length		(Pr1Length),
			.Addr		(Pr1Addr[6:3]),
			.I		(Pr1I),
			.D		(Pr1D),
			.M36		(Pr1M36),
			.Bk0StA2	(Bk2StA2),
			.Bk1StA2	(Bk3StA2),
			.Bk0LastStA3	(Bk2LastStA3),
			.Bk1LastStA3	(Bk3LastStA3),
			.Bk0LastCAS	(Bk2LastCAS),
			.Bk1LastCAS	(Bk3LastCAS),

			.StB0		(Pr1StB0),
			.StB1		(Pr1StB1),
			.nxt_StB1	(Pr1nxt_StB1),
			.StB2		(Pr1StB2),
			.StB5		(Pr1StB5),
			.Bk0MBAct	(Bk2MBAct),
			.Bk1MBAct	(Bk3MBAct),
			.Bk0MB1stAct	(Bk2MB1stAct),
			.Bk1MB1stAct	(Bk3MB1stAct),
			.SBSel		(Pr1SBSel)
			);

BankCtrl	BankCtrl0 (
			.memclk		(memclk),
			.Reset		(Reset),
			.AnyNextCMD	(AnyNextCMD),
			.OtherCAS	(Bk1CAS),
			.OtherDCAS	(Bk1DCAS),
			.Match		(Bk0Match),
			.CASMatch	(Bk0CASMatch),
			.NAE		(NAE),
			.AllCCR		(AllCCR),
			.AllCCW		(AllCCW),
			.AllDone	(AllDone),
			.P62p5		(P62p5),
			.OtherStAi	(Bk1StAi),
			.OtherStA2	(Bk1StA2),
			.OtherStA3	(Bk1StA3),
			.OtherLastStA3	(Bk1LastStA3),
			.StB0		(Pr0StB0[4]),
			.OtherStB0	(Pr1StB0[4]),
			.StB1		(Pr0StB1),
			.nxt_StB1	(Pr0nxt_StB1),
			.MB1stAct	(Bk0MB1stAct),
			.MBAct		(Bk0MBAct),
			.Device		(Bk0Device),
			.Read		(Bk0Read),
			.Length		(Bk0Length[6:3]),
			.Addr		(Bk0Addr[6:3]),
			.I		(Bk0I),
			.D		(Bk0D),
			.M		(Bk0M),
			.StRi		(StRi),
			.SBSel		(Pr0SBSel),
			.TCL2		(TCL2),
			.TCL3		(TCL3),
			.TCL4		(TCL4),
			.TRCD4		(TRCD4),
			.TRASp2		(TRASp2),
			.TRP4		(TRP4),
			.Trdel		(Trdel),
			.Twdel		(Twdel),
			.M36		(Bk0M36),
			.OtherWriteDone	(Bk1WriteDone),
			.OtherReadDone	(Bk1ReadDone),
			.MB1stRAS	(Bk1MB1stRAS),
			.APrechrg	(APrechrg),

			.StAi		(Bk0StAi),
			.StA2		(Bk0StA2),
			.StA3		(Bk0StA3),
			.LastStA3	(Bk0LastStA3),
			.XCnt		(Bk0XCnt),
			.NextCMD	(Bk0NextCMD),
			.WCAS		(Bk0WCAS),
			.RCAS		(Bk0RCAS),
			.DCAS		(Bk0DCAS),
			.PRAS		(Bk0PRAS),
			.APCAS		(Bk0APCAS),
			.RAS		(Bk0RAS),
			.StM0		(Bk0StM0),
			.CCR		(Bk0CCR),
			.ReadEn		(Bk0ReadEn),
			.nxt_Start	(Bk0nxt_Start),
			.pre_start	(Bk0pre_start),
			.nxt_Last	(Bk0nxt_Last),
			.nxt_Done	(Bk0nxt_Done),
			.Pend		(Bk0Pend),
			.BlockRdy	(Bk0BlockRdy),
			.LastCAS	(Bk0LastCAS),
			.nxt_StRS0	(Bk0nxt_StRS0),
			.WriteDone	(Bk0WriteDone),
			.ReadDone	(Bk0ReadDone),
			.DBusInEn	(Bk0DBusInEn),
			.MB1stRASout	(Bk0MB1stRAS),
			.LastWCAS	(Bk0LastWCAS),
			.StWS1		(Bk0StWS1)
			);

BankCtrl	BankCtrl1 (
			.memclk		(memclk),
			.Reset		(Reset),
			.AnyNextCMD	(AnyNextCMD),
			.OtherCAS	(Bk0CAS),
			.OtherDCAS	(Bk0DCAS),
			.Match		(Bk1Match),
			.CASMatch	(Bk1CASMatch),
			.NAE		(NAE),
			.AllCCR		(AllCCR),
			.AllCCW		(AllCCW),
			.AllDone	(AllDone),
			.P62p5		(P62p5),
			.OtherStAi	(Bk0StAi),
			.OtherStA2	(Bk0StA2),
			.OtherStA3	(Bk0StA3),
			.OtherLastStA3	(Bk0LastStA3),
			.StB0		(Pr0StB0[5]),
			.OtherStB0	(Pr1StB0[5]),
			.StB1		(Pr0StB1),
			.nxt_StB1	(Pr0nxt_StB1),
			.MB1stAct	(Bk1MB1stAct),
			.MBAct		(Bk1MBAct),
			.Device		(Bk1Device),
			.Read		(Bk1Read),
			.Length		(Bk1Length[6:3]),
			.Addr		(Bk1Addr[6:3]),
			.I		(Bk1I),
			.D		(Bk1D),
			.M		(Bk1M),
			.StRi		(StRi),
			.SBSel		(Pr0SBSel),
			.TCL2		(TCL2),
			.TCL3		(TCL3),
			.TCL4		(TCL4),
			.TRCD4		(TRCD4),
			.TRASp2		(TRASp2),
			.TRP4		(TRP4),
			.Trdel		(Trdel),
			.Twdel		(Twdel),
			.M36		(Bk1M36),
			.OtherWriteDone	(Bk0WriteDone),
			.OtherReadDone	(Bk0ReadDone),
			.MB1stRAS	(Bk0MB1stRAS),
			.APrechrg	(APrechrg),

			.StAi		(Bk1StAi),
			.StA2		(Bk1StA2),
			.StA3		(Bk1StA3),
			.LastStA3	(Bk1LastStA3),
			.XCnt		(Bk1XCnt),
			.NextCMD	(Bk1NextCMD),
			.WCAS		(Bk1WCAS),
			.RCAS		(Bk1RCAS),
			.DCAS		(Bk1DCAS),
			.PRAS		(Bk1PRAS),
			.APCAS		(Bk1APCAS),
			.RAS		(Bk1RAS),
			.StM0		(Bk1StM0),
			.CCR		(Bk1CCR),
			.ReadEn		(Bk1ReadEn),
			.nxt_Start	(Bk1nxt_Start),
			.pre_start	(Bk1pre_start),
			.nxt_Last	(Bk1nxt_Last),
			.nxt_Done	(Bk1nxt_Done),
			.Pend		(Bk1Pend),
			.BlockRdy	(Bk1BlockRdy),
			.LastCAS	(Bk1LastCAS),
			.nxt_StRS0	(Bk1nxt_StRS0),
			.WriteDone	(Bk1WriteDone),
			.ReadDone	(Bk1ReadDone),
			.DBusInEn	(Bk1DBusInEn),
			.MB1stRASout	(Bk1MB1stRAS),
			.LastWCAS	(Bk1LastWCAS),
			.StWS1		(Bk1StWS1)
			);

BankCtrl	BankCtrl2 (
			.memclk		(memclk),
			.Reset		(Reset),
			.AnyNextCMD	(AnyNextCMD),
			.OtherCAS	(Bk3CAS),
			.OtherDCAS	(Bk3DCAS),
			.Match		(Bk2Match),
			.CASMatch	(Bk2CASMatch),
			.NAE		(NAE),
			.AllCCR		(AllCCR),
			.AllCCW		(AllCCW),
			.AllDone	(AllDone),
			.P62p5		(P62p5),
			.OtherStAi	(Bk3StAi),
			.OtherStA2	(Bk3StA2),
			.OtherStA3	(Bk3StA3),
			.OtherLastStA3	(Bk3LastStA3),
			.StB0		(Pr1StB0[6]),
			.OtherStB0	(Pr0StB0[6]),
			.StB1		(Pr1StB1),
			.nxt_StB1	(Pr1nxt_StB1),
			.MB1stAct	(Bk2MB1stAct),
			.MBAct		(Bk2MBAct),
			.Device		(Bk2Device),
			.Read		(Bk2Read),
			.Length		(Bk2Length[6:3]),
			.Addr		(Bk2Addr[6:3]),
			.I		(Bk2I),
			.D		(Bk2D),
			.M		(Bk2M),
			.StRi		(StRi),
			.SBSel		(Pr1SBSel),
			.TCL2		(TCL2),
			.TCL3		(TCL3),
			.TCL4		(TCL4),
			.TRCD4		(TRCD4),
			.TRASp2		(TRASp2),
			.TRP4		(TRP4),
			.Trdel		(Trdel),
			.Twdel		(Twdel),
			.M36		(Bk2M36),
			.OtherWriteDone	(Bk3WriteDone),
			.OtherReadDone	(Bk3ReadDone),
			.MB1stRAS	(Bk3MB1stRAS),
			.APrechrg	(APrechrg),

			.StAi		(Bk2StAi),
			.StA2		(Bk2StA2),
			.StA3		(Bk2StA3),
			.LastStA3	(Bk2LastStA3),
			.XCnt		(Bk2XCnt),
			.NextCMD	(Bk2NextCMD),
			.WCAS		(Bk2WCAS),
			.RCAS		(Bk2RCAS),
			.DCAS		(Bk2DCAS),
			.PRAS		(Bk2PRAS),
			.APCAS		(Bk2APCAS),
			.RAS		(Bk2RAS),
			.StM0		(Bk2StM0),
			.CCR		(Bk2CCR),
			.ReadEn		(Bk2ReadEn),
			.nxt_Start	(Bk2nxt_Start),
			.pre_start	(Bk2pre_start),
			.nxt_Last	(Bk2nxt_Last),
			.nxt_Done	(Bk2nxt_Done),
			.Pend		(Bk2Pend),
			.BlockRdy	(Bk2BlockRdy),
			.LastCAS	(Bk2LastCAS),
			.nxt_StRS0	(Bk2nxt_StRS0),
			.WriteDone	(Bk2WriteDone),
			.ReadDone	(Bk2ReadDone),
			.DBusInEn	(Bk2DBusInEn),
			.MB1stRASout	(Bk2MB1stRAS),
			.LastWCAS	(Bk2LastWCAS),
			.StWS1		(Bk2StWS1)
			);

BankCtrl	BankCtrl3 (
			.memclk		(memclk),
			.Reset		(Reset),
			.AnyNextCMD	(AnyNextCMD),
			.OtherCAS	(Bk2CAS),
			.OtherDCAS	(Bk2DCAS),
			.Match		(Bk3Match),
			.CASMatch	(Bk3CASMatch),
			.NAE		(NAE),
			.AllCCR		(AllCCR),
			.AllCCW		(AllCCW),
			.AllDone	(AllDone),
			.P62p5		(P62p5),
			.OtherStAi	(Bk2StAi),
			.OtherStA2	(Bk2StA2),
			.OtherStA3	(Bk2StA3),
			.OtherLastStA3	(Bk2LastStA3),
			.StB0		(Pr1StB0[7]),
			.OtherStB0	(Pr0StB0[7]),
			.StB1		(Pr1StB1),
			.nxt_StB1	(Pr1nxt_StB1),
			.MB1stAct	(Bk3MB1stAct),
			.MBAct		(Bk3MBAct),
			.Device		(Bk3Device),
			.Read		(Bk3Read),
			.Length		(Bk3Length[6:3]),
			.Addr		(Bk3Addr[6:3]),
			.I		(Bk3I),
			.D		(Bk3D),
			.M		(Bk3M),
			.StRi		(StRi),
			.SBSel		(Pr1SBSel),
			.TCL2		(TCL2),
			.TCL3		(TCL3),
			.TCL4		(TCL4),
			.TRCD4		(TRCD4),
			.TRASp2		(TRASp2),
			.TRP4		(TRP4),
			.Trdel		(Trdel),
			.Twdel		(Twdel),
			.M36		(Bk3M36),
			.OtherWriteDone	(Bk2WriteDone),
			.OtherReadDone	(Bk2ReadDone),
			.MB1stRAS	(Bk2MB1stRAS),
			.APrechrg	(APrechrg),

			.StAi		(Bk3StAi),
			.StA2		(Bk3StA2),
			.StA3		(Bk3StA3),
			.LastStA3	(Bk3LastStA3),
			.XCnt		(Bk3XCnt),
			.NextCMD	(Bk3NextCMD),
			.WCAS		(Bk3WCAS),
			.RCAS		(Bk3RCAS),
			.DCAS		(Bk3DCAS),
			.PRAS		(Bk3PRAS),
			.APCAS		(Bk3APCAS),
			.RAS		(Bk3RAS),
			.StM0		(Bk3StM0),
			.CCR		(Bk3CCR),
			.ReadEn		(Bk3ReadEn),
			.nxt_Start	(Bk3nxt_Start),
			.pre_start	(Bk3pre_start),
			.nxt_Last	(Bk3nxt_Last),
			.nxt_Done	(Bk3nxt_Done),
			.Pend		(Bk3Pend),
			.BlockRdy	(Bk3BlockRdy),
			.LastCAS	(Bk3LastCAS),
			.nxt_StRS0	(Bk3nxt_StRS0),
			.WriteDone	(Bk3WriteDone),
			.ReadDone	(Bk3ReadDone),
			.DBusInEn	(Bk3DBusInEn),
			.MB1stRASout	(Bk3MB1stRAS),
			.LastWCAS	(Bk3LastWCAS),
			.StWS1		(Bk3StWS1)
			);

ByteMask	ByteMask (
			.memclk		(memclk),
			.Reset		(Reset),
			.CBusMask	(CBusMask),
			.Bk0WCAS	(Bk0WCAS),
			.Bk0M		(Bk0M),
			.Bk0D		(Bk0D),
			.Bk0Length	(Bk0Length),
			.Bk0Addr	(Bk0MAddr),
			.Bk0XCnt	(Bk0XCnt),
			.Bk1WCAS	(Bk1WCAS),
			.Bk1M		(Bk1M),
			.Bk1D		(Bk1D),
			.Bk1Length	(Bk1Length),
			.Bk1Addr	(Bk1MAddr),
			.Bk1XCnt	(Bk1XCnt),
			.Bk2WCAS	(Bk2WCAS),
			.Bk2M		(Bk2M),
			.Bk2D		(Bk2D),
			.Bk2Length	(Bk2Length),
			.Bk2Addr	(Bk2MAddr),
			.Bk2XCnt	(Bk2XCnt),
			.Bk3WCAS	(Bk3WCAS),
			.Bk3M		(Bk3M),
			.Bk3D		(Bk3D),
			.Bk3Length	(Bk3Length),
			.Bk3Addr	(Bk3MAddr),
			.Bk3XCnt	(Bk3XCnt),
			.M36WD0		(M36WD0),

			.MaskOut	(MaskOut)
			);

AddrOut		AddrOut (
			.memclk		(memclk),
			.Reset		(Reset),
			.Bk0WCAS	(Bk0WCAS),
			.Bk0RCAS	(Bk0RCAS),
			.Bk0PRAS	(Bk0PRAS),
			.Bk0APCAS	(Bk0APCAS),
			.Bk0RAS		(Bk0RAS),
			.Bk0D		(Bk0D),
			.Bk0I		(Bk0I),
			.Bk0XCnt	(Bk0XCnt),
			.Bk0Addr	(Bk0Addr),
			.Bk0M36		(Bk0M36),
			.Bk1WCAS	(Bk1WCAS),
			.Bk1RCAS	(Bk1RCAS),
			.Bk1PRAS	(Bk1PRAS),
			.Bk1APCAS	(Bk1APCAS),
			.Bk1RAS		(Bk1RAS),
			.Bk1D		(Bk1D),
			.Bk1I		(Bk1I),
			.Bk1XCnt	(Bk1XCnt),
			.Bk1Addr	(Bk1Addr),
			.Bk1M36		(Bk1M36),
			.Bk2WCAS	(Bk2WCAS),
			.Bk2RCAS	(Bk2RCAS),
			.Bk2PRAS	(Bk2PRAS),
			.Bk2APCAS	(Bk2APCAS),
			.Bk2RAS		(Bk2RAS),
			.Bk2D		(Bk2D),
			.Bk2I		(Bk2I),
			.Bk2XCnt	(Bk2XCnt),
			.Bk2Addr	(Bk2Addr),
			.Bk2M36		(Bk2M36),
			.Bk3WCAS	(Bk3WCAS),
			.Bk3RCAS	(Bk3RCAS),
			.Bk3PRAS	(Bk3PRAS),
			.Bk3APCAS	(Bk3APCAS),
			.Bk3RAS		(Bk3RAS),
			.Bk3D		(Bk3D),
			.Bk3I		(Bk3I),
			.Bk3XCnt	(Bk3XCnt),
			.Bk3Addr	(Bk3Addr),
			.Bk3M36		(Bk3M36),
			.StR1		(StR1),
			.Init_Ref	(Init_Ref),
			.Init_Pre	(Init_Pre),
			.Init_Mod	(Init_Mod),
			.CDataIn	(CDataIn[14:0]),
			.XMem		(XMem),

			.RA		(RA),
			.BA		(BA),
			.CS		(CS),
			.RAS		(RAS),
			.CAS		(CAS),
			.WE		(WE)
			);

	// Data Path Control for Memory Writes

	wire	AnyStM0 = Bk0StM0 | Bk1StM0 | Bk2StM0 | Bk3StM0;

	wire	AnyDBusInEn = Bk0DBusInEn | Bk1DBusInEn 
			    | Bk2DBusInEn | Bk3DBusInEn;

	reg	CBusMaskEn;
	always @(posedge memclk)
		CBusMaskEn <= ~Reset & AnyStM0;

	wire	WD0 = Bk0WCAS | Bk1WCAS | Bk2WCAS | Bk3WCAS;
	reg	WD1;
	reg	WD2;

	assign	M36WD0 = Bk0WCAS & Bk0M36 | Bk1WCAS & Bk1M36 
		       | Bk2WCAS & Bk2M36 | Bk3WCAS & Bk3M36;
	reg	M36WD1;
	reg	M36WD2;

	always @(posedge memclk) begin
		WD1    <= ~Reset & WD0;
		WD2    <= ~Reset & WD1;
		M36WD1 <= ~Reset & M36WD0;
		M36WD2 <= ~Reset & M36WD1;
	end

	reg	d1AnyDBusInEn;
	reg	d2AnyDBusInEn;
	always @(posedge memclk) begin
		d1AnyDBusInEn <= ~Reset &   AnyDBusInEn;
		d2AnyDBusInEn <= ~Reset & d1AnyDBusInEn;
	end

	wire	DBusInEn = d1AnyDBusInEn | d2AnyDBusInEn;

	wire	RDOutEN  = WD1 | WD2;

	wire	RDP = Bk3WCAS & (Bk3Device==`ID_SPAN)
		    | Bk2WCAS & (Bk2Device==`ID_SPAN)
		    | Bk1WCAS & (Bk1Device==`ID_SPAN)
		    | Bk0WCAS & (Bk0Device==`ID_SPAN);

	reg	RDPD1;
	reg	RDPD2;

	always @(posedge memclk) begin
		RDPD1 <= ~Reset & RDP;
		RDPD2 <= ~Reset & RDPD1;
	end

	reg	Pr0dbus_write_enable;
	reg	Pr1dbus_write_enable;
	reg	mi_dbus_write_enable;
	reg	sp_dbus_write_enable;
	reg	span_dbus_write_enable;
	reg	pi_dbus_write_enable;
	reg	si_dbus_write_enable;
	reg	ui_dbus_write_enable;

	reg	[3:0]	reg_Pr0Device;
	reg	[3:0]	reg_Pr1Device;

	reg	Pr0_off;
	reg	Pr1_off;
	reg	reg_Bk0StWS1;
	reg	reg_Bk1StWS1;
	reg	reg_Bk2StWS1;
	reg	reg_Bk3StWS1;

	always @(posedge memclk) begin
	Pr0_off <= ~(Bk0LastWCAS & ~(Pr0StB5 | Pr0StB2))
		 & ~(Bk1LastWCAS & ~(Pr0StB5 | Pr0StB2));
	Pr1_off <= ~(Bk2LastWCAS & ~(Pr1StB5 | Pr1StB2))
		 & ~(Bk3LastWCAS & ~(Pr1StB5 | Pr1StB2));
	reg_Bk0StWS1 <= Bk0StWS1;
	reg_Bk1StWS1 <= Bk1StWS1;
	reg_Bk2StWS1 <= Bk2StWS1;
	reg_Bk3StWS1 <= Bk3StWS1;
	end

	wire	[3:0]	hld_Pr0Device 
			=(~Pr0dbus_write_enable &   reg_Bk0StWS1
			| ~Pr0dbus_write_enable &   reg_Bk1StWS1)
			?  Pr0Device
			:  reg_Pr0Device;

	wire	[3:0]	hld_Pr1Device 
			=(~Pr1dbus_write_enable &   reg_Bk2StWS1
			| ~Pr1dbus_write_enable &   reg_Bk3StWS1)
			?  Pr1Device
			:  reg_Pr1Device;

	wire	Pr0nxt_dbus_write_enable 
			= ~Pr0dbus_write_enable &   reg_Bk0StWS1
			| ~Pr0dbus_write_enable &   reg_Bk1StWS1
			|  Pr0dbus_write_enable 
		& ~(Bk0LastWCAS & ~(Pr0StB5 | Pr0StB2)) 
		& ~(Bk1LastWCAS & ~(Pr0StB5 | Pr0StB2))
		&  Pr0_off;

	wire	Pr1nxt_dbus_write_enable 
			= ~Pr1dbus_write_enable &   reg_Bk2StWS1
			| ~Pr1dbus_write_enable &   reg_Bk3StWS1
			|  Pr1dbus_write_enable 
		& ~(Bk2LastWCAS & ~(Pr1StB5 | Pr1StB2)) 
		& ~(Bk3LastWCAS & ~(Pr1StB5 | Pr1StB2))
		&  Pr1_off;

	always @(posedge sysclk) begin
	reg_Pr0Device 		<= hld_Pr0Device;
	reg_Pr1Device 		<= hld_Pr1Device;
	Pr0dbus_write_enable    <= ~Reset & Pr0nxt_dbus_write_enable;
	Pr1dbus_write_enable    <= ~Reset & Pr1nxt_dbus_write_enable;

	mi_dbus_write_enable    
		<= ~Reset & Pr0nxt_dbus_write_enable & (hld_Pr0Device==`ID_MI)
		 | ~Reset & Pr1nxt_dbus_write_enable & (hld_Pr1Device==`ID_MI);
	sp_dbus_write_enable    
		<= ~Reset & Pr0nxt_dbus_write_enable & (hld_Pr0Device==`ID_SP)
		 | ~Reset & Pr1nxt_dbus_write_enable & (hld_Pr1Device==`ID_SP);
	span_dbus_write_enable  
		<= ~Reset & Pr0nxt_dbus_write_enable & (hld_Pr0Device==`ID_SPAN)
		 | ~Reset & Pr1nxt_dbus_write_enable & (hld_Pr1Device==`ID_SPAN);
	pi_dbus_write_enable    
		<= ~Reset & Pr0nxt_dbus_write_enable & (hld_Pr0Device==`ID_PI)
		 | ~Reset & Pr1nxt_dbus_write_enable & (hld_Pr1Device==`ID_PI);
	si_dbus_write_enable    
		<= ~Reset & Pr0nxt_dbus_write_enable & (hld_Pr0Device==`ID_SI)
		 | ~Reset & Pr1nxt_dbus_write_enable & (hld_Pr1Device==`ID_SI);
	ui_dbus_write_enable    
		<= ~Reset & Pr0nxt_dbus_write_enable & (hld_Pr0Device==`ID_UI)
		 | ~Reset & Pr1nxt_dbus_write_enable & (hld_Pr1Device==`ID_UI);
	end
		
	wire		DBusOutEn;
	reg		mi_dbus_read_enable;
	reg		sp_dbus_read_enable;
	reg		span_dbus_read_enable;
	reg		vi_dbus_read_enable;
	reg		ui_dbus_read_enable;
	reg	[1:0]	D4ReadNum;

	wire	nxt_mi_rd_en =	~mi_dbus_read_enable & (
		  DBusOutEn & (D4ReadNum==2'b11) & (Bk3Device==`ID_MI)
		| DBusOutEn & (D4ReadNum==2'b10) & (Bk2Device==`ID_MI)
		| DBusOutEn & (D4ReadNum==2'b01) & (Bk1Device==`ID_MI)
		| DBusOutEn & (D4ReadNum==2'b00) & (Bk0Device==`ID_MI))
		|  mi_dbus_read_enable & DBusOutEn;

	wire	nxt_sp_rd_en =	~sp_dbus_read_enable & (
		  DBusOutEn & (D4ReadNum==2'b11) & (Bk3Device==`ID_SP)
		| DBusOutEn & (D4ReadNum==2'b10) & (Bk2Device==`ID_SP)
		| DBusOutEn & (D4ReadNum==2'b01) & (Bk1Device==`ID_SP)
		| DBusOutEn & (D4ReadNum==2'b00) & (Bk0Device==`ID_SP)
		| DBusOutEn & (D4ReadNum==2'b11) & (Bk3Device==`ID_CMD)
		| DBusOutEn & (D4ReadNum==2'b10) & (Bk2Device==`ID_CMD)
		| DBusOutEn & (D4ReadNum==2'b01) & (Bk1Device==`ID_CMD)
		| DBusOutEn & (D4ReadNum==2'b00) & (Bk0Device==`ID_CMD))
		|  sp_dbus_read_enable & DBusOutEn;

	wire	nxt_span_rd_en = ~span_dbus_read_enable & (
		  DBusOutEn & (D4ReadNum==2'b11) & (Bk3Device==`ID_SPAN)
		| DBusOutEn & (D4ReadNum==2'b10) & (Bk2Device==`ID_SPAN)
		| DBusOutEn & (D4ReadNum==2'b01) & (Bk1Device==`ID_SPAN)
		| DBusOutEn & (D4ReadNum==2'b00) & (Bk0Device==`ID_SPAN))
		|  span_dbus_read_enable & DBusOutEn;

	wire	nxt_vi_rd_en = ~vi_dbus_read_enable & (
		  DBusOutEn & (D4ReadNum==2'b11) & (Bk3Device==`ID_VI)
		| DBusOutEn & (D4ReadNum==2'b10) & (Bk2Device==`ID_VI)
		| DBusOutEn & (D4ReadNum==2'b01) & (Bk1Device==`ID_VI)
		| DBusOutEn & (D4ReadNum==2'b00) & (Bk0Device==`ID_VI))
		|  vi_dbus_read_enable & DBusOutEn;

	wire	nxt_ui_rd_en = ~ui_dbus_read_enable & (
		  DBusOutEn & (D4ReadNum==2'b11) & (Bk3Device==`ID_UI)
		| DBusOutEn & (D4ReadNum==2'b10) & (Bk2Device==`ID_UI)
		| DBusOutEn & (D4ReadNum==2'b01) & (Bk1Device==`ID_UI)
		| DBusOutEn & (D4ReadNum==2'b00) & (Bk0Device==`ID_UI))
		|  ui_dbus_read_enable & DBusOutEn;

	always @(posedge sysclk) begin
		mi_dbus_read_enable   <= ~Reset & nxt_mi_rd_en;
		sp_dbus_read_enable   <= ~Reset & nxt_sp_rd_en;
		span_dbus_read_enable <= ~Reset & nxt_span_rd_en;
		vi_dbus_read_enable   <= ~Reset & nxt_vi_rd_en;
		ui_dbus_read_enable   <= ~Reset & nxt_ui_rd_en;
	end

	wire	nxt_bugcheck3 = (  vi_dbus_read_enable
			      |    ui_dbus_read_enable
			      |  span_dbus_read_enable
			      |    sp_dbus_read_enable
			      |    mi_dbus_read_enable) &
			        (span_dbus_write_enable
			      |    mi_dbus_write_enable
			      |    sp_dbus_write_enable
			      |    pi_dbus_write_enable
			      |    si_dbus_write_enable
			      |    ui_dbus_write_enable);

	reg	bugcheck3;
	always @(posedge memclk)
		bugcheck3 <= nxt_bugcheck3 & ~Reset;
	// synopsys translate_off
	always @(bugcheck3) 
	if (bugcheck3) begin
	$display("ERROR: %t: %M: dbus read/write overlap", $time);
	repeat (20) @(posedge memclk);
	$finish;
	end
	// synopsys translate_on

	// Data Path for Memory Writes

	reg	[63:0]	DBusIn;

	wire	[63:0]	nxt_DBusIn = DBusInEn ? dbus_din : DBusIn;

	always @(posedge sysclk)
			DBusIn <= nxt_DBusIn;

	reg	[7:0]	EBusIn;

	wire	[7:0]	nxt_EBusIn = DBusInEn ? ebus_din : EBusIn;

	always @(posedge sysclk)
			EBusIn <= nxt_EBusIn;

	wire	[63:0]	RDOut;

	assign		RDOut[63:32] = {32{WD1          }} & DBusIn[63:32]
				     | {32{WD2 & ~M36WD2}} & DBusIn[63:32]
				     | {32{WD2 &  M36WD2}} & DBusIn[31:0];

	wire	[31:0]	Nibble0 = RDPD1 ? {7'b0000000,EBusIn[7],
					   7'b0000000,EBusIn[6],
					   7'b0000000,EBusIn[5],
					   7'b0000000,EBusIn[4]}
				        : {7'b0000000,DBusIn[48],
					   7'b0000000,DBusIn[48],
					   7'b0000000,DBusIn[32],
					   7'b0000000,DBusIn[32]};

	wire	[31:0]	Nibble1 = RDPD2 ? {7'b0000000,EBusIn[3],
					   7'b0000000,EBusIn[2],
					   7'b0000000,EBusIn[1],
					   7'b0000000,EBusIn[0]}
				        : {7'b0000000,DBusIn[16],
					   7'b0000000,DBusIn[16],
					   7'b0000000,DBusIn[0],
					   7'b0000000,DBusIn[0]};

	assign	RDOut[31:0] = {32{WD1 &  M36WD1}} & Nibble0
			    | {32{WD2 &  M36WD2}} & Nibble1
			    | {32{WD1 & ~M36WD1}} & DBusIn[31:0]
			    | {32{WD2 & ~M36WD2}} & DBusIn[31:0];

	wire	[63:0]	nxt_CBusMask = CBusMaskEn ? DBusIn : CBusMask;

	always @(posedge memclk)
			CBusMask <= nxt_CBusMask;

	// Data Path Control for Memory Reads

	reg	d2ReadEn;
	reg	d1ReadEn;
	reg	p1ReadEn;
	reg	p2ReadEn;
	reg	p3ReadEn;
	reg	p4ReadEn;
	reg	p5ReadEn;
	reg	p6ReadEn;
	reg	p7ReadEn;
	reg	p8ReadEn;
	reg	p9ReadEn;
	reg	pAReadEn;

	wire	d0ReadEn = Bk0ReadEn | Bk1ReadEn | Bk2ReadEn | Bk3ReadEn;

	always @(posedge memclk) begin
		d2ReadEn <= ~Reset & d1ReadEn;
		d1ReadEn <= ~Reset & p1ReadEn;
		p1ReadEn <= ~Reset & p2ReadEn;
		p2ReadEn <= ~Reset & p3ReadEn;
		p3ReadEn <= ~Reset & p4ReadEn;
		p4ReadEn <= ~Reset & (TRD2 ? d0ReadEn : p5ReadEn);
		p5ReadEn <= ~Reset & p6ReadEn;
		p6ReadEn <= ~Reset & (TRD3 ? d0ReadEn : p7ReadEn);
		p7ReadEn <= ~Reset & p8ReadEn;
		p8ReadEn <= ~Reset & (TRD4 ? d0ReadEn : p9ReadEn);
		p9ReadEn <= ~Reset & pAReadEn;
		pAReadEn <= ~Reset & (TRD5 ? d0ReadEn : 1'b0);
	end

	wire	ReadEn =        p1ReadEn;

	wire	RDInEn	=  TCL2 & TRD5 & p8ReadEn
			|  TCL3 & TRD5 & p7ReadEn
			|  TCL4 & TRD5 & p6ReadEn
			|  TCL2 & TRD4 & p6ReadEn
			|  TCL3 & TRD4 & p5ReadEn
			|  TCL4 & TRD4 & p4ReadEn
			|  TCL2 & TRD3 & p4ReadEn
			|  TCL3 & TRD3 & p3ReadEn
			|  TCL4 & TRD3 & p2ReadEn
			|  TCL2 & TRD2 & p2ReadEn
			|  TCL3 & TRD2 & p1ReadEn
			|  TCL4 & TRD2 & d1ReadEn;

	reg	d2M64;
	reg	d1M64;
	reg	p1M64;
	reg	p2M64;
	reg	p3M64;
	reg	p4M64;
	reg	p5M64;
	reg	p6M64;
	reg	p7M64;
	reg	p8M64;
	reg	p9M64;
	reg	pAM64;

	wire	d0M64 = Bk0ReadEn & ~Bk0M36 | Bk1ReadEn & ~Bk1M36
		      | Bk2ReadEn & ~Bk2M36 | Bk3ReadEn & ~Bk3M36;

	always @(posedge memclk) begin
		d2M64 <= d1M64;
		d1M64 <= p1M64;
		p1M64 <= p2M64;
		p2M64 <= p3M64;
		p3M64 <= p4M64;
		p4M64 <= TRD2 ? d0M64 : p5M64;
		p5M64 <= p6M64;
		p6M64 <= TRD3 ? d0M64 : p7M64;
		p7M64 <= p8M64;
		p8M64 <= TRD4 ? d0M64 : p9M64;
		p9M64 <= pAM64;
		pAM64 <= TRD5 ? d0M64 : 1'b0;
	end

	wire	M64    =        p1M64;

	reg	dly1_M64;
	reg	dly2_M64;
	reg	dly3_M64;
	reg	dly4_M64;
	reg	dly5_M64;
	reg	dly6_M64;

	always @(posedge memclk) begin
		dly1_M64 <= ~Reset & M64;
		dly2_M64 <= ~Reset & dly1_M64;
		dly3_M64 <= ~Reset & dly2_M64;
		dly4_M64 <= ~Reset & dly3_M64;
		dly5_M64 <= ~Reset & dly4_M64;
		dly6_M64 <= ~Reset & dly5_M64 & ~P62p5;
	end

	wire	DBusM64 =        dly5_M64 | dly6_M64;

	wire	[1:0]	d0ReadNum = {(Bk3ReadEn | Bk2ReadEn),
				     (Bk3ReadEn | Bk1ReadEn)};

	reg	[1:0]	p1ReadNum;
	reg	[1:0]	p2ReadNum;
	reg	[1:0]	p3ReadNum;
	reg	[1:0]	p4ReadNum;
	reg	[1:0]	p5ReadNum;
	reg	[1:0]	p6ReadNum;
	reg	[1:0]	p7ReadNum;
	reg	[1:0]	p8ReadNum;
	reg	[1:0]	p9ReadNum;
	reg	[1:0]	pAReadNum;

	always @(posedge memclk) begin
		p1ReadNum <= p2ReadNum;
		p2ReadNum <= p3ReadNum;
		p3ReadNum <= p4ReadNum;
		p4ReadNum <= TRD2 ? d0ReadNum : p5ReadNum;
		p5ReadNum <= p6ReadNum;
		p6ReadNum <= TRD3 ? d0ReadNum : p7ReadNum;
		p7ReadNum <= p8ReadNum;
		p8ReadNum <= TRD4 ? d0ReadNum : p9ReadNum;
		p9ReadNum <= pAReadNum;
		pAReadNum <= TRD5 ? d0ReadNum : 2'b0;
	end

	reg	[1:0]	ReadNum;
	reg	[1:0]	D1ReadNum;
	reg	[1:0]	D2ReadNum;
	reg	[1:0]	D3ReadNum;

	always @(posedge memclk) begin
		ReadNum   <= p1ReadNum;
		D1ReadNum <= ReadNum;
		D2ReadNum <= D1ReadNum;
		D3ReadNum <= D2ReadNum;
		D4ReadNum <= D3ReadNum;
	end

	reg	dly1_ReadEn;
	reg	dly2_ReadEn;
	reg	dly3_ReadEn;
	reg	dly4_ReadEn;
	reg	dly5_ReadEn;
	reg	p0_DBusOutEn;
	reg	p1_DBusOutEn;

	always @(posedge memclk) begin
			dly1_ReadEn  <= ~Reset & ReadEn;
			dly2_ReadEn  <= ~Reset & dly1_ReadEn;
			dly3_ReadEn  <= ~Reset & dly2_ReadEn;
			dly4_ReadEn  <= ~Reset & dly3_ReadEn;
			dly5_ReadEn  <= ~Reset & dly4_ReadEn;
			p0_DBusOutEn <= ~Reset & dly4_ReadEn;
			p1_DBusOutEn <= ~Reset & DBusOutEn & ~P62p5;
	end

	assign	DBusOutEn = p0_DBusOutEn | p1_DBusOutEn;

	always @(posedge sysclk) 
			DBusOE      <= ~Reset & DBusOutEn;

	assign	AllCCW = AllCCR 
			& ~p1ReadEn & ~p2ReadEn & ~p3ReadEn & ~p4ReadEn 
			& ~p5ReadEn & ~p6ReadEn & ~p7ReadEn & ~p8ReadEn
			& ~p9ReadEn & ~pAReadEn & ~d0ReadEn 
			& ~d1ReadEn & ~d2ReadEn 
			&      ~ReadEn & ~dly1_ReadEn & ~dly2_ReadEn 
			& ~dly3_ReadEn & ~dly4_ReadEn & ~dly5_ReadEn 
		        & ~DBusOutEn & ~DBusOE;

	// Data Path for Memory Reads

	reg	[63:0]	D1RDIn;

	always @(posedge memclk)
			D1RDIn <= mdin;

	wire	[63:0]	d0RDIn = TCL3 ? D1RDIn : mdin;

	reg	[63:0]	p0RDIn;
	reg	[63:0]	p1RDIn;
	reg	[63:0]	p2RDIn;
	reg	[63:0]	p3RDIn;
	reg	[63:0]	p4RDIn;
	reg	[63:0]	p5RDIn;
	reg	[63:0]	p6RDIn;
	reg	[63:0]	p7RDIn;
	reg	[63:0]	p8RDIn;
	reg	[63:0]	p9RDIn;
	reg	[63:0]	pARDIn;

	always @(posedge memclk) begin
			p0RDIn <= p1RDIn;
			p1RDIn <= p2RDIn;
			p2RDIn <= (TRD2 & ~TCL2) ? d0RDIn : p3RDIn;
			p3RDIn <= p4RDIn;
			p4RDIn <= (TRD2 &  TCL2 |
				   TRD3 & ~TCL2) ? d0RDIn : p5RDIn;
			p5RDIn <= p6RDIn;
			p6RDIn <= (TRD3 &  TCL2 |
				   TRD4 & ~TCL2) ? d0RDIn : p7RDIn;
			p7RDIn <= p8RDIn;
			p8RDIn <= (TRD4 &  TCL2 |
				   TRD5 & ~TCL2) ? d0RDIn : p9RDIn;
			p9RDIn <= pARDIn;
			pARDIn <= (TRD5 &  TCL2) ? d0RDIn : 64'b0;
	end

	reg	[63:0]	DBusOut;
	reg	[7:0]	EBusOut;

	wire	[63:0]	`XDEL nxt_DBusOut = 
			DBusOutEn ? (DBusM64  ?  p0RDIn[63:0]
					      : {p0RDIn[63:32],
						 p1RDIn[63:32]})
				  :  DBusOut;

	wire	[7:0]	`XDEL nxt_EBusOut = DBusOutEn ? {p0RDIn[24],
						   p0RDIn[16],
						   p0RDIn[8],
						   p0RDIn[0],
						   p1RDIn[24],
						   p1RDIn[16],
						   p1RDIn[8],
						   p1RDIn[0]}
						:  EBusOut;
	always @(posedge sysclk) begin
			DBusOut <= nxt_DBusOut;
			EBusOut <= nxt_EBusOut;
	end

	wire	[63:0]	dbus_dout =  DBusOE ? DBusOut : 64'b0;

	wire	[7:0]	ebus_dout =  DBusOE ? EBusOut : 8'b0;

	// CBus Register Reads, Writes and Responses Infrastructure

	reg	CAE_Resp;
	reg	CAE_Read;
	reg	CAE_Write;

	reg	[31:0]	CAddrIn;

	wire	RISpace = (CAddrIn[31:20]==`BUS_ADDRESS_RI);

	wire	nxt_CAE_Resp  = ~CAE_Resp  & (cbus_command==`CMD_RESPONSE);
	wire	nxt_CAE_Read  = ~CAE_Read  & (cbus_command==`CMD_READ);
	wire	nxt_CAE_Write = ~CAE_Write & (cbus_command==`CMD_WRITE);

	always @(posedge memclk) 
		begin
		CAE_Resp  <= ~Reset & nxt_CAE_Resp;
		CAE_Read  <= ~Reset & nxt_CAE_Read;
		CAE_Write <= ~Reset & nxt_CAE_Write;
		end

	reg	nxt_COutEN;
	reg	COutEN;

	always @(posedge memclk) begin
		nxt_COutEN <= ~Reset & CAE_Read;
		COutEN     <= ~Reset & nxt_COutEN;
	end

	wire	CAE =  CAE_Read | CAE_Write;

	reg	dly_CAE_Write;
	reg	CDE;
	reg	RegWriteEn;
	wire	nxt_CDE = dly_CAE_Write & RISpace;

	always @(posedge memclk) begin
		dly_CAE_Write <= ~Reset & CAE_Write;
		CDE           <= ~Reset & nxt_CDE;
		RegWriteEn    <= ~Reset & CDE;
	end

	wire	[31:0]	nxt_CAddrIn = CAE ? cbus_din : CAddrIn;
	wire	[31:0]	nxt_CDataIn = CDE ? cbus_din : CDataIn;

	always @(posedge memclk) begin
			CAddrIn <= nxt_CAddrIn;
			CDataIn <= nxt_CDataIn;
	end

	wire	nxt_cbus_read_request =  
			    ~cbus_read_request & nxt_COutEN & RISpace
			 |   cbus_read_request & ~cbus_read_grant;

	reg	cbus_read_request;
	always @(posedge memclk)
		cbus_read_request <= ~Reset & nxt_cbus_read_request;

	// CBus Register

	// Invert the strobes

	wire	Tsr_Sel = (CAddrIn[19:4]==`SREV_SET);

	wire	Tsr_Write = RegWriteEn & Tsr_Sel;

	reg	[4:0]	strobe_rev;
	wire	[4:0]	nxt_strobe_rev =  Reset ? 5'b0 
						: (Tsr_Write ? {5{CDataIn[0]}}
						  	     : strobe_rev);
	always @(posedge memclk) 
			strobe_rev  <= nxt_strobe_rev;

	// Enables greater that 16MByte
	//  which move the AP bit from CAS A8 to A10

	wire	Txm_Sel = (CAddrIn[19:4]==`XMEM_SET);

	wire	Txm_Write = RegWriteEn & Txm_Sel;

	wire	nxt_XMem = Reset ? 1'b0
				     : (Txm_Write ? CDataIn[0]
						  : XMem);
	always @(posedge memclk) 
			XMem  <= nxt_XMem;

	// Auto Precharge Only Mode

	wire	Tapm_Sel = (CAddrIn[19:4]==`AUTO_SET);

	wire	Tapm_Write = RegWriteEn & Tapm_Sel;

	wire	nxt_APrechrg = Reset ? 1'b1
				     : (Tapm_Write ? CDataIn[0]
						   : APrechrg);
	always @(posedge memclk) 
			APrechrg  <= nxt_APrechrg;

	reg		Tras;
	reg		Trp;
	reg		Trcd;
	reg	[3:0]	Trfc;
	reg	[2:0]	Tcl;

	// Memory Parameter Register (mpr)

	wire	Tmpr_Sel = (CAddrIn[19:4]==`TMPR_SET);

	wire	Tmpr_Write = RegWriteEn & Tmpr_Sel;

	wire	[2:0]	nxt_Trdel = Reset ?  3'h3	
					  : (Tmpr_Write ? CDataIn[26:24]
						        : Trdel);

	wire	[2:0]	nxt_Twdel = Reset ?  3'h1	
					  : (Tmpr_Write ? CDataIn[22:20]
						        : Twdel);

	wire		nxt_Tras = Reset ?  1'b0	// Tras = 7 (else 9)
					 : (Tmpr_Write ? CDataIn[16]
						       : Tras);

	assign	TRASp2 = (Tras==1'b1);

	wire		nxt_Trp  = Reset ?  1'h0	// Trp  = 3 (else 4)
					 : (Tmpr_Write ? CDataIn[12]
						       : Trp);
	assign	TRP4 = (Trp==1'b1);

	wire		nxt_Trcd  = Reset ?  1'b0	// Trcd  = 3 (else 4)
					  : (Tmpr_Write ? CDataIn[8]
						        : Trcd);

	assign	TRCD4 = (Trcd==1'h1);

	wire	[3:0]	nxt_Trfc = Reset ?  4'hF	//    2 = 16
							//    1 = 17
							//    0 = 18
							//  3-F = 3-15
					 : (Tmpr_Write ? CDataIn[7:4]
						       : Trfc);

	wire	[2:0]	nxt_Tcl = Reset ? 3'h3
					: (Tmpr_Write ? CDataIn[2:0]
						      : Tcl);
	
	always @(posedge memclk) begin
			Trdel <= nxt_Trdel;
			Twdel <= nxt_Twdel;
			Tras  <= nxt_Tras;
			Trp   <= nxt_Trp;
			Trcd  <= nxt_Trcd;
			Trfc  <= nxt_Trfc;
			Tcl   <= nxt_Tcl;
	end

	reg	[3:0]	TrfcCnt;
	wire	[3:0]	nxt_TrfcCnt = 
			Reset ? 4'b0 
			      : StR1 ? Trfc
			 	     : (TrfcCnt==4'h3) ? TrfcCnt
						       : TrfcCnt - 4'h1;

	always @(posedge memclk)
			TrfcCnt <= nxt_TrfcCnt;

	// Mode Register and Maintanance Access

	reg	Write_MRS;

	wire	nxt_Write_MRS = ~Write_MRS & RegWriteEn 
			      & ({CAddrIn[19:4]}==`MODE_SET)
			      |  Write_MRS & ~StR1;

	always @(posedge memclk) 
		Write_MRS <= ~Reset & nxt_Write_MRS;

	assign	Init_Ref = Write_MRS & ~CDataIn[31] &  CDataIn[30];

	assign	Init_Pre = Write_MRS &  CDataIn[31] & ~CDataIn[30];

	assign	Init_Mod = Write_MRS &  CDataIn[31] &  CDataIn[30]
			 | Write_MRS & ~CDataIn[31] & ~CDataIn[30];


	// Refresh and Maintanance Operation State Machine

	reg	RefReq;

	wire	MaintReq = Write_MRS;

	wire	AllStAi = Bk0StAi & Bk1StAi & Bk2StAi & Bk3StAi;

	wire	nxt_StRi = StRi & ~MaintReq & ~RefReq
			 | StR2 & (TrfcCnt[3:0]==4'h3); 

	wire	nxt_StR0 = StRi &  RefReq
			 | StRi &  MaintReq
			 | StR0 & ~AllStAi;

	wire	nxt_StR1 = StR0 &  AllStAi;

	wire	nxt_StR2 = StR1
			 | StR2 & ~(TrfcCnt[3:0]==4'h3);

	always @(posedge memclk) begin
		StRi <=  Reset | nxt_StRi;
		StR0 <= ~Reset & nxt_StR0;
		StR1 <= ~Reset & nxt_StR1;
		StR2 <= ~Reset & nxt_StR2;
	end

	assign	TCL2 = (Tcl==3'b010);
	assign	TCL3 = (Tcl==3'b011) | (Tcl==3'b110);
	assign	TCL4 = (Tcl==3'b100);
	assign	TCL6 = (Tcl==3'b110);

	// Refresh Counter

	// Divide memclk by 32 to get basic units of refresh

	reg	[4:0]	Ref_Div;
	reg		RefEn;

	wire	[4:0]	nxt_Ref_Div = RefEn ? Ref_Div + 1'b1
					    : 5'b0;

	always @(posedge memclk)
	if (Reset)	Ref_Div = 5'b0;
	else		Ref_Div = nxt_Ref_Div;

	reg	Inc_Ref_Cntr;
	wire	nxt_Inc_Ref_Cntr = ~Ref_Div[4] & nxt_Ref_Div[4];

	always @(posedge memclk)
		Inc_Ref_Cntr = nxt_Inc_Ref_Cntr;

	// Refresh Interval Register, contains the number of
	// basic units between refresh request
	// Refresh Rate = memclk / (32 * Tref)
	// Refresh Period (usec) = (32 * Tref) / memclk frequecy (MHz)
	// Tref = 0 is equivalent to 256

	reg	[11:4]	Tref;

	wire	Tref_Sel = (CAddrIn[19:4]==`TREF_SET);

	wire	Tref_Write = RegWriteEn & Tref_Sel;

	wire	[11:4]	nxt_Tref  = Tref_Write ? CDataIn[11:4]
					       : Tref;

	wire		nxt_RefEn = Tref_Write ? CDataIn[12]
					       : RefEn;
	always @(posedge memclk)
	if (Reset)	Tref <= 8'h70;
	else		Tref <= nxt_Tref;

	always @(posedge memclk)
	if (Reset)	RefEn <= 1'b0;
	else		RefEn <= nxt_RefEn;

	reg	[7:0]	Ref_Cntr;

	wire	[7:0]	nxt_Ref_Cntr = 
		(RefReq | Tref_Write) ? 8'h00
		        : Inc_Ref_Cntr ? Ref_Cntr + 1'b1
				       : Ref_Cntr;
	always @(posedge memclk)
	if (Reset)	Ref_Cntr <= 8'h00;
	else		Ref_Cntr <= nxt_Ref_Cntr;

	wire	nxt_RefReq = ~(Ref_Cntr==Tref) & (nxt_Ref_Cntr==Tref);

	always @(posedge memclk)
		RefReq = nxt_RefReq;

	// CBus Register Read Data Out

	reg	[31:0]	CDataOut;
	wire	[31:0]	ReadData;

	assign	ReadData = (Tref_Sel ? {{19{1'b0}},
					    RefEn,
					    Tref,
					    4'b0}
				      : 32'b0)

			 | (Tmpr_Sel ?  {1'b0,Trdel,
			    		 1'b0,Twdel,
			    		 3'b0,Tras,
			    		 3'b0,Trp,
			    		 3'b0,Trcd,
					      Trfc,
					 1'b0,Tcl}
				      : 32'b0)

			 | (Tsr_Sel  ? {{31'b0,strobe_rev[0]}} : 32'b0)
			 | (Txm_Sel  ? {{31'b0,XMem}}	       : 32'b0)
			 | (Tapm_Sel ? {{31'b0,APrechrg}}      : 32'b0) ;

	wire	[31:0]	`XDEL nxt_CDataOut = COutEN ? ReadData : CDataOut;

	always @(posedge sysclk)
			CDataOut <= nxt_CDataOut;

	assign	cbus_dout =  cbus_write_enable ? CDataOut : 32'b0;

	assign mcke = ~Reset;
	assign maddr = RA;
	assign mbank = BA;
	assign mdin_ena = RDInEn;
	assign mdout = RDOut;
	assign mdout_ena = RDOutEN;
	assign mras = RAS;
	assign mcas = CAS;
	assign mwe = WE;
	assign mdqm = MaskOut;

endmodule