Makefile
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# Makefile for compiling top-level RSP Verilog simulation
VCS_SRC_DIR = /ecad/sgi/bin
VCS_OPTIONS_LOC = +libext+.v+libext+.vzd+libext+.vmd \
+incdir+$(ROOT)/PR/hw/chip/rcp/su/src \
+incdir+$(ROOT)/PR/hw/chip/rcp/vu/src \
+incdir+$(ROOT)/PR/hw/chip/rcp/inc \
-Mupdate=1 -Mdir=sgicom -l vcs.log
RSP_LIBS_LOC = -y . \
-y $(ROOT)/PR/hw/chip/rcp/rsp/src \
-y $(ROOT)/PR/hw/chip/rcp/su/src \
-y $(ROOT)/PR/hw/chip/rcp/vu/src \
-y $(ROOT)/PR/hw/chip/rcp/ls/src \
-y $(ROOT)/PR/hw/chip/rcp/dm/src \
-y $(ROOT)/PR/hw/chip/rcp/io/src \
-y $(ROOT)/PR/hw/chip/rcp/su/fixes \
-y $(ROOT)/PR/hw/chip/lib/verilog/dp \
-y $(ROOT)/PR/hw/chip/lib/verilog/stdcell \
-y $(ROOT)/PR/hw/chip/lib/verilog/ram \
-y $(ROOT)/PR/hw/chip/lib/verilog/user
VCS_OPTIONS_INST = +libext+.v+libext+.vzd+libext+.vmd \
+incdir+/hosts/madman/mdev/PR/hw/chip/rcp/su/src \
+incdir+/hosts/madman/mdev/PR/hw/chip/rcp/vu/src \
+incdir+/hosts/madman/mdev/PR/hw/chip/rcp/inc \
-Mupdate=1 -Mdir=sgicom -l vcs.log
RSP_LIBS_INST = -y . \
-y /hosts/madman/mdev/PR/hw/chip/rcp/rsp/src \
-y /hosts/madman/mdev/PR/hw/chip/rcp/su/src \
-y /hosts/madman/mdev/PR/hw/chip/rcp/vu/src \
-y /hosts/madman/mdev/PR/hw/chip/rcp/ls/src \
-y /hosts/madman/mdev/PR/hw/chip/rcp/dm/src \
-y /hosts/madman/mdev/PR/hw/chip/rcp/io/src \
-y /hosts/madman/mdev/PR/hw/chip/rcp/su/fixes \
-y /hosts/madman/mdev/PR/hw/chip/lib/verilog/dp \
-y /hosts/madman/mdev/PR/hw/chip/lib/verilog/stdcell \
-y /hosts/madman/mdev/PR/hw/chip/lib/verilog/ram \
-y /hosts/madman/mdev/PR/hw/chip/lib/verilog/user
rspWrap:
$(VCS_SRC_DIR)/compile.vcs $(RSP_LIBS_LOC) $(VCS_OPTIONS_LOC) rspWrap.v
instRsp:
$(VCS_SRC_DIR)/compile.vcs $(RSP_LIBS_INST) $(VCS_OPTIONS_INST) rspWrap.v