// bcp.v v1 Frank Berndt
// bcp top level;
// :set tabstop=4

`timescale 1ns/1ns

module bcp (
	sysclk, memclk, rst_l, reset_l, avrst_l, pll_lock,
	pll_bypass,
	button,
	divmode, coldrst_l, warmrst_l,
	sysad_out, sysad_in, syscmd_out, syscmd_in,
	pvalid_l, eok_l, evalid_l, int_l, nmi_l,
	v_recall, v_tread, v_time, v_me, v_we,
	v0_addr, v0_in, v0_out,
	v1_addr, v1_in, v1_out,
	v2_addr, v2_in, v2_out,
	mcke, maddr, mbank,
	mdin, mdin_ena, mdout, mdout_ena, strobe_rev,
	mras, mcas, mwe, mdqm,
	vclock, vdata, vsync, avctrl,
	aclock, adata, aword,
	jchan_in, jchan_ena, jchan_oe,
	lctrl_x, lctrl_y,
	io_rst, io_in, io_ena, io_out, io_oe, io_ale,
	io_ior, io_iow, io_cs, io_dmarq, io_dmack, io_intr,
	fl_ce, fl_ale, fl_cle, fl_re, fl_we, fl_wp, fl_ryby, fl_md,
	gpio_oe, gpio_out, gpio_in,
	usb_clk, usb_sel_sys,
	usb_dp, usb_dpo, usb_dm, usbxr_ose,
	usbxr_y1, usbxr_oen, usbxr_ien, usbxr_fl,
	usb_dp_high, usb_d_low_n,usb_vbus_vld,
	usb_id, usb_vbus_on_n,
	dbg_rst, dbg_boot, dbg_sena, dbg_sclk, dbg_swe, dbg_sre, dbg_si, dbg_so
);

`include "rcp.vh"
`include "define.vh"

	// global signals;

	input sysclk;				// system clock;
	input memclk;				// memory clock;
	input rst_l;				// pin reset;
	output reset_l;				// system reset;
	input avrst_l ;
	input [1:0] pll_lock;		// important plls are locked;
	input pll_bypass;			// bypass plls;
	input button;				// button input;

	// r4300 interface;

	output [2:0] divmode;		// cpu freuqency config;
	output coldrst_l;			// cpu cold reset;
	output warmrst_l;			// cpu warm reset;
	input [31:0] sysad_out;		// system addr/data from cpu;
	output [31:0] sysad_in;		// system addr/data to cpu;
	input [4:0] syscmd_out;		// system command from cpu;
	output [4:0] syscmd_in;		// system command to cpu;
	input pvalid_l;				// processor data valid;
	output eok_l;				// external agent ok;
	output evalid_l;			// external data valid;
	output [4:0] int_l;			// cpu interupts;
	output nmi_l;				// non-maskable interrupt;

	// virage flash interface;

	output v_recall;			// virage recall on hard reset;
	output v_tread;				// virage read for test enable;
	output v_time;				// virage time base, 1us;
	output [2:0] v_me;			// virage memory enables;
	output [2:0] v_we;			// virage write enables;
	output [15:2] v0_addr;		// virage 0 address;
	output [31:0] v0_in;		// virage 0 write data;
	input [31:0] v0_out;		// virage 0 read data;
	output [15:2] v1_addr;		// virage 1 address;
	output [31:0] v1_in;		// virage 1 write data;
	input [31:0] v1_out;		// virage 1 read data;
	output [15:2] v2_addr;		// virage 2 address;
	output [31:0] v2_in;		// virage 2 write data;
	input [31:0] v2_out;		// virage 2 read data;

	// memory interface;

	output		mcke;		// clock enable;
	output	[12:0]	maddr;		// row/col address;
	output	[1:0]	mbank;		// bank address;
	input	[63:0]	mdin;		// input data;
	output		mdin_ena;	// input register enable;
	output	[63:0]	mdout;		// output data;
	output		mdout_ena;	// output enable;
	output	[4:0]	strobe_rev;	// invert strobes
	output mras, mcas, mwe;		// command;
	output	[7:0]	mdqm;		// byte enables;

	// video/audio DAC interface;

	input vclock;				// video clock;
	output [6:0] vdata;			// video data;
	output vsync;				// video sync;
	output [25:0] avctrl;		// video pll controls;
	output aclock;				// audio clock;
	output adata;				// audio data;
	output aword;				// audio word clock;

	// joy channel interface;

	input [3:1] jchan_in;		// joychannel ctrl inputs;
	output [3:1] jchan_ena;		// enable joychannel input regs;
	output [3:1] jchan_oe;		// enable joychannel drivers;

	// local joystick;

	input [1:0] lctrl_x;		// stick x inputs;
	input [1:0] lctrl_y;		// stick y inputs;

	// generic io interface;

	output io_rst;				// io bus reset;
	input [15:0] io_in;			// io input data;
	output io_ena;				// io input clock enables;
	output [15:0] io_out;		// io output data;
	output [1:0] io_oe;			// io data output enables;
	output io_ale;				// io address latch enable;
	output io_ior;				// io read pulse;
	output io_iow;				// io write pulse;
	output [3:0] io_cs;			// io pio chip selects;
	input io_dmarq;				// io dma request;
	output io_dmack;			// io dma acknowledge;
	input io_intr;				// io device interrupt;

	// nand flash controls;

	output [3:0] fl_ce;			// chip enables;
	output fl_ale;				// address latch enable;
	output fl_cle;				// command latch enable;
	output fl_re;				// read eanble;
	output fl_we;				// write eanble;
	output fl_wp;				// write protect;
	input fl_ryby;				// ready/busy;
	input fl_md;				// module detect;

	// general purpose io;

	output [3:0] gpio_oe;		// output enables;
	output [3:0] gpio_out;		// output values;
	input [3:0] gpio_in;		// input values;

	// USB propagated up signals
	input 		 usb_clk;	    // 48MHz usb clk
	output		usb_sel_sys;
	
	input  [1:0] usb_dp;           
	input  [1:0] usb_dm;
	output [1:0] usb_dpo;
	output [1:0] usbxr_ose;
	
    input  [1:0] usbxr_y1;
	output [1:0] usbxr_oen;
	output [1:0] usbxr_ien;
	output [1:0] usbxr_fl;

    output [1:0] usb_dp_high;    // resistor signals
    output [1:0] usb_d_low_n;
    
    input  [1:0] usb_vbus_vld;
    input  [1:0] usb_id;        //  OTG signals
    output [1:0] usb_vbus_on_n;

	// test interface;

	input dbg_rst;			// cpu reset for debug;
	input dbg_boot;			// boot from bram instead of brom;
	input dbg_sena;			// debug serial enable;
	input dbg_sclk;			// debug serial clock;
	input dbg_swe;			// debug serial write enable;
	input dbg_sre;			// debug serial read enable;
	input dbg_si;			// debug serial in;
	output dbg_so;			// debug serial out;

	// bcp reset signal;
	// rst_l -> mi -> reset_l -> bcp blocks, pads;
	// rst_l -> mi -> reset_h   -> ui, ri;
	//             -> coldrst_l -> r4300
	//             -> warmrst_l -> r4300
	//             -> pi ioc

	wire reset_l;			// system reset;
	wire reset_h;			// system reset active high;
	wire start_gclk;		// start gated clock;

	// sp signals;

	wire sp_cbus_read_enable, sp_cbus_write_enable;
	wire sp_dma_request, sp_dma_grant;
	wire sp_dma_start, sp_dma_last;
	wire sp_read_request, sp_read_grant;
	wire sp_dbus_read_enable, sp_dbus_write_enable;
	wire sp_intr;

	wire cbuf_ready, cbuf_write;
	wire cmd_busy;
	wire pipe_busy;
	wire tmem_busy;
	wire flush;
	wire freeze, unfreeze;

	wire mem_read_request;
	wire mem_cbus_read_enable, mem_cbus_write_enable;

	wire cmd_cbus_read_enable, cmd_cbus_write_enable;
	wire cmd_dma_request, cmd_dma_grant;
	wire cmd_read_request, cmd_read_grant;

	// mi signals;

	wire mi_dma_request;
	wire mi_dma_start, mi_dma_last;
	wire mi_cbus_read_request, mi_cbus_write_request;
	wire mi_cbus_write_enable;
	wire mi_cbus_grant;
	wire mi_dbus_read_enable, mi_dbus_write_enable;

	// pi signals;

	wire pi_cbus_write_enable;
	wire pi_cbus_error;
	wire pi_read_request, pi_read_grant;
	wire pi_dbus_write_enable;
	wire pi_dma_request, pi_dma_grant;
	wire pi_dma_start, pi_dma_last;
	wire pi_intr;
	wire pi_aes_intr;
	wire pi_flc_intr;
	wire pi_ide_intr;
	wire pi_err_trap;
	wire pi_err_intr;

	// si signals;

	wire lctrl_req;				// si requests button sample;
	wire lctrl_val;				// button sample valid from pi;
	wire [13:0] lctrl_but;		// button data;

	wire si_cbus_write_enable;
	wire si_read_request, si_read_grant;
	wire si_dbus_write_enable;
	wire si_dma_request, si_dma_grant;
	wire si_dma_start, si_dma_last;
	wire si_intr;

	// vi signals;

	wire vi_cbus_read_enable, vi_cbus_write_enable;
	wire vi_read_request, vi_read_grant;
	wire vi_dma_request, vi_dma_grant;
	wire vi_dma_start, vi_dma_last;
	wire vi_intr;

	// ui signals;

	wire ui_cbus_read_enable, ui_cbus_write_enable;
	wire ui_read_request, ui_read_grant;
	wire ui_dbus_write_enable, ui_dbus_read_enable;
	wire ui_dma_request, ui_dma_grant;
	wire ui_dma_start;
	wire ui_irq;

	// ai signals;

	wire ai_cbus_read_enable, ai_cbus_write_enable;
	wire ai_read_request, ai_read_grant;
	wire ai_dma_request, ai_dma_grant;
	wire ai_dma_start, ai_dma_last;
	wire ai_intr;

	// span signals;

	wire span_dbus_read_enable, span_dbus_write_enable;
	wire span_cbus_read_enable, span_cbus_write_enable;
	wire span_read_request, span_read_grant;
	wire span_dma_request, span_dma_grant;
	wire span_dma_start, span_dma_last;

	// ri signals;

	wire ri_read_request, ri_read_grant;
	wire ri_cbus_read_enable, ri_cbus_write_enable;
	wire dma_ready;

	// common cbus signals;

	wire [2:0] cbus_command;
	wire [1:0] cbus_select;
	wire [31:0] cbus_din;
	wire [63:0] dbus_din;
	wire [7:0] ebus_din;
	wire [63:0] xbus_data;

	wire [31:0] rsp_cbus_dout;
	wire [31:0] rdp_cbus_dout;
	wire [31:0] mi_cbus_dout;
	wire [31:0] pi_cbus_dout;
	wire [31:0] si_cbus_dout;
	wire [31:0] vi_cbus_dout;
	wire [31:0] ai_cbus_dout;
	wire [31:0] ri_cbus_dout;
	wire [31:0] ui_cbus_dout;

	wire [63:0] rsp_dbus_dout;
	wire [63:0] rdp_dbus_dout;
	wire [63:0] mi_dbus_dout;
	wire [63:0] pi_dbus_dout;
	wire [63:0] si_dbus_dout;
	wire [63:0] ri_dbus_dout;
	wire [63:0] ui_dbus_dout;

	wire [7:0] rdp_ebus_dout;
	wire [7:0] ri_ebus_dout;

	`RSP rsp (
		.clk(sysclk),
		.reset_l(reset_l),
		.sp_cbus_read_enable(sp_cbus_read_enable),
		.sp_cbus_write_enable(sp_cbus_write_enable),
		.mem_cbus_write_enable(mem_cbus_write_enable),
		.cmd_cbus_read_enable(cmd_cbus_read_enable),
		.cmd_cbus_write_enable(cmd_cbus_write_enable),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.dma_start(sp_dma_start),
		.dma_last(sp_dma_last),
		.sp_dma_grant(sp_dma_grant),
		.sp_read_grant(sp_read_grant),
		.cmd_dma_grant(cmd_dma_grant),
		.cmd_read_grant(cmd_read_grant),
		.sp_dbus_read_enable(sp_dbus_read_enable),
		.sp_dbus_write_enable(sp_dbus_write_enable),
		.cbuf_ready(cbuf_ready),
		.cmd_busy(cmd_busy),
		.pipe_busy(pipe_busy),
		.tmem_busy(tmem_busy),
		.frozen(start_gclk),
		.sp_dma_request(sp_dma_request),
		.sp_read_request(sp_read_request),
		.mem_read_request(mem_read_request),
		.cmd_dma_request(cmd_dma_request),
		.cmd_read_request(cmd_read_request),
		.cbuf_write(cbuf_write),
		.flush(flush),
		.freeze(freeze),
		.unfreeze(unfreeze),
		.sp_interrupt(sp_intr),
		.xbus_data(xbus_data),
		.cbus_din(cbus_din),
		.cbus_dout(rsp_cbus_dout),
		.dbus_din(dbus_din),
		.dbus_dout(rsp_dbus_dout)
	);

	// instantiate rdp or dummy;

	`RDP rdp (
		.clk(sysclk),
		.reset_l(reset_l),
		.cbus_write_enable(span_cbus_write_enable),
		.cbus_read_enable(span_cbus_read_enable),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.xbus_cs_data(xbus_data),
		.xbus_cs_valid(cbuf_write),
		.flush(flush),
		.freeze(freeze),
		.unfreeze(unfreeze),
		.grant(span_dma_grant),
		.start(span_dma_start),
		.finish(span_dma_last),
		.read_grant(span_read_grant),
		.dma_write_enable(span_dbus_write_enable),
		.dma_read_enable(span_dbus_read_enable),
		.cs_xbus_req(cbuf_ready),
		.start_gclk(start_gclk),
		.rdramreq(span_dma_request),
		.read_request(span_read_request),
		.cmd_busy(cmd_busy),
		.pipe_busy(pipe_busy),
		.tmem_busy(tmem_busy),
		.cbus_din(cbus_din),
		.cbus_dout(rdp_cbus_dout),
		.dbus_din(dbus_din),
		.dbus_dout(rdp_dbus_dout),
		.ebus_din(ebus_din),
		.ebus_dout(rdp_ebus_dout)
	);

	// instantiate new mi;
	// pi is the only one reporting cbus errors;

	wire [31:0] version;	// mi version number;
	wire secure;			// cpu in secure mode;
	wire [1:0] usb_intr;	// usb interrupts;
	wire jchan_clk;			// si jchan clock for mi button timer;

	assign version = { 8'd2, 8'd2, 8'hb0, 8'hb0 };

	mi mi (
		.sysclk(sysclk),
		.randclk(vclock),
		.rst_l(rst_l),
		.reset_l(reset_l),
		.reset_h(reset_h),
		.pll_lock(pll_lock),
		.divmode(divmode),
		.coldrst_l(coldrst_l),
		.warmrst_l(warmrst_l),
		.sysad_out(sysad_out),
		.sysad_in(sysad_in),
		.syscmd_out(syscmd_out),
		.syscmd_in(syscmd_in),
		.pvalid_l(pvalid_l),
		.eok_l(eok_l),
		.evalid_l(evalid_l),
		.int_l(int_l),
		.nmi_l(nmi_l),
		.cbus_din(cbus_din),
		.cbus_dout(mi_cbus_dout),
		.cbus_error(pi_cbus_error),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.cbus_write_enable(mi_cbus_write_enable),
		.cbus_write_request(mi_cbus_write_request),
		.cbus_read_request(mi_cbus_read_request),
		.cbus_grant(mi_cbus_grant),
		.dbus_din(dbus_din),
		.dbus_dout(mi_dbus_dout),
		.dbus_enable(mi_dbus_write_enable),
		.dma_request(mi_dma_request),
		.dma_start(mi_dma_start),
		.dma_last(mi_dma_last),
		.button(button),
		.jchan_clk(jchan_clk),
		.fl_md(fl_md),
		.pi_intr(pi_intr),
		.si_intr(si_intr),
		.vi_intr(vi_intr),
		.ai_intr(ai_intr),
		.sp_intr(sp_intr),
		.pipe_busy(pipe_busy),
		.pi_aes_intr(pi_aes_intr),
		.pi_flc_intr(pi_flc_intr),
		.pi_ide_intr(pi_ide_intr),
		.pi_err_intr(pi_err_intr),
		.pi_err_trap(pi_err_trap),
		.usb_intr(usb_intr),
		.v_recall(v_recall),
		.v_tread(v_tread),
		.v_time(v_time),
		.v_me(v_me),
		.v_we(v_we),
		.v0_addr(v0_addr),
		.v0_in(v0_in),
		.v0_out(v0_out),
		.v1_addr(v1_addr),
		.v1_in(v1_in),
		.v1_out(v1_out),
		.v2_addr(v2_addr),
		.v2_in(v2_in),
		.v2_out(v2_out),
		.version(version),
		.secure(secure),
		.avctrl(avctrl),
		.dbg_rst(dbg_rst),
		.dbg_boot(dbg_boot),
		.dbg_sena(dbg_sena),
		.dbg_sclk(dbg_sclk),
		.dbg_swe(dbg_swe),
		.dbg_sre(dbg_sre),
		.dbg_si(dbg_si),
		.dbg_so(dbg_so)
	);

	// instantiate pi;

	pi pi (
		.sysclk(sysclk),
		.rst_l(rst_l),
		.reset_l(reset_l),
		.secure(secure),
		.cbus_din(cbus_din),
		.cbus_dout(pi_cbus_dout),
		.cbus_error(pi_cbus_error),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.cbus_write_enable(pi_cbus_write_enable),
		.cbus_read_request(pi_read_request),
		.cbus_read_grant(pi_read_grant),
		.dbus_din(dbus_din),
		.dbus_dout(pi_dbus_dout),
		.dbus_enable(pi_dbus_write_enable),
		.dma_request(pi_dma_request),
		.dma_grant(pi_dma_grant),
		.dma_start(pi_dma_start),
		.dma_last(pi_dma_last),
		.dma_intr(pi_intr),
		.aes_intr(pi_aes_intr),
		.flc_intr(pi_flc_intr),
		.ide_intr(pi_ide_intr),
		.err_intr(pi_err_intr),
		.err_trap(pi_err_trap),
		.io_rst(io_rst),
		.io_in(io_in),
		.io_ena(io_ena),
		.io_out(io_out),
		.io_oe(io_oe),
		.io_ale(io_ale),
		.io_ior(io_ior),
		.io_iow(io_iow),
		.io_cs(io_cs),
		.io_dmarq(io_dmarq),
		.io_dmack(io_dmack),
		.io_intr(io_intr),
		.fl_ce(fl_ce),
		.fl_ale(fl_ale),
		.fl_cle(fl_cle),
		.fl_re(fl_re),
		.fl_we(fl_we),
		.fl_wp(fl_wp),
		.fl_ryby(fl_ryby),
		.fl_md(fl_md),
		.lctrl_req(lctrl_req),
		.lctrl_val(lctrl_val),
		.lctrl_but(lctrl_but),
		.gpio_oe(gpio_oe),
		.gpio_out(gpio_out),
		.gpio_in(gpio_in)
	);

	// instantiate si logic;
	// JoyChannel ctrl io registers are in pad layer;

	si si (
		.sysclk(sysclk),
		.reset_l(reset_l),
		.cbus_din(cbus_din),
		.cbus_dout(si_cbus_dout),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.cbus_write_enable(si_cbus_write_enable),
		.cbus_read_request(si_read_request),
		.cbus_read_grant(si_read_grant),
		.dbus_din(dbus_din),
		.dbus_dout(si_dbus_dout),
		.dbus_enable(si_dbus_write_enable),
		.dma_request(si_dma_request),
		.dma_grant(si_dma_grant),
		.dma_start(si_dma_start),
		.dma_last(si_dma_last),
		.dma_intr(si_intr),
		.jchan_clk(jchan_clk),
		.jchan_in(jchan_in),
		.jchan_ena(jchan_ena),
		.jchan_oe(jchan_oe),
		.lctrl_req(lctrl_req),
		.lctrl_val(lctrl_val),
		.lctrl_but(lctrl_but),
		.lctrl_x(lctrl_x),
		.lctrl_y(lctrl_y)
	);

	// instantiate vi logic;

	`VI vi (
		.clk(sysclk),
		.reset_l(avrst_l),
		.cbus_din(cbus_din),
		.cbus_dout(vi_cbus_dout),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.cbus_read_enable(vi_cbus_read_enable),
		.cbus_write_enable(vi_cbus_write_enable),
		.read_request(vi_read_request),
		.read_grant(vi_read_grant),
		.dbus_data(dbus_din),
		.dma_request(vi_dma_request),
		.dma_grant(vi_dma_grant),
		.dma_start(vi_dma_start),
		.dma_last(vi_dma_last),
		.ebus_data(ebus_din),
		.vclk(vclock),
		.vbus_clock_enable_l(),
		.vbus_data(vdata),
		.vbus_sync(vsync),
		.vi_int(vi_intr)
	);

	// instantiate ai logic;

	`AI ai (
		.clock(sysclk),
		.reset_l(avrst_l),
		.cbus_din(cbus_din),
		.cbus_dout(ai_cbus_dout),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.cbus_read_enable(ai_cbus_read_enable),
		.cbus_write_enable(ai_cbus_write_enable),
		.read_request(ai_read_request),
		.read_grant(ai_read_grant),
		.dbus_data(dbus_din),
		.dma_request(ai_dma_request),
		.dma_grant(ai_dma_grant),
		.dma_start(ai_dma_start),
		.vbus_clock(vclock),
		.abus_clock(aclock),
		.abus_data(adata),
		.abus_word(aword),
		.ai_full(ai_intr)
	);

	// instantiate cbus arbiter;

	arb arb (
		.clock(sysclk),
		.reset_l(reset_l),
		.dma_ready(dma_ready),
		.sp_dma_request(sp_dma_request),
		.sp_read_request(sp_read_request),
		.mem_read_request(mem_read_request),
		.mi_dma_request(mi_dma_request),
		.mi_write_request(mi_cbus_write_request),
		.mi_read_request(mi_cbus_read_request),
		.cmd_dma_request(cmd_dma_request),
		.cmd_read_request(cmd_read_request),
		.ri_read_request(ri_read_request),
		.pi_dma_request(pi_dma_request),
		.pi_read_request(pi_read_request),
		.si_dma_request(si_dma_request),
		.si_read_request(si_read_request),
		.ai_dma_request(ai_dma_request),
		.ai_read_request(ai_read_request),
		.vi_dma_request(vi_dma_request),
		.vi_read_request(vi_read_request),
		.ui_dma_request(ui_dma_request),
		.ui_read_request(ui_read_request),
		.span_dma_request(span_dma_request),
		.span_read_request(span_read_request),
		.sp_cbus_read_enable(sp_cbus_read_enable),
		.sp_cbus_write_enable(sp_cbus_write_enable),
		.sp_dma_grant(sp_dma_grant),
		.sp_read_grant(sp_read_grant),
		.mem_cbus_write_enable(mem_cbus_write_enable),
		.mi_cbus_read_enable(),
		.mi_cbus_write_enable(mi_cbus_write_enable),
		.mi_cbus_grant(mi_cbus_grant),
		.cmd_cbus_read_enable(cmd_cbus_read_enable),
		.cmd_cbus_write_enable(cmd_cbus_write_enable),
		.cmd_dma_grant(cmd_dma_grant),
		.cmd_read_grant(cmd_read_grant),
		.ri_cbus_read_enable(ri_cbus_read_enable),
		.ri_cbus_write_enable(ri_cbus_write_enable),
		.ri_read_grant(ri_read_grant),
		.pi_cbus_read_enable(),
		.pi_cbus_write_enable(pi_cbus_write_enable),
		.pi_dma_grant(pi_dma_grant),
		.pi_read_grant(pi_read_grant),
		.si_cbus_read_enable(),
		.si_cbus_write_enable(si_cbus_write_enable),
		.si_dma_grant(si_dma_grant),
		.si_read_grant(si_read_grant),
		.ai_cbus_read_enable(ai_cbus_read_enable),
		.ai_cbus_write_enable(ai_cbus_write_enable),
		.ai_dma_grant(ai_dma_grant),
		.ai_read_grant(ai_read_grant),
		.vi_cbus_read_enable(vi_cbus_read_enable),
		.vi_cbus_write_enable(vi_cbus_write_enable),
		.vi_dma_grant(vi_dma_grant),
		.vi_read_grant(vi_read_grant),
		.ui_cbus_read_enable(ui_cbus_read_enable),
		.ui_cbus_write_enable(ui_cbus_write_enable),
		.ui_dma_grant(ui_dma_grant),
		.ui_read_grant(ui_read_grant),
		.span_cbus_read_enable(span_cbus_read_enable),
		.span_cbus_write_enable(span_cbus_write_enable),
		.span_dma_grant(span_dma_grant),
		.span_read_grant(span_read_grant),
		.cbus_select(cbus_select),
		.cbus_command(cbus_command),
		.rsp_cbus_dout(rsp_cbus_dout),
		.rsp_dbus_dout(rsp_dbus_dout),
		.rdp_cbus_dout(rdp_cbus_dout),
		.rdp_dbus_dout(rdp_dbus_dout),
		.rdp_ebus_dout(rdp_ebus_dout),
		.mi_cbus_dout(mi_cbus_dout),
		.mi_dbus_dout(mi_dbus_dout),
		.pi_cbus_dout(pi_cbus_dout),
		.pi_dbus_dout(pi_dbus_dout),
		.si_cbus_dout(si_cbus_dout),
		.si_dbus_dout(si_dbus_dout),
		.vi_cbus_dout(vi_cbus_dout),
		.ai_cbus_dout(ai_cbus_dout),
		.ri_cbus_dout(ri_cbus_dout),
		.ri_dbus_dout(ri_dbus_dout),
		.ri_ebus_dout(ri_ebus_dout),
		.ui_cbus_dout(ui_cbus_dout),
		.ui_dbus_dout(ui_dbus_dout),
		.cbus_din(cbus_din),
		.dbus_din(dbus_din),
		.ebus_din(ebus_din)

	);

	// instantiate ram interface;

	ri ri (
		.sysclk(sysclk),
		.memclk(memclk),
		.pll_bypass(pll_bypass),
		.reset_l(reset_l),
		.cbus_read_enable(ri_cbus_read_enable),
		.cbus_write_enable(ri_cbus_write_enable),
		.cbus_command(cbus_command),
		.cbus_din(cbus_din),
		.cbus_dout(ri_cbus_dout),
		.cbus_read_request(ri_read_request),
		.cbus_read_grant(ri_read_grant),
		.dbus_din(dbus_din),
		.dbus_dout(ri_dbus_dout),
		.ebus_din(ebus_din),
		.ebus_dout(ri_ebus_dout),
		.dma_ready(dma_ready),
		.mi_dma_start(mi_dma_start),
		.mi_dma_last(mi_dma_last),
		.sp_dma_start(sp_dma_start),
		.sp_dma_last(sp_dma_last),
		.span_dma_start(span_dma_start),
		.span_dma_last(span_dma_last),
		.pi_dma_start(pi_dma_start),
		.pi_dma_last(pi_dma_last),
		.si_dma_start(si_dma_start),
		.si_dma_last(si_dma_last),
		.ai_dma_start(ai_dma_start),
		.ai_dma_last(ai_dma_last),
		.vi_dma_start(vi_dma_start),
		.vi_dma_last(vi_dma_last),
		.ui_dma_start(ui_dma_start),
		.mi_dbus_read_enable(mi_dbus_read_enable),
		.mi_dbus_write_enable(mi_dbus_write_enable),
		.sp_dbus_read_enable(sp_dbus_read_enable),
		.sp_dbus_write_enable(sp_dbus_write_enable),
		.span_dbus_read_enable(span_dbus_read_enable),
		.span_dbus_write_enable(span_dbus_write_enable),
		.pi_dbus_write_enable(pi_dbus_write_enable),
		.si_dbus_write_enable(si_dbus_write_enable),
		.ui_dbus_read_enable(ui_dbus_read_enable),
		.ui_dbus_write_enable(ui_dbus_write_enable),
		.mcke(mcke),
		.maddr(maddr),
		.mbank(mbank),
		.mdin(mdin),
		.mdin_ena(mdin_ena),
		.mdout(mdout),
		.mdout_ena(mdout_ena),
		.strobe_rev(strobe_rev),
		.mras(mras),
		.mcas(mcas),
		.mwe(mwe),
		.mdqm(mdqm)
	);

ui ui (
	.sysclk			(sysclk),
	.Reset			(reset_h),
	.cbus_write_enable	(ui_cbus_write_enable),
	.cbus_select		(cbus_select),
	.cbus_command		(cbus_command),
	.cbus_din		(cbus_din),
	.cbus_dout		(ui_cbus_dout),
	.cbus_read_request	(ui_read_request),
	.cbus_read_grant	(ui_read_grant),
	.cbus_dma_request	(ui_dma_request),
	.cbus_dma_grant		(ui_dma_grant),
	.dbus_din		(dbus_din),
	.dbus_dout		(ui_dbus_dout),
	.dma_start		(ui_dma_start),
	.dbus_read_enable	(ui_dbus_read_enable),
	.dbus_write_enable	(ui_dbus_write_enable),
	.secure			(secure),
	.irq			(usb_intr),
	.usb_clk  		(usb_clk),
	.usb_sel_sys  	(usb_sel_sys),
	.usb_dp			(usb_dp),
	.usb_dm			(usb_dm),
	.usb_dpo		(usb_dpo),
	.usbxr_ose		(usbxr_ose),
	.usbxr_y1		(usbxr_y1),
	.usbxr_oen		(usbxr_oen),
	.usbxr_ien		(usbxr_ien),
	.usbxr_fl		(usbxr_fl),
	.usb_dp_high		(usb_dp_high),
	.usb_d_low_n		(usb_d_low_n),
	.usb_vbus_vld		(usb_vbus_vld),
	.usb_id			(usb_id),
	.usb_vbus_on_n  	(usb_vbus_on_n)
	);

endmodule