su.v
8.59 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: su.v,v 1.2 2002/10/22 19:32:46 doug Exp $
// su.v: RSP scalar unit datapath and control
// std cell version
`timescale 1ns / 10ps
module su (clk, reset_l,
halt, single_step, pc_in_wr_en, pc_data_in,
dma_dm_to_rd, dma_rd_to_dm, dma_imem_select, rd_inst,
rd_base, ls_drive_rd_base, rd_offset, rd_elem_num,
chip_sel, su_ex_store, su_ex_load, vu_ex_store, vu_ex_load,
ex_mfc2, ex_mtc2, ex_cfc2, ex_mfc0,
ex_su_byte_ls, ex_su_half_ls, ex_su_uns_ls,
df_ls_drive_ls_in_wb, df_pass_thru, imem_dma_cycle,
su_nop_debug, vu_nop_debug, pc,
branch_or_addr, set_broke, vu_rd_ld_dec_k, vu_rd_st_dec_k,
break_inst_debug,
ls_data, su_ls_data,
vu_comp, vu_comp_k, vu_func, ex_ctc2_vc0, ex_ctc2_vc1, ex_ctc2_vc2,
vu_rd_store_type_k, vu_elem,
vu_ld_addr, vu_st_addr, vu_st_xpose_addr,
vs, vt, acc_wr_reg, acc_wr_en, store_xpose_rd, load_xpose_wb,
rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k,
cp0_address, cp0_write, cp0_enable, rd_inst_buf);
input clk;
input reset_l;
input halt;
input single_step;
input pc_in_wr_en;
input [11:2] pc_data_in;
input dma_dm_to_rd;
input dma_rd_to_dm;
input dma_imem_select;
input [63:0] rd_inst;
output chip_sel;
output [3:0] rd_base;
output ls_drive_rd_base;
output [3:0] rd_offset;
output [3:0] rd_elem_num;
output su_ex_store;
output su_ex_load;
output vu_ex_store;
output vu_ex_load;
output ex_mfc2;
output ex_mtc2;
output ex_cfc2;
output ex_mfc0;
output ex_su_byte_ls;
output ex_su_half_ls;
output ex_su_uns_ls;
output df_ls_drive_ls_in_wb;
output df_pass_thru;
output imem_dma_cycle; // IF stage to BIST
output su_nop_debug; // RD stage to nowhere
output vu_nop_debug; // RD stage to nowhere
output [11:2] pc; // to IO land
output [11:0] branch_or_addr;
output set_broke;
output [11:0] vu_rd_ld_dec_k; // RD stage
output [11:0] vu_rd_st_dec_k; // RD stage
output break_inst_debug;
input [31:0] ls_data;
output [31:0] su_ls_data;
// Controls for VU
output vu_comp_k;
output vu_comp;
output [5:0] vu_func;
output ex_ctc2_vc0;
output ex_ctc2_vc1;
output ex_ctc2_vc2;
output vu_rd_store_type_k;
output [3:0] vu_elem;
output [4:0] vu_ld_addr;
output [4:0] vu_st_addr;
output [4:0] vu_st_xpose_addr;
output [4:0] vs; // RD: reg num for vs read
output [4:0] vt; // RD: reg num for vt read
output [4:0] acc_wr_reg; // ACC: reg num for datapath writeback
output acc_wr_en; // ACC: write en for dp results
output store_xpose_rd;
output load_xpose_wb;
output rd_cfvc0_k;
output rd_cfvc1_k;
output rd_cfvc2_k;
output [63:0] rd_inst_buf; // buffered instruction to rspbusses
// DMA-related IO
output [3:0] cp0_address; // EX
output cp0_write; // CTC0, EX
output cp0_enable; // CFC0, EX
// RD stage
wire [31:0] su_inst;
wire su_inst6;
wire su_inst15;
wire [4:0] surf_ra; // encoded ra addr
wire [4:0] surf_rb; // decoded rb addr
wire [2:0] surdamux;
wire [2:0] surdbmux;
wire [1:0] suimmmux; // sext or zext immediate
wire suimmlsmux;
wire [2:0] suvulsoffsetmux; // vu l/s offset generation
wire [4:0] sushvamt;
wire [11:0] branch_or_addr_unbuf;
wire [23:0] link_pc_delay_pc; // EX stage to LS
wire sudrivels;
wire sualuamux; // EX stage
wire sualubmux;
wire [1:0] sushamux;
wire [1:0] sushbmux;
wire suslten;
wire susltlt;
wire sualuen;
wire [4:0] sualu;
wire sualu_cin;
wire sualu_cout;
wire sualu_ovr;
wire sualumsb;
wire [4:0] shiftamt;
wire suonesdet_z;
wire suexasign;
wire suexbsign;
// WB stage
wire [4:0] surf_w; // encoded write en
wire surf_wen; // su rf write enable
wire suwben; // enable wb_data into RFile
sudp_sc sudp ( // use std cell version
.clk (clk),
.sualuamux (sualuamux),
.sualubmux (sualubmux),
.sushamux (sushamux),
.sushbmux (sushbmux),
.suslten (suslten),
.sushvamt (sushvamt),
.surf_w (surf_w),
.surf_wen (surf_wen),
.surdbmux (surdbmux),
.suonesdet_z (suonesdet_z),
.surdamux (surdamux),
.sualu_ovr (sualu_ovr),
.sualu_cout (sualu_cout),
.sualu_cin (sualu_cin),
.sualumsb (sualumsb),
.sualu (sualu[4:0]),
.surf_rb (surf_rb),
.surf_ra (surf_ra),
.suimmmux (suimmmux),
.suimmlsmux (suimmlsmux),
.suvulsoffsetmux (suvulsoffsetmux),
.suexasign (suexasign),
.suexbsign (suexbsign),
.sualuen (sualuen),
.susltlt (susltlt),
.suwben (suwben),
.shiftamt (shiftamt),
.inst_data ({su_inst15, su_inst[14:7],
su_inst6, su_inst[5:0]}),
.branch_or_addr (branch_or_addr_unbuf[11:0]),
.link_pc_delay_pc (link_pc_delay_pc),
.sudrivels (sudrivels),
.ls_data (ls_data[31:0]),
.su_ls_data (su_ls_data[31:0])
);
suctl suctl (
.clk (clk),
.reset_l (reset_l),
.halt (halt),
.single_step (single_step),
.pc_in_wr_en (pc_in_wr_en),
.pc_data_in (pc_data_in),
.dma_dm_to_rd (dma_dm_to_rd),
.dma_rd_to_dm (dma_rd_to_dm),
.dma_imem_select (dma_imem_select),
.branch_or_addr_unbuf (branch_or_addr_unbuf),
.rd_inst (rd_inst),
.rd_base (rd_base),
.ls_drive_rd_base (ls_drive_rd_base),
.rd_offset (rd_offset),
.rd_elem_num (rd_elem_num),
.sushvamt (sushvamt),
.sualu_cout (sualu_cout),
.sualu_ovr (sualu_ovr),
.sualumsb (sualumsb),
.suexasign (suexasign),
.suexbsign (suexbsign),
.suonesdet_z (suonesdet_z),
.su_inst (su_inst),
.su_inst6 (su_inst6),
.su_inst15 (su_inst15),
.surf_ra (surf_ra),
.surf_rb (surf_rb),
.surdamux (surdamux),
.surdbmux (surdbmux),
.suimmmux (suimmmux),
.suimmlsmux (suimmlsmux),
.suvulsoffsetmux (suvulsoffsetmux),
.set_broke (set_broke),
.break_inst_debug (break_inst_debug),
.sualuamux (sualuamux),
.sualubmux (sualubmux),
.sushamux (sushamux),
.sushbmux (sushbmux),
.sudrivels (sudrivels),
.suslten (suslten),
.susltlt (susltlt),
.sualuen (sualuen),
.sualu (sualu[4:0]),
.sualu_cin (sualu_cin),
.shiftamt (shiftamt),
.su_ex_store (su_ex_store),
.su_ex_load (su_ex_load),
.vu_ex_store (vu_ex_store),
.vu_ex_load (vu_ex_load),
.ex_mfc2 (ex_mfc2),
.ex_mtc2 (ex_mtc2),
.ex_cfc2 (ex_cfc2),
.ex_su_byte_ls (ex_su_byte_ls),
.ex_su_half_ls (ex_su_half_ls),
.ex_su_uns_ls (ex_su_uns_ls),
.chip_sel (chip_sel),
.vu_rd_ld_dec_k (vu_rd_ld_dec_k),
.vu_rd_st_dec_k (vu_rd_st_dec_k),
.df_ls_drive_ls_in_wb (df_ls_drive_ls_in_wb),
.df_pass_thru (df_pass_thru),
.surf_w (surf_w),
.surf_wen (surf_wen),
.suwben (suwben),
.vu_comp (vu_comp),
.vu_comp_k (vu_comp_k),
.vu_func (vu_func),
.vu_elem (vu_elem),
.vs (vs),
.vt (vt),
.ex_ctc2_vc0 (ex_ctc2_vc0),
.ex_ctc2_vc1 (ex_ctc2_vc1),
.ex_ctc2_vc2 (ex_ctc2_vc2),
.vu_rd_store_type_k (vu_rd_store_type_k),
.rd_cfvc0_k (rd_cfvc0_k),
.rd_cfvc1_k (rd_cfvc1_k),
.rd_cfvc2_k (rd_cfvc2_k),
.acc_wr_reg (acc_wr_reg),
.acc_wr_en (acc_wr_en),
.vu_ld_addr (vu_ld_addr),
.vu_st_addr (vu_st_addr),
.vu_st_xpose_addr (vu_st_xpose_addr),
.store_xpose_rd (store_xpose_rd),
.load_xpose_wb (load_xpose_wb),
.cp0_address (cp0_address),
.cp0_write (cp0_write),
.cp0_enable (cp0_enable),
.ex_mfc0 (ex_mfc0),
.imem_dma_cycle (imem_dma_cycle),
.su_nop_debug (su_nop_debug),
.vu_nop_debug (vu_nop_debug),
.branch_or_addr (branch_or_addr),
.rd_inst_buf (rd_inst_buf),
.link_pc_delay_pc (link_pc_delay_pc),
.pc (pc)
);
endmodule