/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: suctl.v,v 1.2 2002/12/06 21:14:14 doug Exp $

// suctl.v:  RSP scalar unit control with calls to VU control and issue logic
// std cell version

`timescale 1ns / 10ps

`include "sopcodes.vh"

module suctl (clk, reset_l, 
	halt, single_step, pc_in_wr_en, pc_data_in, 
	dma_dm_to_rd, dma_rd_to_dm, dma_imem_select, 
	branch_or_addr_unbuf, rd_inst, 
	sushvamt, sualu_cout, sualu_ovr, sualumsb, 
	suexasign, suexbsign, suonesdet_z, 
	su_inst, su_inst6, su_inst15,
	surf_ra, surf_rb,
	surdamux, surdbmux, suimmmux, suvulsoffsetmux, suimmlsmux,
	set_broke, break_inst_debug, 
	sualuamux, sualubmux, sushamux, sushbmux, 
	suslten, susltlt, sualuen, sualu, sualu_cin, sudrivels, 
	shiftamt, 
	su_ex_store, su_ex_load, vu_ex_store, vu_ex_load, 
	ex_mfc2, ex_mtc2, ex_cfc2, ex_su_byte_ls, ex_su_half_ls, ex_su_uns_ls, 
	chip_sel, rd_base, ls_drive_rd_base, rd_offset, rd_elem_num, 
	vu_rd_ld_dec_k, vu_rd_st_dec_k, 
	df_ls_drive_ls_in_wb, df_pass_thru, 
	surf_w, surf_wen, suwben, 
	vu_comp, vu_comp_k, vu_func, vu_elem, vs, vt,
	ex_ctc2_vc0, ex_ctc2_vc1, ex_ctc2_vc2, 
	vu_rd_store_type_k, rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k, 
	acc_wr_reg, acc_wr_en, 
	vu_ld_addr, vu_st_addr, vu_st_xpose_addr,
	store_xpose_rd, load_xpose_wb, 
	cp0_address, cp0_write, cp0_enable, ex_mfc0, imem_dma_cycle, 
	su_nop_debug, vu_nop_debug, 
	branch_or_addr, rd_inst_buf,
	link_pc_delay_pc, pc);

   input		clk;
   input		reset_l;
   input		halt;
   input		single_step;
   input		pc_in_wr_en;
   input	[11:2]	pc_data_in;
   input		dma_dm_to_rd;  
   input		dma_rd_to_dm;
   input		dma_imem_select;   
   input	[11:0]	branch_or_addr_unbuf;
   input  	[63:0]  rd_inst;	// imem out.  [63:32] is low order inst
   input	[4:0]	sushvamt;

						// EX stage from SU DP
   input		sualu_cout;
   input		sualu_ovr;
   input		sualumsb;
   input		suexasign;
   input		suexbsign;
   input 		suonesdet_z;

   						// RD stage to SU DP
   output	[31:0]	su_inst;
   output		su_inst6;		// buffered su_inst[6]
   output		su_inst15;		// buffered su_inst[15]
   output	[4:0]	surf_ra;		// encoded ra addr
   output	[4:0]	surf_rb;		// encoded rb addr
   output	[2:0]	surdamux;
   output	[2:0]	surdbmux;
   output	[1:0]	suimmmux;		// imm sxt, zxt, lui
   output	 	suimmlsmux;
   output	[2:0]	suvulsoffsetmux;	// vu l/s offset generation

						// RD stage to LS
   output	[3:0]	rd_base;
   output		ls_drive_rd_base;	// ls_data to rd_base bypass
   output	[3:0]	rd_offset;
   output	[3:0]	rd_elem_num;
   output      	[11:0]	vu_rd_ld_dec_k;		// type of vu ld data
   output      	[11:0]	vu_rd_st_dec_k;		// type of vu st data

						// RD stage to DMA
   output		set_broke;
						// RD stage to nowhere
   output		break_inst_debug;

   output		sualuamux;		// EX stage to SU DP
   output		sualubmux;
   output	[1:0]	sushamux;
   output	[1:0]	sushbmux;
   output		sudrivels;
   output		suslten;		// enable slt result
   output		susltlt;		// set, lt true
   output		sualuen;
   output	[4:0]	sualu;
   output		sualu_cin;
   output	[4:0]	shiftamt;
						// EX stage to LS
   output		su_ex_store;
   output		su_ex_load;
   output		vu_ex_store;
   output		vu_ex_load;
   output		ex_mfc2;
   output		ex_mtc2;
   output		ex_cfc2;
   output		ex_su_byte_ls;
   output		ex_su_half_ls;
   output		ex_su_uns_ls;
   output		chip_sel;		// dmem chip select

						// DF stage to LS
   output		df_ls_drive_ls_in_wb;
   output		df_pass_thru;		// df_inst is MT, MF, CT, CF

						// WB stage to SU DP

   output	[4:0]	surf_w;			// encoded rf write en
   output		surf_wen;		// rf write enable
   output		suwben;			// en wb_data into SU RFile


// Controls for VU

						// RD stage to VU
   output 		vu_comp;
   output 		vu_comp_k;
   output	[5:0]	vu_func;
   output	[3:0]	vu_elem;
   output	[4:0]   vs;          		// RD: reg num for vs read
   output	[4:0]   vt;          		// RD: reg num for vt read
   output		vu_rd_store_type_k;
   output		rd_cfvc0_k;
   output		rd_cfvc1_k;
   output		rd_cfvc2_k;
						// EX/ACC stage to VU
   output		ex_ctc2_vc0;
   output		ex_ctc2_vc1;
   output		ex_ctc2_vc2;
						// DF stage to VU
   output	[4:0]   acc_wr_reg;    	
   output		acc_wr_en;

   output	[4:0]	vu_ld_addr;
   output	[4:0]	vu_st_addr;
   output	[4:0]	vu_st_xpose_addr;
   output		store_xpose_rd;
   output		load_xpose_wb;

						// EX stage to CP0
   output	[3:0]	cp0_address;
   output		cp0_write;		// CTC0
   output		cp0_enable;		// !CTC0
   output		ex_mfc0;

   output		imem_dma_cycle;		// IF stage to BIST
   output		su_nop_debug;		// RD stage to nowhere
   output		vu_nop_debug;		// RD stage to nowhere
   output	[23:0]	link_pc_delay_pc;	// EX stage to LS
   output  	[11:2]  pc;
   output	[11:0]	branch_or_addr;
   output       [63:0]  rd_inst_buf;    // buffered instruction to rspbusses


   wire 		halting;
   wire			imem_dma_pif;
   wire		[31:0]	su_inst;		// RD stage
   wire		[31:0]	vu_inst;
   wire			adv_ir;
   wire			kill_re_non_vu;
   wire			kill_re;		// kill inst entering EX
   wire 		kill_su_issue;
   wire 		kill_vu_issue;
   wire			vu_reg_hazard_comp;
   wire			vu_reg_hazard_ls;

   wire		[10:6]	ex_su_inst;
   wire 		taken;

   suotherctl suotherctl (
// *** Maybe remaining pipeline stuff should move to issue: 
// kill*, adv_ir, *hazard*
	.clk			(clk),
	.reset_l		(reset_l),
	.halt			(halt),
	.single_step		(single_step),
	.su_inst		(su_inst),
	.kill_su_issue		(kill_su_issue),
	.kill_vu_issue		(kill_vu_issue),
	.vu_reg_hazard_comp	(vu_reg_hazard_comp),
	.vu_reg_hazard_ls	(vu_reg_hazard_ls),

	.dma_dm_to_rd		(dma_dm_to_rd),
	.dma_rd_to_dm		(dma_rd_to_dm),
	.dma_imem_select	(dma_imem_select),
	.sushvamt		(sushvamt),
	.vu_comp		(vu_comp),

	.sualu_cout		(sualu_cout),
	.sualu_ovr		(sualu_ovr),
	.sualumsb		(sualumsb),
	.suexasign		(suexasign),
	.suexbsign		(suexbsign),
	.suonesdet_z		(suonesdet_z),

	.halting		(halting),
	.imem_dma_pif		(imem_dma_pif),
	.adv_ir			(adv_ir),
	.kill_re_non_vu		(kill_re_non_vu),
	.kill_re		(kill_re),
	.ex_su_inst		(ex_su_inst),
	.taken			(taken),

	.surf_ra		(surf_ra),
	.surf_rb		(surf_rb),
	.surdamux		(surdamux),
	.surdbmux		(surdbmux),
	.suimmmux		(suimmmux),
	.suimmlsmux		(suimmlsmux),
	.suvulsoffsetmux	(suvulsoffsetmux),

	.rd_base		(rd_base),
	.ls_drive_rd_base	(ls_drive_rd_base),
	.rd_offset		(rd_offset),
	.rd_elem_num		(rd_elem_num),
	.vu_rd_ld_dec_k		(vu_rd_ld_dec_k),
	.vu_rd_st_dec_k		(vu_rd_st_dec_k),
	.set_broke		(set_broke),
	.break_inst_debug	(break_inst_debug),

	.sualuamux		(sualuamux),
	.sualubmux		(sualubmux),
	.sushamux		(sushamux),
	.sushbmux		(sushbmux),
	.sudrivels		(sudrivels),
	.suslten		(suslten),
	.susltlt		(susltlt),
	.sualuen		(sualuen),
	.sualu			(sualu),
	.sualu_cin		(sualu_cin),
	.shiftamt		(shiftamt),
	.su_ex_store		(su_ex_store),
	.su_ex_load		(su_ex_load),
	.vu_ex_store		(vu_ex_store),
	.vu_ex_load		(vu_ex_load),
	.ex_mfc2		(ex_mfc2),
	.ex_mtc2		(ex_mtc2),
	.ex_cfc2		(ex_cfc2),
	.ex_su_byte_ls		(ex_su_byte_ls),
	.ex_su_half_ls		(ex_su_half_ls),
	.ex_su_uns_ls		(ex_su_uns_ls),
	.chip_sel		(chip_sel),

	.df_ls_drive_ls_in_wb	(df_ls_drive_ls_in_wb),
	.df_pass_thru		(df_pass_thru),
	.surf_w			(surf_w),
	.surf_wen		(surf_wen),
	.suwben			(suwben),

	.vu_comp_k		(vu_comp_k),
	.cp0_address		(cp0_address),
	.cp0_write		(cp0_write),
	.cp0_enable		(cp0_enable),
	.ex_mfc0		(ex_mfc0),
	.imem_dma_cycle		(imem_dma_cycle)
   );

   suvuctl suvuctl (
	.clk			(clk),
	.reset_l		(reset_l),
	.su_inst		(su_inst),
	.vu_inst		(vu_inst),
	.kill_re_non_vu		(kill_re_non_vu),
	.kill_su_issue		(kill_su_issue),
	.kill_vu_issue		(kill_vu_issue),
	.elem_num		(ex_su_inst[10:7]),
	.vu_comp_k		(vu_comp_k),
	.vu_reg_hazard_comp	(vu_reg_hazard_comp),
	.vu_reg_hazard_ls	(vu_reg_hazard_ls),
	.vs			(vs),
	.vt			(vt),
	.vu_comp		(vu_comp),
	.vu_func		(vu_func),
	.vu_elem		(vu_elem),
	.vu_ld_addr		(vu_ld_addr),
	.vu_st_addr		(vu_st_addr),
	.vu_st_xpose_addr	(vu_st_xpose_addr),
	.ex_ctc2_vc0		(ex_ctc2_vc0),
	.ex_ctc2_vc1		(ex_ctc2_vc1),
	.ex_ctc2_vc2		(ex_ctc2_vc2),
	.vu_rd_store_type_k	(vu_rd_store_type_k),
	.rd_cfvc0_k		(rd_cfvc0_k),
	.rd_cfvc1_k		(rd_cfvc1_k),
	.rd_cfvc2_k		(rd_cfvc2_k),
	.acc_wr_reg		(acc_wr_reg),
	.acc_wr_en		(acc_wr_en),
	.load_xpose_wb		(load_xpose_wb)
    );

issue issue (
	.clk			(clk),
	.reset_l		(reset_l),
	.halt			(halt),
	.single_step		(single_step),
	.pc_in_wr_en		(pc_in_wr_en),
	.pc_data_in		(pc_data_in),
	.halting		(halting),
	.br_addr		(branch_or_addr_unbuf[11:2]),
	.rd_inst		(rd_inst),
	.set_broke		(set_broke),
	.imem_dma_pif		(imem_dma_pif),
	.taken			(taken),
	.adv_ir			(adv_ir),
	.kill_re		(kill_re),

	.su_inst		(su_inst),
	.vu_inst		(vu_inst),
	.su_nop_debug		(su_nop_debug),
	.vu_nop_debug		(vu_nop_debug),
	.link_pc_delay_pc	(link_pc_delay_pc),
	.pc			(pc),
	.kill_su_issue		(kill_su_issue),
	.kill_vu_issue		(kill_vu_issue),
	.store_xpose_rd		(store_xpose_rd)
    );

vt_decode vt_decode (
	.rd_inst		(rd_inst),
	.branch_or_addr_unbuf	(branch_or_addr_unbuf),
	.su_inst_6_unbuf	(su_inst[6]),
	.su_inst_15_unbuf	(su_inst[15]),
	.branch_or_addr		(branch_or_addr),
	.rd_inst_buf		(rd_inst_buf),
	.su_inst6		(su_inst6),
	.su_inst15		(su_inst15)
    );

endmodule