suvuctl.v
17.4 KB
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: suvuctl.v,v 1.5 2003/01/22 22:11:50 berndt Exp $
// suvuctl.v: RSP VU control generation and interlock detection
`timescale 1ns / 10ps
`include "sopcodes.vh"
module suvuctl (clk, reset_l, su_inst, vu_inst,
kill_re_non_vu, kill_su_issue, kill_vu_issue,
vu_reg_hazard_comp, vu_reg_hazard_ls,
vs, vt, vu_comp, vu_func, vu_elem,
elem_num, vu_comp_k,
vu_ld_addr, vu_st_addr, vu_st_xpose_addr,
ex_ctc2_vc0, ex_ctc2_vc1, ex_ctc2_vc2,
vu_rd_store_type_k, rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k,
acc_wr_reg, acc_wr_en, load_xpose_wb);
input clk;
input reset_l;
input [31:0] su_inst;
input [31:0] vu_inst; // RD stage
input kill_re_non_vu;
input kill_su_issue;
input kill_vu_issue;
input [3:0] elem_num;
input vu_comp_k;
// RD stage to SU
output vu_reg_hazard_comp;
output vu_reg_hazard_ls;
// RD stage to VU
output [4:0] vs;
output [4:0] vt;
output vu_comp;
output [5:0] vu_func;
output [3:0] vu_elem;
output [4:0] vu_ld_addr;
output [4:0] vu_st_addr;
output [4:0] vu_st_xpose_addr;
output vu_rd_store_type_k;
output rd_cfvc0_k;
output rd_cfvc1_k;
output rd_cfvc2_k;
// EX/ACC stage to VU
output ex_ctc2_vc0;
output ex_ctc2_vc1;
output ex_ctc2_vc2;
// DF stage to VU
output [4:0] acc_wr_reg;
output acc_wr_en;
// WB stage to VU
output load_xpose_wb;
wire [31:0] su_inst;
wire [31:0] vu_inst;
wire [5:0] opc;
wire [5:0] func;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire rd_mfc2;
wire vu_rd_store_type;
wire store_xpose_rd;
wire [4:0] rd_st_src;
// VU Pipe Signals:
wire [4:0] vd;
wire [4:0] vu_ld_reg;
wire [4:0] vu_st_reg;
wire [4:0] vu_mf_reg;
wire mul_ld_en;
wire acc_ld_en;
wire wbv_ld_en;
wire mul_ld_xpose;
wire acc_ld_xpose;
wire [4:0] mul_ld_reg;
wire [4:0] acc_ld_reg;
wire [4:0] wbv_ld_reg;
wire mul_wr_en;
wire wbv_wr_en;
wire [4:0] mul_wr_reg;
wire [4:0] acc_ld_dest;
wire [2:0] df_elem_num;
wire ctc2_vc0;
wire ctc2_vc1;
wire ctc2_vc2;
wire ctc2_vc0_k;
wire ctc2_vc1_k;
wire ctc2_vc2_k;
wire rd_cfvc0;
wire rd_cfvc1;
wire rd_cfvc2;
wire ld_xpose;
wire ld_xpose_k;
wire st_xpose;
wire use_vs;
wire use_vt;
wire use_mf_reg;
wire use_st_reg;
wire vu_rd_ld_en;
wire vu_rd_ld_en_k;
//
// RD stage signals: instruction decode, bypasses
//
assign opc = su_inst[31:26];
assign func = su_inst[5:0];
assign rs = su_inst[25:21];
assign rt = su_inst[20:16];
assign rd = su_inst[15:11];
assign rd_mfc2 = (opc[5:4]==2'b01) && (opc[1]==1'b1) &&
(rs[4]==0) && (rs[2:1]==2'b00);
assign vu_comp = (vu_inst[31:25] == 7'b0100101) && // nop
!((vu_func == 6'b110111) || (vu_func == 6'b111111));
assign vu_func = vu_inst[5:0];
assign vu_elem = vu_inst[24:21];
assign vd = vu_inst[10:6];
assign use_vs =
vu_comp && !((vu_func[5:4] == 2'b11) || // !div-class
(vu_func[5:0] == 6'b001011) || // !macq
(vu_func[5:0] == 6'b011100) || // !vsum
(vu_func[5:0] == 6'b000010) || // !rnd
(vu_func[5:0] == 6'b001010) || // !rnd
(vu_func[5:2] == 4'b0111)); // !sar
assign use_vt =
vu_comp && !((vu_func[5:0] == 6'b001011) || // !macq
(vu_func[5:0] == 6'b011100) || // !vsum
(vu_func[5:2] == 4'b1111) || // !extract
(vu_func[5:2] == 4'b0111)); // !sar
assign use_mf_reg = (opc=='h12) && (rs=='h00); // `COP2 && `MFC;
assign use_st_reg = (opc=='h3a); // SWC2
// *** ld_reg and st_reg may be xpose.
wire wb_ld_en;
wire [4:0] wb_ld_reg;
wire wb_ld_xpose;
wire wb_wr_en;
wire [4:0] wb_wr_reg;
assign vu_reg_hazard_ls =
(use_mf_reg && (rd[4:3] == mul_ld_reg[4:3]) && mul_ld_xpose) || // mfc2
(use_mf_reg && (rd[4:3] == acc_ld_reg[4:3]) && acc_ld_xpose) || // mfc2
(use_mf_reg && (rd[4:3] == wb_ld_reg[4:3]) && wb_ld_xpose) || // mfc2
(use_mf_reg && (rd == mul_ld_reg) && mul_ld_en) || // mfc2
(use_mf_reg && (rd == acc_ld_reg) && acc_ld_en) || // mfc2
(use_mf_reg && (rd == wb_ld_reg) && wb_ld_en) || // mfc2
(use_mf_reg && (rd == mul_wr_reg) && mul_wr_en) || // mfc2
(use_mf_reg && (rd == acc_wr_reg) && acc_wr_en) || // mfc2
(use_mf_reg && (rd == wb_wr_reg) && wb_wr_en) || // mfc2
(use_st_reg && (rt[4:3] == mul_ld_reg[4:3]) && mul_ld_en && (store_xpose_rd || mul_ld_xpose)) || // store and store or load xpose
(use_st_reg && (rt[4:3] == acc_ld_reg[4:3]) && acc_ld_en && (store_xpose_rd || acc_ld_xpose)) || // store and store or load xpose
(use_st_reg && (rt[4:3] == wb_ld_reg[4:3]) && wb_ld_en && (store_xpose_rd || wb_ld_xpose)) || // store and store or load xpose
(st_xpose && (rt[4:3] == mul_wr_reg[4:3]) && mul_wr_en) || // store xpose
(st_xpose && (rt[4:3] == acc_wr_reg[4:3]) && acc_wr_en) || // store xpose
(st_xpose && (rt[4:3] == wb_wr_reg[4:3]) && wb_wr_en) || // store xpose
(use_st_reg && (rt == mul_ld_reg) && mul_ld_en) || // store
(use_st_reg && (rt == acc_ld_reg) && acc_ld_en) || // store
(use_st_reg && (rt == wb_ld_reg) && wb_ld_en) || // store
(use_st_reg && (rt == mul_wr_reg) && mul_wr_en) || // store
(use_st_reg && (rt == acc_wr_reg && acc_wr_en)) || // store
(use_st_reg && (rt == wb_wr_reg) && wb_wr_en); // store
assign vu_reg_hazard_comp =
(use_vs && (vs[4:3] == mul_ld_reg[4:3]) && mul_ld_xpose) ||
(use_vs && (vs[4:3] == acc_ld_reg[4:3]) && acc_ld_xpose) ||
(use_vs && (vs[4:3] == wb_ld_reg[4:3]) && wb_ld_xpose) ||
(use_vs && (vs == mul_ld_reg) && mul_ld_en) ||
(use_vs && (vs == acc_ld_reg) && acc_ld_en) ||
(use_vs && (vs == wb_ld_reg) && wb_ld_en) ||
(use_vs && (vs == mul_wr_reg) && mul_wr_en) ||
(use_vs && (vs == acc_wr_reg) && acc_wr_en) ||
(use_vs && (vs == wb_wr_reg) && wb_wr_en) ||
(use_vt && (vt[4:3] == mul_ld_reg[4:3]) && mul_ld_xpose) ||
(use_vt && (vt[4:3] == acc_ld_reg[4:3]) && acc_ld_xpose) ||
(use_vt && (vt[4:3] == wb_ld_reg[4:3]) && wb_ld_xpose) ||
(use_vt && (vt == mul_ld_reg) && mul_ld_en) ||
(use_vt && (vt == acc_ld_reg) && acc_ld_en) ||
(use_vt && (vt == wb_ld_reg) && wb_ld_en) ||
(use_vt && (vt == mul_wr_reg) && mul_wr_en) ||
(use_vt && (vt == acc_wr_reg) && acc_wr_en) ||
(use_vt && (vt == wb_wr_reg) && wb_wr_en);
assign ld_xpose = `LWC2 && (su_inst[14:11]==4'b1011);
assign st_xpose = (su_inst[31:26]==6'b111010) && (su_inst[14:11]==4'b1011);
assign store_xpose_rd = su_inst[31] && (su_inst[14:11]==4'b1011);
assign rd_cfvc0 = `COP2 && `CFC && (rd[1:0]==2'b00);
assign ctc2_vc0 = `COP2 && `CTC && (rd[1:0]==2'b00);
assign rd_cfvc1 = `COP2 && `CFC && (rd[1:0]==2'b01);
assign ctc2_vc1 = `COP2 && `CTC && (rd[1:0]==2'b01);
assign rd_cfvc2 = `COP2 && `CFC && (rd[1:0]==2'b10);
assign ctc2_vc2 = `COP2 && `CTC && (rd[1:0]==2'b10);
assign vu_rd_ld_en = `LWC2 || (`COP2 && `MTC);
assign vu_ld_reg = `LWC2 ? rt : rd;
assign vu_st_reg = rt;
assign vu_mf_reg = rd;
// VU control register hazards:
// There aren't any involving outstanding writes, because the control
// registers are both read and written (by both computation instructions
// and CTC2/CFC2) in the EX stage. The only hazards involve dual issuing
// instructions both of which want to access the same control register.
// This is handled in the issue logic.
// Kill: optionally kill EX stage signals
assign ld_xpose_k = ld_xpose && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign vu_rd_ld_en_k = vu_rd_ld_en && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign ctc2_vc0_k = ctc2_vc0 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign ctc2_vc1_k = ctc2_vc1 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign ctc2_vc2_k = ctc2_vc2 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
spasdff_1_0 su_re_vulden_ff(mul_ld_en, vu_rd_ld_en_k, clk, reset_l);
spasdff_5_0 su_re_vu_ld_reg_ff(mul_ld_reg, vu_ld_reg, clk, reset_l);
spasdff_1_0 su_re_vu_xp_ff(mul_ld_xpose, ld_xpose_k, clk, reset_l);
spasdff_1_0 su_re_vuwren_ff(mul_wr_en,vu_comp_k,clk,reset_l);
spasdff_5_0 su_re_vu_wr_reg_ff(mul_wr_reg, vd, clk, reset_l);
spasdff_1_0 su_re_vu_ct0_ff(ex_ctc2_vc0, ctc2_vc0_k, clk, reset_l);
spasdff_1_0 su_re_vu_ct1_ff(ex_ctc2_vc1, ctc2_vc1_k, clk, reset_l);
spasdff_1_0 su_re_vu_ct2_ff(ex_ctc2_vc2, ctc2_vc2_k, clk, reset_l);
spasdff_1_0 su_ed_vu_ld_en_ff(acc_ld_en, mul_ld_en, clk, reset_l);
spasdff_5_0 su_ed_vu_ld_reg_ff(acc_ld_reg, mul_ld_reg, clk, reset_l);
spasdff_1_0 su_ed_vu_xp_en_ff(acc_ld_xpose, mul_ld_xpose, clk, reset_l);
spasdff_1_0 su_ed_vu_wr_en_ff(acc_wr_en, mul_wr_en, clk, reset_l);
spasdff_5_0 su_ed_vu_wr_reg_ff(acc_wr_reg, mul_wr_reg, clk, reset_l);
spasdff_3_0 su_ed_elem_ff(df_elem_num, elem_num[3:1], clk,reset_l);
spasdff_1_0 su_dw_vu_ld_en_ff(wb_ld_en, acc_ld_en, clk, reset_l);
spasdff_5_0 su_dw_vu_ld_reg_ff(wb_ld_reg, acc_ld_reg, clk, reset_l);
spasdff_1_0 su_dw_vu_xp_en_ff(wb_ld_xpose, acc_ld_xpose, clk, reset_l);
spasdff_1_0 su_dw_vu_wr_en_ff(wb_wr_en, acc_wr_en, clk, reset_l);
spasdff_5_0 su_dw_vu_wr_reg_ff(wb_wr_reg, acc_wr_reg, clk, reset_l);
assign load_xpose_wb = wb_ld_xpose;
/* ********************************************************************** */
// VU Control Generation:
assign vu_rd_store_type = `SWC2 || (`COP2 && `MFC);
/* assign vu_rd_storecfc2 = `SWC2 || (`COP2 && (`MFC || `CFC)); */
function [4:0] rd_st_src_mux;
input [1:0] rd_st_src_sel;
input [4:0] in_a, in_b, in_c;
begin
case (1'b1) //
rd_st_src_sel[0] : rd_st_src_mux = in_a;
rd_st_src_sel[1] : rd_st_src_mux = in_b;
default : rd_st_src_mux = in_c;
endcase
end
endfunction
wire [1:0] rd_st_src_sel;
assign rd_st_src_sel[0] = rd_mfc2;
assign rd_st_src_sel[1] = !rd_mfc2 && st_xpose;
assign rd_st_src = rd_st_src_mux(rd_st_src_sel,
su_inst[15:11], {su_inst[20:19], su_inst[10:8]}, su_inst[20:16]);
assign rd_cfvc0_k = rd_cfvc0 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign rd_cfvc1_k = rd_cfvc1 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign rd_cfvc2_k = rd_cfvc2 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
assign vu_rd_store_type_k = vu_rd_store_type && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
/*
assign vu_rd_storecfc2_k = vu_rd_storecfc2 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
*/
wire [4:0] vu_st_addr;
wire [4:0] vu_st_xpose_addr;
assign vu_ld_addr =
acc_ld_xpose ? {acc_ld_reg[4:3], df_elem_num} : acc_ld_reg;
assign vu_st_addr = su_inst[29]? su_inst[20:16] : su_inst[15:11];
assign vu_st_xpose_addr = {su_inst[20:19], su_inst[10:8]};
assign vs = vu_inst[15:11];
assign vt = vu_inst[20:16];
endmodule
module new_rf_decode (dec_addr, enc_addr);
input [4:0] enc_addr;
output [31:0] dec_addr;
wire [4:0] enc_addr_buf_l;
wire [4:0] a_h_a;
wire [4:0] a_h_b;
wire [4:0] a_l_a;
wire [4:0] a_l_b;
in01d7 dec_buf_0 (.i(enc_addr[0]), .zn(enc_addr_buf_l[0]));
in01d7 dec_buf_1 (.i(enc_addr[1]), .zn(enc_addr_buf_l[1]));
in01d7 dec_buf_2 (.i(enc_addr[2]), .zn(enc_addr_buf_l[2]));
in01d7 dec_buf_3 (.i(enc_addr[3]), .zn(enc_addr_buf_l[3]));
in01d7 dec_buf_4 (.i(enc_addr[4]), .zn(enc_addr_buf_l[4]));
ni01d7 dec_bufh_a_0 (.i(enc_addr_buf_l[0]), .z(a_l_a[0]));
ni01d7 dec_bufh_a_1 (.i(enc_addr_buf_l[1]), .z(a_l_a[1]));
ni01d7 dec_bufh_a_2 (.i(enc_addr_buf_l[2]), .z(a_l_a[2]));
ni01d7 dec_bufh_a_3 (.i(enc_addr_buf_l[3]), .z(a_l_a[3]));
ni01d7 dec_bufh_a_4 (.i(enc_addr_buf_l[4]), .z(a_l_a[4]));
in01d7 dec_bufl_a_0 (.i(enc_addr_buf_l[0]), .zn(a_h_a[0]));
in01d7 dec_bufl_a_1 (.i(enc_addr_buf_l[1]), .zn(a_h_a[1]));
in01d7 dec_bufl_a_2 (.i(enc_addr_buf_l[2]), .zn(a_h_a[2]));
in01d7 dec_bufl_a_3 (.i(enc_addr_buf_l[3]), .zn(a_h_a[3]));
in01d7 dec_bufl_a_4 (.i(enc_addr_buf_l[4]), .zn(a_h_a[4]));
ni01d7 dec_bufh_b_0 (.i(enc_addr_buf_l[0]), .z(a_l_b[0]));
ni01d7 dec_bufh_b_1 (.i(enc_addr_buf_l[1]), .z(a_l_b[1]));
ni01d7 dec_bufh_b_2 (.i(enc_addr_buf_l[2]), .z(a_l_b[2]));
ni01d7 dec_bufh_b_3 (.i(enc_addr_buf_l[3]), .z(a_l_b[3]));
ni01d7 dec_bufh_b_4 (.i(enc_addr_buf_l[4]), .z(a_l_b[4]));
in01d7 dec_bufl_b_0 (.i(enc_addr_buf_l[0]), .zn(a_h_b[0]));
in01d7 dec_bufl_b_1 (.i(enc_addr_buf_l[1]), .zn(a_h_b[1]));
in01d7 dec_bufl_b_2 (.i(enc_addr_buf_l[2]), .zn(a_h_b[2]));
in01d7 dec_bufl_b_3 (.i(enc_addr_buf_l[3]), .zn(a_h_b[3]));
in01d7 dec_bufl_b_4 (.i(enc_addr_buf_l[4]), .zn(a_h_b[4]));
nr05d2 dec_00 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_l_a[2]), .a4(a_l_a[1]), .a5(a_l_a[0]), .zn(dec_addr[ 0]));
nr05d2 dec_01 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_l_a[2]), .a4(a_l_a[1]), .a5(a_h_a[0]), .zn(dec_addr[ 1]));
nr05d2 dec_02 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_l_a[2]), .a4(a_h_a[1]), .a5(a_l_a[0]), .zn(dec_addr[ 2]));
nr05d2 dec_03 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_l_a[2]), .a4(a_h_a[1]), .a5(a_h_a[0]), .zn(dec_addr[ 3]));
nr05d2 dec_04 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_h_a[2]), .a4(a_l_a[1]), .a5(a_l_a[0]), .zn(dec_addr[ 4]));
nr05d2 dec_05 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_h_a[2]), .a4(a_l_a[1]), .a5(a_h_a[0]), .zn(dec_addr[ 5]));
nr05d2 dec_06 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_h_a[2]), .a4(a_h_a[1]), .a5(a_l_a[0]), .zn(dec_addr[ 6]));
nr05d2 dec_07 (.a1(a_l_a[4]), .a2(a_l_a[3]), .a3(a_h_a[2]), .a4(a_h_a[1]), .a5(a_h_a[0]), .zn(dec_addr[ 7]));
nr05d2 dec_08 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_l_a[2]), .a4(a_l_a[1]), .a5(a_l_a[0]), .zn(dec_addr[ 8]));
nr05d2 dec_09 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_l_a[2]), .a4(a_l_a[1]), .a5(a_h_a[0]), .zn(dec_addr[ 9]));
nr05d2 dec_10 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_l_a[2]), .a4(a_h_a[1]), .a5(a_l_a[0]), .zn(dec_addr[10]));
nr05d2 dec_11 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_l_a[2]), .a4(a_h_a[1]), .a5(a_h_a[0]), .zn(dec_addr[11]));
nr05d2 dec_12 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_h_a[2]), .a4(a_l_a[1]), .a5(a_l_a[0]), .zn(dec_addr[12]));
nr05d2 dec_13 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_h_a[2]), .a4(a_l_a[1]), .a5(a_h_a[0]), .zn(dec_addr[13]));
nr05d2 dec_14 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_h_a[2]), .a4(a_h_a[1]), .a5(a_l_a[0]), .zn(dec_addr[14]));
nr05d2 dec_15 (.a1(a_l_b[4]), .a2(a_h_a[3]), .a3(a_h_a[2]), .a4(a_h_a[1]), .a5(a_h_a[0]), .zn(dec_addr[15]));
nr05d2 dec_16 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_l_b[2]), .a4(a_l_b[1]), .a5(a_l_b[0]), .zn(dec_addr[16]));
nr05d2 dec_17 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_l_b[2]), .a4(a_l_b[1]), .a5(a_h_b[0]), .zn(dec_addr[17]));
nr05d2 dec_18 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_l_b[2]), .a4(a_h_b[1]), .a5(a_l_b[0]), .zn(dec_addr[18]));
nr05d2 dec_19 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_l_b[2]), .a4(a_h_b[1]), .a5(a_h_b[0]), .zn(dec_addr[19]));
nr05d2 dec_20 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_h_b[2]), .a4(a_l_b[1]), .a5(a_l_b[0]), .zn(dec_addr[20]));
nr05d2 dec_21 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_h_b[2]), .a4(a_l_b[1]), .a5(a_h_b[0]), .zn(dec_addr[21]));
nr05d2 dec_22 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_h_b[2]), .a4(a_h_b[1]), .a5(a_l_b[0]), .zn(dec_addr[22]));
nr05d2 dec_23 (.a1(a_h_a[4]), .a2(a_l_b[3]), .a3(a_h_b[2]), .a4(a_h_b[1]), .a5(a_h_b[0]), .zn(dec_addr[23]));
nr05d2 dec_24 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_l_b[2]), .a4(a_l_b[1]), .a5(a_l_b[0]), .zn(dec_addr[24]));
nr05d2 dec_25 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_l_b[2]), .a4(a_l_b[1]), .a5(a_h_b[0]), .zn(dec_addr[25]));
nr05d2 dec_26 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_l_b[2]), .a4(a_h_b[1]), .a5(a_l_b[0]), .zn(dec_addr[26]));
nr05d2 dec_27 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_l_b[2]), .a4(a_h_b[1]), .a5(a_h_b[0]), .zn(dec_addr[27]));
nr05d2 dec_28 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_h_b[2]), .a4(a_l_b[1]), .a5(a_l_b[0]), .zn(dec_addr[28]));
nr05d2 dec_29 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_h_b[2]), .a4(a_l_b[1]), .a5(a_h_b[0]), .zn(dec_addr[29]));
nr05d2 dec_30 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_h_b[2]), .a4(a_h_b[1]), .a5(a_l_b[0]), .zn(dec_addr[30]));
nr05d2 dec_31 (.a1(a_h_b[4]), .a2(a_h_b[3]), .a3(a_h_b[2]), .a4(a_h_b[1]), .a5(a_h_b[0]), .zn(dec_addr[31]));
endmodule