tm.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: tm.v,v 1.7 2003/01/23 21:05:29 berndt Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tm
// description: Texture Memory Unit
//
// designer: Tony DeLaurier
// date: 7/11/94
//
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps //1unit = 0.01ns
module tm (clk, start_gclk, reset_l,
tlut_en, tlut_type, adrs_bnk0l,
adrs_bnk1l, adrs_bnk2l, adrs_bnk3l, adrs_bnk0h, adrs_bnk1h, adrs_bnk2h,
adrs_bnk3h, adrs_a, adrs_b_ba, adrs_c, adrs_d_ba, adrs_b_rg, adrs_d_rg,
swap_rg, swap_ba, tile_tex_type, tile_tex_size, palette, odd_t, a_three,
a_twelve, clr_ind_a, clr_ind_b, clr_ind_c, clr_ind_d, red_a,
green_a, blue_a, alpha_a, red_b, green_b, blue_b, alpha_b, red_c, green_c,
blue_c, alpha_c, red_d, green_d, blue_d, alpha_d,
copy_load, tm_copy_load, load_dv
);
input clk;
input start_gclk;
input reset_l; // reset (active low)
// attribute data
input tlut_en; // enable texture lookup table
input tlut_type; // tlut type
// from texture coordinate unit
input [7:0] adrs_bnk0l; // sorted address to low bank 0
input [7:0] adrs_bnk1l; // sorted address to low bank 1
input [7:0] adrs_bnk2l; // sorted address to low bank 2
input [7:0] adrs_bnk3l; // sorted address to low bank 3
input [7:0] adrs_bnk0h; // sorted address to high bank 0
input [7:0] adrs_bnk1h; // sorted address to high bank 1
input [7:0] adrs_bnk2h; // sorted address to high bank 2
input [7:0] adrs_bnk3h; // sorted address to high bank 3
input [4:0] adrs_a; // address of texel a <12,3:0>
input [4:0] adrs_b_ba; // address of texel b (ba banks) <12,3:0>
input [4:0] adrs_c; // address of texel c <12,3:0>
input [4:0] adrs_d_ba; // address of texel d (ba banks) <12,3:0>
input [4:0] adrs_b_rg; // address of texel b (rg banks) <12,3:0>
input [4:0] adrs_d_rg; // address of texel d (rg banks) <12,3:0>
input swap_rg; // swap texels (RG)
input swap_ba; // swap texels (BA)
input [2:0] tile_tex_type; // tile texel type
input [1:0] tile_tex_size; // tile texel size
input [3:0] palette; // palette for 4-bit color index
input odd_t; // odd line
input a_three; // address a[3] before interleave
input a_twelve; // address a[12]
// to texture coordinate unit
output [7:0] clr_ind_a; // color index texel a
output [7:0] clr_ind_b; // color index texel b
output [7:0] clr_ind_c; // color index texel c
output [7:0] clr_ind_d; // color index texel d
// to texture filter unit
output [8:0] red_a; // texel a, red / u channel
output [8:0] green_a; // texel a, green / v channel
output [8:0] blue_a; // texel a, blue / y channel
output [8:0] alpha_a; // texel a, alpha / y channel
output [8:0] red_b; // texel b, red / u channel
output [8:0] green_b; // texel b, green / v channel
output [8:0] blue_b; // texel b, blue / y channel
output [8:0] alpha_b; // texel b, alpha / y channel
output [8:0] red_c; // texel c, red / u channel
output [8:0] green_c; // texel c, green / v channel
output [8:0] blue_c; // texel c, blue / y channel
output [8:0] alpha_c; // texel c, alpha / y channel
output [8:0] red_d; // texel d, red / u channel
output [8:0] green_d; // texel d, green / v channel
output [8:0] blue_d; // texel d, blue / y channel
output [8:0] alpha_d; // texel d, alpha / y channel
// to / from memspan unit
input [63:0] copy_load; // bidirectional copy / load bus
output [63:0] tm_copy_load; // bidirectional copy / load bus
input load_dv; // valid load data on copy_load bus
// wires
wire [63:0] di_high; // data_in to high banks
wire [63:0] di_low; // data_in to low banks
wire web01_low; // write enable banks 0,1 (low half)
wire web23_low; // write enable banks 2,3 (low half)
wire web01_high; // write enable banks 0,1 (high half)
wire web23_high; // write enable banks 2,3 (high half)
wire [15:0] dout_bnk0l; // data out bank0 - low half
wire [15:0] dout_bnk1l; // data out bank1 - low half
wire [15:0] dout_bnk2l; // data out bank2 - low half
wire [15:0] dout_bnk3l; // data out bank3 - low half
wire [15:0] dout_bnk0h; // data out bank0 - high half
wire [15:0] dout_bnk1h; // data out bank1 - high half
wire [15:0] dout_bnk2h; // data out bank2 - high half
wire [15:0] dout_bnk3h; // data out bank3 - high half
wire [63:0] copy_bus; // copy bus
wire [7:0] ram0_addr; // address to ram (bnk0)
wire [7:0] ram1_addr; // address to ram (bnk1)
wire [7:0] ram2_addr; // address to ram (bnk2)
wire [7:0] ram3_addr; // address to ram (bnk3)
wire [7:0] ram4_addr; // address to ram (bnk4)
wire [7:0] ram5_addr; // address to ram (bnk5)
wire [7:0] ram6_addr; // address to ram (bnk6)
wire [7:0] ram7_addr; // address to ram (bnk7)
wire [15:0] ram0_din; // data_in to ram (bnk0)
wire [15:0] ram1_din; // data_in to ram (bnk1)
wire [15:0] ram2_din; // data_in to ram (bnk2)
wire [15:0] ram3_din; // data_in to ram (bnk3)
wire [15:0] ram4_din; // data_in to ram (bnk4)
wire [15:0] ram5_din; // data_in to ram (bnk5)
wire [15:0] ram6_din; // data_in to ram (bnk6)
wire [15:0] ram7_din; // data_in to ram (bnk7)
wire ram0_web; // web to ram (bnk0)
wire ram1_web; // web to ram (bnk1)
wire ram2_web; // web to ram (bnk2)
wire ram3_web; // web to ram (bnk3)
wire ram4_web; // web to ram (bnk4)
wire ram5_web; // web to ram (bnk5)
wire ram6_web; // web to ram (bnk6)
wire ram7_web; // web to ram (bnk7)
wire [15:0] sort_tex_a_low; // sorted texel a (low half)
wire [15:0] sort_tex_b_low; // sorted texel b (low half)
wire [15:0] sort_tex_c_low; // sorted texel c (low half)
wire [15:0] sort_tex_d_low; // sorted texel d (low half)
wire [15:0] sort_tex_a_high; // sorted texel a (high half)
wire [15:0] sort_tex_b_high; // sorted texel b (high half)
wire [15:0] sort_tex_c_high; // sorted texel c (high half)
wire [15:0] sort_tex_d_high; // sorted texel d (high half)
wire [4:0] swap_a_low; // swapped address a (low half)
wire [4:0] swap_b_low; // swapped address b (low half)
wire [4:0] swap_c_low; // swapped address c (low half)
wire [4:0] swap_d_low; // swapped address d (low half)
wire [4:0] swap_a_high; // swapped address a (high half)
wire [4:0] swap_b_high; // swapped address b (high half)
wire [4:0] swap_c_high; // swapped address c (high half)
wire [4:0] swap_d_high; // swapped address d (high half)
wire [1:0] tile_tex_size_2d; // tile texel size delayed 2
wire [3:0] palette_1d; // palette delayed 1
wire tlut_en_2d; // tlut_en delayed 2
// instance the tmem load interface
tm_load load (.clk(clk), .start_gclk(start_gclk), .copy_load(copy_load), .load_dv(load_dv),
.tile_tex_type(tile_tex_type), .tile_tex_size(tile_tex_size),
.odd_t(odd_t), .a_three(a_three), .a_twelve(a_twelve),
.di_high(di_high), .di_low(di_low), .web01_low(web01_low),
.web23_low(web23_low), .web01_high(web01_high),
.web23_high(web23_high));
// JCM Replace bist module with wires connecting addresses, data in,
// and write enables.
assign ram0_addr = adrs_bnk0l;
assign ram1_addr = adrs_bnk1l;
assign ram2_addr = adrs_bnk2l;
assign ram3_addr = adrs_bnk3l;
assign ram4_addr = adrs_bnk0h;
assign ram5_addr = adrs_bnk1h;
assign ram6_addr = adrs_bnk2h;
assign ram7_addr = adrs_bnk3h;
assign ram0_din = di_low[63:48];
assign ram1_din = di_low[47:32];
assign ram2_din = di_low[31:16];
assign ram3_din = di_low[15:0];
assign ram4_din = di_high[63:48];
assign ram5_din = di_high[47:32];
assign ram6_din = di_high[31:16];
assign ram7_din = di_high[15:0];
assign ram0_web = web01_low;
assign ram1_web = web01_low;
assign ram2_web = web23_low;
assign ram3_web = web23_low;
assign ram4_web = web01_high;
assign ram5_web = web01_high;
assign ram6_web = web23_high;
assign ram7_web = web23_high;
// instance the 8 texture memory banks
tm_half low_half (.clk(clk), .start_gclk(start_gclk), .ram0_addr(ram0_addr),
.ram1_addr(ram1_addr), .ram2_addr(ram2_addr),
.ram3_addr(ram3_addr), .ram0_web(ram0_web),
.ram1_web(ram1_web), .ram2_web(ram2_web),
.ram3_web(ram3_web), .ram0_din(ram0_din),
.ram1_din(ram1_din), .ram2_din(ram2_din),
.ram3_din(ram3_din), .ram0_dout(dout_bnk0l),
.ram1_dout(dout_bnk1l), .ram2_dout(dout_bnk2l),
.ram3_dout(dout_bnk3l));
tm_half hi_half (.clk(clk), .start_gclk(start_gclk), .ram0_addr(ram4_addr),
.ram1_addr(ram5_addr), .ram2_addr(ram6_addr),
.ram3_addr(ram7_addr), .ram0_web(ram4_web),
.ram1_web(ram5_web), .ram2_web(ram6_web),
.ram3_web(ram7_web), .ram0_din(ram4_din),
.ram1_din(ram5_din), .ram2_din(ram6_din),
.ram3_din(ram7_din), .ram0_dout(dout_bnk0h),
.ram1_dout(dout_bnk1h), .ram2_dout(dout_bnk2h),
.ram3_dout(dout_bnk3h));
// instance the texture memory mux modules
tm_mux1 mux1 (.clk(clk), .start_gclk(start_gclk), .swap_rg(swap_rg), .swap_ba(swap_ba),
.adrs_a(adrs_a), .adrs_b_ba(adrs_b_ba), .adrs_c(adrs_c),
.adrs_d_ba(adrs_d_ba), .adrs_b_rg(adrs_b_rg),
.adrs_d_rg(adrs_d_rg), .dout_bnk0l(dout_bnk0l),
.dout_bnk1l(dout_bnk1l), .dout_bnk2l(dout_bnk2l),
.dout_bnk3l(dout_bnk3l), .dout_bnk0h(dout_bnk0h),
.dout_bnk1h(dout_bnk1h), .dout_bnk2h(dout_bnk2h),
.dout_bnk3h(dout_bnk3h), .tlut_en(tlut_en),
.tile_tex_size(tile_tex_size), .palette(palette),
//
.sort_tex_a_low_buf(sort_tex_a_low), .sort_tex_b_low_buf(sort_tex_b_low),
.sort_tex_c_low_buf(sort_tex_c_low), .sort_tex_d_low_buf(sort_tex_d_low),
.sort_tex_a_high_buf(sort_tex_a_high), .sort_tex_b_high_buf(sort_tex_b_high),
.sort_tex_c_high_buf(sort_tex_c_high), .sort_tex_d_high_buf(sort_tex_d_high),
.swap_a_low_buf(swap_a_low), .swap_b_low_buf(swap_b_low),
.swap_c_low_buf(swap_c_low), .swap_d_low_buf(swap_d_low),
.swap_a_high_buf(swap_a_high), .swap_b_high_buf(swap_b_high),
.swap_c_high_buf(swap_c_high), .swap_d_high_buf(swap_d_high),
.clr_ind_a_buf(clr_ind_a), .clr_ind_b_buf(clr_ind_b),
.clr_ind_c_buf(clr_ind_c), .clr_ind_d_buf(clr_ind_d),
.tile_tex_size_2d_buf(tile_tex_size_2d), .palette_1d_buf(palette_1d),
.tlut_en_2d_buf(tlut_en_2d));
tm_mux2 mux2 (.clk(clk), .start_gclk(start_gclk), .tlut_type(tlut_type), .tile_tex_type(tile_tex_type),
.tile_tex_size_2d(tile_tex_size_2d), .palette_1d(palette_1d),
.tlut_en_2d(tlut_en_2d), .swap_a_low(swap_a_low), .swap_b_low(swap_b_low),
.swap_c_low(swap_c_low), .swap_d_low(swap_d_low), .swap_a_high(swap_a_high),
.swap_b_high(swap_b_high), .swap_c_high(swap_c_high), .swap_d_high(swap_d_high),
.sort_tex_a_low(sort_tex_a_low), .sort_tex_b_low(sort_tex_b_low),
.sort_tex_c_low(sort_tex_c_low), .sort_tex_d_low(sort_tex_d_low),
.sort_tex_a_high(sort_tex_a_high), .sort_tex_b_high(sort_tex_b_high),
.sort_tex_c_high(sort_tex_c_high),
.sort_tex_d_high(sort_tex_d_high), .copy_bus(copy_bus),
.red_a(red_a), .red_b(red_b), .red_c(red_c),
.red_d(red_d), .green_a(green_a), .green_b(green_b),
.green_c(green_c), .green_d(green_d), .blue_a(blue_a),
.blue_b(blue_b), .blue_c(blue_c), .blue_d(blue_d),
.alpha_a(alpha_a), .alpha_b(alpha_b),
.alpha_c(alpha_c), .alpha_d(alpha_d));
// copy_load bus
// tm_tbuf64 copy_load_bufs (.z(copy_load), .i(copy_bus), .oen(load_dv));
wire [63:0] tm_copy_load = load_dv ? {64{1'b0}} : copy_bus;
endmodule // tm