/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: tm_mux.v,v 1.3 2003/01/04 02:15:55 berndt Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	tm_mux
// description:	address-swap muxes, texel-sort muxes, texel-type mux,
//		texel-size mux, hi-lo muxes, and texel-format muxes
//
// designer:	Tony DeLaurier
// date:	7/27/94
//
////////////////////////////////////////////////////////////////////////

module tm_mux (clk, start_gclk, swap_rg, swap_ba, adrs_a, adrs_b_ba, adrs_c, adrs_d_ba, 
	       adrs_b_rg, adrs_d_rg, dout_bnk0l, dout_bnk1l, dout_bnk2l, 
	       dout_bnk3l, dout_bnk0h, dout_bnk1h, dout_bnk2h, dout_bnk3h,
	       tlut_en, tlut_type, tile_tex_type, tile_tex_size, palette, 
	       clr_ind_a, clr_ind_b, clr_ind_c, clr_ind_d, copy_bus, 
	       red_a, red_b, red_c, red_d, green_a, green_b, 
	       green_c, green_d, blue_a, blue_b, blue_c, 
	       blue_d, alpha_a, alpha_b, alpha_c, alpha_d);

  `include "tex.vh"

  input clk, start_gclk;                   // RDP gated clock

  input swap_rg;                // swap texels (RG)
  input swap_ba;                // swap texels (BA)

  input [4:0] adrs_a;           // address of texel a <12,3:0>
  input [4:0] adrs_b_ba;        // address of texel b (ba banks) <12,3:0>
  input [4:0] adrs_c;           // address of texel c <12,3:0>
  input [4:0] adrs_d_ba;        // address of texel d (ba banks) <12,3:0>
  input [4:0] adrs_b_rg;        // address of texel b (rg banks) <12,3:0>
  input [4:0] adrs_d_rg;        // address of texel d (rg banks) <12,3:0>

  input [15:0] dout_bnk0l;      // data out bank0 - low half
  input [15:0] dout_bnk1l;      // data out bank1 - low half
  input [15:0] dout_bnk2l;      // data out bank2 - low half
  input [15:0] dout_bnk3l;      // data out bank3 - low half
  input [15:0] dout_bnk0h;      // data out bank0 - high half
  input [15:0] dout_bnk1h;      // data out bank1 - high half
  input [15:0] dout_bnk2h;      // data out bank2 - high half
  input [15:0] dout_bnk3h;      // data out bank3 - high half

  input tlut_en;                // enable texture lookup table
  input tlut_type;              // tlut type

  input [2:0] tile_tex_type;    // tile texel type
  input [1:0] tile_tex_size;    // tile texel size

  input [3:0] palette;          // palette for 4-bit color index

  output [7:0] clr_ind_a;       // color index texel a
  output [7:0] clr_ind_b;       // color index texel b
  output [7:0] clr_ind_c;       // color index texel c
  output [7:0] clr_ind_d;       // color index texel d

  output [63:0] copy_bus;	// copy bus
  reg [63:0] copy_bus;		// copy bus

  output [8:0] red_a;	// texel a (red channel)
  output [8:0] red_b;	// texel b (red channel)
  output [8:0] red_c;	// texel c (red channel)
  output [8:0] red_d;	// texel d (red channel)

  output [8:0] green_a;	// texel a (green channel)
  output [8:0] green_b;	// texel b (green channel)
  output [8:0] green_c;	// texel c (green channel)
  output [8:0] green_d;	// texel d (green channel)

  output [8:0] blue_a;	// texel a (blue channel)
  output [8:0] blue_b;	// texel b (blue channel)
  output [8:0] blue_c;	// texel c (blue channel)
  output [8:0] blue_d;	// texel d (blue channel)

  output [8:0] alpha_a;	// texel a (alpha channel)
  output [8:0] alpha_b;	// texel b (alpha channel)
  output [8:0] alpha_c;	// texel c (alpha channel)
  output [8:0] alpha_d;	// texel d (alpha channel)

  reg [8:0] red_a;        	// texel a (red channel)
  reg [8:0] red_b;        	// texel b (red channel)
  reg [8:0] red_c;        	// texel c (red channel)
  reg [8:0] red_d;        	// texel d (red channel)

  reg [8:0] green_a;      	// texel a (green channel)
  reg [8:0] green_b;      	// texel b (green channel)
  reg [8:0] green_c;      	// texel c (green channel)
  reg [8:0] green_d;      	// texel d (green channel)

  reg [8:0] blue_a;       	// texel a (blue channel)
  reg [8:0] blue_b;       	// texel b (blue channel)
  reg [8:0] blue_c;       	// texel c (blue channel)
  reg [8:0] blue_d;       	// texel d (blue channel)

  reg [8:0] alpha_a;      	// texel a (alpha channel)
  reg [8:0] alpha_b;         // texel b (alpha channel)
  reg [8:0] alpha_c;         // texel c (alpha channel)
  reg [8:0] alpha_d;         // texel d (alpha channel)

  reg [2:0] texel_type;		// tlut or tile texel type
  reg [1:0] texel_size;		// tlut or tile texel size

  reg long_texel;		// texel type is 32-RGBA or 16-YUV

  reg [15:0] tex_a_rg;		// texel a after hi-lo mux (low half)
  reg [15:0] tex_b_rg;		// texel b after hi-lo mux (low half)
  reg [15:0] tex_c_rg;		// texel c after hi-lo mux (low half)
  reg [15:0] tex_d_rg;		// texel d after hi-lo mux (low half)

  reg [15:0] tex_a_ba;		// texel a after hi-lo mux (high half)
  reg [15:0] tex_b_ba;		// texel b after hi-lo mux (high half)
  reg [15:0] tex_c_ba;		// texel c after hi-lo mux (high half)
  reg [15:0] tex_d_ba;		// texel d after hi-lo mux (high half)

  reg [7:0] repl_a;		// texel a replicate bus
  reg [7:0] repl_b;		// texel b replicate bus
  reg [7:0] repl_c;		// texel c replicate bus
  reg [7:0] repl_d;		// texel d replicate bus

  reg [2:0] tile_tex_type_1d;  	// tile texel type delayed 1
  reg [2:0] tile_tex_type_2d;  	// tile texel type delayed 2
  reg [1:0] tile_tex_size_1d;  	// tile texel size delayed 1
  reg [1:0] tile_tex_size_2d;  	// tile texel size delayed 2

  reg [4:0] adrs_a_1d;         	// adrs_a delayed 2
  reg [4:0] adrs_b_ba_1d;      	// adrs_b_ba delayed 2
  reg [4:0] adrs_c_1d;         	// adrs_c delayed 2
  reg [4:0] adrs_d_ba_1d;      	// adrs_d_ba delayed 2
  reg [4:0] adrs_b_rg_1d;      	// adrs_b_rg delayed 2
  reg [4:0] adrs_d_rg_1d;      	// adrs_d_rg delayed 2

  reg swap_rg_1d;              	// swap_rg delayed 1
  reg swap_ba_1d;              	// swap_ba delayed 1

  reg [3:0] palette_1d;        	// palette delayed 1

  reg tlut_en_1d;        	// tlut_en delayed 1
  reg tlut_en_2d;        	// tlut_en delayed 2

  wire [4:0] swap_a_low;       	// swapped address a (low half)
  wire [4:0] swap_b_low;       	// swapped address b (low half)
  wire [4:0] swap_c_low;       	// swapped address c (low half)
  wire [4:0] swap_d_low;       	// swapped address d (low half)

  wire [4:0] swap_a_high;      	// swapped address a (high half)
  wire [4:0] swap_b_high;      	// swapped address b (high half)
  wire [4:0] swap_c_high;      	// swapped address c (high half)
  wire [4:0] swap_d_high;      	// swapped address d (high half)

  wire [15:0] sort_tex_a_low;  	// sorted texel a (low half)
  wire [15:0] sort_tex_b_low;  	// sorted texel b (low half)
  wire [15:0] sort_tex_c_low;  	// sorted texel c (low half)
  wire [15:0] sort_tex_d_low;  	// sorted texel d (low half)

  wire [15:0] sort_tex_a_high; 	// sorted texel a (high half)
  wire [15:0] sort_tex_b_high; 	// sorted texel b (high half)
  wire [15:0] sort_tex_c_high; 	// sorted texel c (high half)
  wire [15:0] sort_tex_d_high; 	// sorted texel d (high half)


  // nibble select mux

  function [3:0] nib_select;

    input [15:0] tex_rg;
    input [1:0] select;

    begin
  
      case (select[1:0])
        2'b00: nib_select[3:0] = tex_rg[3:0];
        2'b01: nib_select[3:0] = tex_rg[7:4];
        2'b10: nib_select[3:0] = tex_rg[11:8];
        2'b11: nib_select[3:0] = tex_rg[15:12];
        default: nib_select[3:0] = 4'hx;
      endcase
  
  end
  endfunction // nib_select


  // texel-sort mux (low half)

  function [15:0] tex_sort_low;

    input [3:2] adrs;
    input [15:0] dout_bnk0;
    input [15:0] dout_bnk1;
    input [15:0] dout_bnk2;
    input [15:0] dout_bnk3;

    begin

      case (adrs[3:2])
        2'b00: tex_sort_low = dout_bnk0;
        2'b01: tex_sort_low = dout_bnk1;
        2'b10: tex_sort_low = dout_bnk2;
        2'b11: tex_sort_low = dout_bnk3;
        default: tex_sort_low = 16'hx;
      endcase

    end
  endfunction // tex_sort_low


  // texel-sort mux (high half)

  function [15:0] tex_sort_high;

    input [3:2] adrs;
    input [1:0] tlut_bank;
    input tlut_en;
    input [15:0] dout_bnk0;
    input [15:0] dout_bnk1;
    input [15:0] dout_bnk2;
    input [15:0] dout_bnk3;

    reg [1:0] sel;

    begin

      sel[1:0] = tlut_en ? tlut_bank[1:0] : adrs[3:2];

      case (sel[1:0])
        2'b00: tex_sort_high = dout_bnk0;
        2'b01: tex_sort_high = dout_bnk1;
        2'b10: tex_sort_high = dout_bnk2;
        2'b11: tex_sort_high = dout_bnk3;
        default: tex_sort_high = 16'hx;
      endcase

    end
  endfunction // tex_sort_high


  // color index format mux 

  function [7:0] ci_form;

    input [15:0] sort_tex;
    input [1:0] swap_low;
    input [1:0] tile_texel_size;
    input [3:0] palette;

    reg msb_sel;
    reg [1:0] lsb_sel;

    begin

      msb_sel = ~swap_low[1];

      case (tile_texel_size[1:0])

        SIZE_4BIT:
          lsb_sel[1:0] = ~swap_low[1:0];

        default:
          lsb_sel[1:0] = {~swap_low[1], 1'b0};

      endcase

      ci_form[7:4] = (tile_texel_size == SIZE_4BIT) ? palette[3:0]
		: msb_sel? sort_tex[15:12] : sort_tex[7:4];

      ci_form[3:0] = nib_select(sort_tex[15:0], lsb_sel[1:0]);

    end
  endfunction // ci_form


  // hi-lo mux (low half)

  function [15:0] hi_lo_rg;

    input tlut_en;
    input long_texel;
    input [15:0] sort_tex_high;
    input [15:0] sort_tex_low;
    input adrs_msb;

    begin

      if (tlut_en)
        hi_lo_rg = sort_tex_high;
      else if (long_texel)
        hi_lo_rg = sort_tex_low;
      else
        hi_lo_rg = adrs_msb ? sort_tex_high : sort_tex_low;

    end
  endfunction // hi_lo_rg


  // hi-lo mux (high half)

  function [15:0] hi_lo_ba;

    input tlut_en;
    input long_texel;
    input [15:0] sort_tex_high;
    input [15:0] sort_tex_low;
    input adrs_msb;

    begin

      if (tlut_en || long_texel)
        hi_lo_ba = sort_tex_high;
      else
        hi_lo_ba = adrs_msb ? sort_tex_high : sort_tex_low;

    end
  endfunction // hi_lo_ba


  // texel-format mux (replicate)

  function [7:0] tex_form_rep;

    input [15:0] tex_rg;
    input [1:0] swap_low;
    input [2:0] texel_type;
    input [1:0] texel_size;
    input [3:0] palette;

    reg [1:0] msb_sel;
    reg [1:0] lsb_sel;

    begin

      case (texel_size[1:0])

        SIZE_4BIT:
	begin
          msb_sel[1:0] = ~swap_low[1:0];
          lsb_sel[1:0] = ~swap_low[1:0];
	end

        SIZE_8BIT:
	begin
          msb_sel[1:0] = {~swap_low[1], 1'b1};
          if (texel_type[2:0] == TYPE_IA)
            lsb_sel[1:0] = {~swap_low[1], 1'b1};
          else
            lsb_sel[1:0] = {~swap_low[1], 1'b0};
	end

        default:
	begin
          msb_sel[1:0] = 2'b11;
          lsb_sel[1:0] = 2'b10;
	end

      endcase

      tex_form_rep[7:4] = nib_select(tex_rg[15:0], msb_sel[1:0]);
      tex_form_rep[3:0] = nib_select(tex_rg[15:0], lsb_sel[1:0]);

      // if 4-bit CI mux in palette

      tex_form_rep[7:4] = ((texel_size[1:0] == SIZE_4BIT) && 
			   (texel_type[2:0] == TYPE_CI)) ? palette[3:0] : 
							   tex_form_rep[7:4];

      // special case 4-bit IA 

      tex_form_rep[7:0] = ((texel_size[1:0] == SIZE_4BIT) && 
                           (texel_type[2:0] == TYPE_IA)) ? 
		    {tex_form_rep[7:5], tex_form_rep[7:5], tex_form_rep[7:6]} :
		     tex_form_rep[7:0];

    end
  endfunction // tex_form_rep


  // texel-format mux (red)

  function [8:0] tex_form_red;

    input [7:0] repl;
    input [15:11] tex;
    input [2:0] texel_type;
    input [1:0] texel_size;

    begin

      tex_form_red[7] = repl[7] ^ (texel_type == TYPE_YUV);

      tex_form_red[6:0] = repl[6:0];

      tex_form_red[8] = tex_form_red[7] & (texel_type == TYPE_YUV);

      tex_form_red[7:0] = ((texel_type == TYPE_RGBA) &&
                           (texel_size == SIZE_16BIT)) ?
                           {tex[15:11], tex[15:13]} : tex_form_red[7:0];

    end
  endfunction // tex_form_red


  // texel-format mux (green)

  function [8:0] tex_form_green;

    input [7:0] repl;
    input [10:0] tex;
    input [2:0] texel_type;
    input [1:0] texel_size;

    begin

      tex_form_green[7:0] = (((texel_type == TYPE_IA) &&
                             (texel_size == SIZE_16BIT)) ||
                             (texel_size == SIZE_4BIT) ||
                             (texel_size == SIZE_8BIT)) ?
                             repl[7:0] : tex[7:0];

      tex_form_green[7] = tex_form_green[7] ^ (texel_type == TYPE_YUV);

      tex_form_green[8] = tex_form_green[7] & (texel_type == TYPE_YUV);

      tex_form_green[7:0] = ((texel_type == TYPE_RGBA) &&
                             (texel_size == SIZE_16BIT)) ?
                             {tex[10:6], tex[10:8]} : tex_form_green[7:0];

    end
  endfunction // tex_form_green


  // texel-format mux (blue)

  function [8:0] tex_form_blue;

    input [7:0] repl;
    input [15:0] tex;
    input [1:1] swap_high;
    input [2:0] texel_type;
    input [1:0] texel_size;

    begin

      tex_form_blue[7:0] = ((!(texel_type == TYPE_YUV)) || (!swap_high[1])) ?
                             tex[15:8] : tex[7:0];

      tex_form_blue[7:0] = (((texel_type == TYPE_IA) &&
                             (texel_size == SIZE_16BIT)) ||
                             (texel_size == SIZE_4BIT) ||
                             (texel_size == SIZE_8BIT)) ?
                             repl[7:0] : tex_form_blue[7:0];

      tex_form_blue[7:0] = ((texel_type == TYPE_RGBA) &&
                            (texel_size == SIZE_16BIT)) ?
                            {tex[5:1], tex[5:3]} : tex_form_blue[7:0];

      tex_form_blue[8] = 1'b0;

    end
  endfunction // tex_form_blue


  // texel-format mux (alpha)

  function [8:0] tex_form_alpha;

    input [7:0] repl;
    input [15:0] tex;
    input [1:0] swap_high;
    input [2:0] texel_type;
    input [1:0] texel_size;

    reg [1:0] msb_sel;
    reg lsb_sel;

    begin

      case (texel_size[1:0])

        SIZE_4BIT:
          msb_sel[1:0] = {~swap_high[1], ~swap_high[0]};

        SIZE_8BIT:
          msb_sel[1:0] = {~swap_high[1], 1'b0};

        SIZE_16BIT:
          if (texel_type[2:0] == TYPE_YUV)
            msb_sel[1:0] = {~swap_high[1], 1'b1};
	  else
	    msb_sel[1:0] = 2'b01;

        default:
          msb_sel[1:0] = 2'b01;

      endcase

      tex_form_alpha[7:4] = nib_select(tex[15:0], msb_sel[1:0]);

      lsb_sel = (((texel_type[2:0] == TYPE_YUV) ||
                 ((texel_size[1:0] == SIZE_8BIT) &&
                  (texel_type[2:0] == TYPE_IA))) && (!swap_high[1]));

      tex_form_alpha[3:0] = lsb_sel ? tex[11:8] : tex[3:0];


      tex_form_alpha[7:0] = ((texel_size[1:0] == SIZE_4BIT) &&
                             (texel_type[2:0] == TYPE_IA)) ?
                             {8{tex_form_alpha[4]}} : tex_form_alpha[7:0];

      tex_form_alpha[7:0] = (((texel_size[1:0] == SIZE_4BIT) &&
                              (texel_type[2:0] != TYPE_IA)) ||
                             ((texel_size[1:0] == SIZE_8BIT) &&
                              (texel_type[2:0] != TYPE_IA))) ?
                               repl[7:0] : tex_form_alpha[7:0];

      tex_form_alpha[7:0] = ((texel_type == TYPE_RGBA) &&
                             (texel_size == SIZE_16BIT)) ?
                             {8{tex[0]}} : tex_form_alpha[7:0];

      tex_form_alpha[8] = 1'b0;

    end
  endfunction // tex_form_alpha


  // address-swap muxes (low half)

  assign swap_a_low[4:0] = (!swap_rg_1d) ? adrs_a_1d : adrs_d_rg_1d;
  assign swap_b_low[4:0] = (!swap_rg_1d) ? adrs_b_rg_1d : adrs_c_1d;
  assign swap_c_low[4:0] = (!swap_rg_1d) ? adrs_c_1d : adrs_b_rg_1d;
  assign swap_d_low[4:0] = (!swap_rg_1d) ? adrs_d_rg_1d : adrs_a_1d;

  // address-swap muxes (high half)

  assign swap_a_high[4:0] = (!swap_ba_1d) ? adrs_a_1d : adrs_d_ba_1d;
  assign swap_b_high[4:0] = (!swap_ba_1d) ? adrs_b_ba_1d : adrs_c_1d;
  assign swap_c_high[4:0] = (!swap_ba_1d) ? adrs_c_1d : adrs_b_ba_1d;
  assign swap_d_high[4:0] = (!swap_ba_1d) ? adrs_d_ba_1d : adrs_a_1d;

  // texel-sort muxes (low half)

  assign sort_tex_a_low[15:0] = tex_sort_low(swap_a_low[3:2], dout_bnk0l, 
                                      dout_bnk1l, dout_bnk2l, dout_bnk3l);

  assign sort_tex_b_low[15:0] = tex_sort_low(swap_b_low[3:2], dout_bnk0l, 
                                      dout_bnk1l, dout_bnk2l, dout_bnk3l);

  assign sort_tex_c_low[15:0] = tex_sort_low(swap_c_low[3:2], dout_bnk0l, 
                                      dout_bnk1l, dout_bnk2l, dout_bnk3l);

  assign sort_tex_d_low[15:0] = tex_sort_low(swap_d_low[3:2], dout_bnk0l, 
                                      dout_bnk1l, dout_bnk2l, dout_bnk3l);

  // texel-sort muxes (high half)

  assign sort_tex_a_high[15:0] = tex_sort_high(swap_a_high[3:2], 2'b00, 
                                 tlut_en_2d, dout_bnk0h, dout_bnk1h, 
                                 dout_bnk2h, dout_bnk3h);

  assign sort_tex_b_high[15:0] = tex_sort_high(swap_b_high[3:2], 2'b01, 
                                 tlut_en_2d, dout_bnk0h, dout_bnk1h, 
                                 dout_bnk2h, dout_bnk3h);

  assign sort_tex_c_high[15:0] = tex_sort_high(swap_c_high[3:2], 2'b10, 
                                 tlut_en_2d, dout_bnk0h, dout_bnk1h, 
                                 dout_bnk2h, dout_bnk3h);

  assign sort_tex_d_high[15:0] = tex_sort_high(swap_d_high[3:2], 2'b11, 
                                 tlut_en_2d, dout_bnk0h, dout_bnk1h, 
                                 dout_bnk2h, dout_bnk3h);

  // color index format muxes

  assign clr_ind_a[7:0] = ci_form(sort_tex_a_low, swap_a_low[1:0], 
                                  tile_tex_size_2d, palette_1d);

  assign clr_ind_b[7:0] = ci_form(sort_tex_b_low, swap_b_low[1:0], 
                                  tile_tex_size_2d, palette_1d);

  assign clr_ind_c[7:0] = ci_form(sort_tex_c_low, swap_c_low[1:0], 
                                  tile_tex_size_2d, palette_1d);

  assign clr_ind_d[7:0] = ci_form(sort_tex_d_low, swap_d_low[1:0], 
                                  tile_tex_size_2d, palette_1d);

  always @(posedge clk)
   if (start_gclk) begin

    // delay signals into block

    tile_tex_type_1d <= tile_tex_type;
    tile_tex_type_2d <= tile_tex_type_1d;

    tile_tex_size_1d <= tile_tex_size;
    tile_tex_size_2d <= tile_tex_size_1d;

    adrs_a_1d <= adrs_a;
    adrs_b_ba_1d <= adrs_b_ba;
    adrs_c_1d <= adrs_c;
    adrs_d_ba_1d <= adrs_d_ba;
    adrs_b_rg_1d <= adrs_b_rg;
    adrs_d_rg_1d <= adrs_d_rg;

    swap_rg_1d <= swap_rg;
    swap_ba_1d <= swap_ba;

    palette_1d <= palette;

    tlut_en_1d <= tlut_en;
    tlut_en_2d <= tlut_en_1d;

    // texel-type and texel-size muxes

    if (tlut_en_2d)
    begin
      texel_size[1:0] = SIZE_16BIT;
      if (tlut_type == TLUT_RGBA)
	texel_type[2:0] = TYPE_RGBA;
      else
	texel_type[2:0] = TYPE_IA;
    end
    else
    begin
      texel_type[2:0] = tile_tex_type_2d[2:0];
      texel_size[1:0] = tile_tex_size_2d[1:0];
    end

    // hi-lo muxes (low half)

    long_texel = (((texel_type[2:0] == TYPE_RGBA) && 
		   (texel_size[1:0] == SIZE_32BIT)) || 
		   (texel_type[2:0] == TYPE_YUV));

    tex_a_rg = hi_lo_rg(tlut_en_2d, long_texel, sort_tex_a_high, 
		        sort_tex_a_low, swap_a_low[4]);

    tex_b_rg = hi_lo_rg(tlut_en_2d, long_texel, sort_tex_b_high, 
		        sort_tex_b_low, swap_b_low[4]);

    tex_c_rg = hi_lo_rg(tlut_en_2d, long_texel, sort_tex_c_high, 
		        sort_tex_c_low, swap_c_low[4]);

    tex_d_rg = hi_lo_rg(tlut_en_2d, long_texel, sort_tex_d_high, 
		        sort_tex_d_low, swap_d_low[4]);

    // hi-lo muxes (high half)

    tex_a_ba = hi_lo_ba(tlut_en_2d, long_texel, sort_tex_a_high, 
		        sort_tex_a_low, swap_a_high[4]);

    tex_b_ba = hi_lo_ba(tlut_en_2d, long_texel, sort_tex_b_high, 
		        sort_tex_b_low, swap_b_high[4]);

    tex_c_ba = hi_lo_ba(tlut_en_2d, long_texel, sort_tex_c_high, 
		        sort_tex_c_low, swap_c_high[4]);

    tex_d_ba = hi_lo_ba(tlut_en_2d, long_texel, sort_tex_d_high, 
		        sort_tex_d_low, swap_d_high[4]);

    // texel format muxes (replicate)

    repl_a = tex_form_rep(tex_a_rg, swap_a_low[1:0], texel_type, texel_size, 
		          palette_1d);

    repl_b = tex_form_rep(tex_b_rg, swap_b_low[1:0], texel_type, texel_size, 
		          palette_1d);

    repl_c = tex_form_rep(tex_c_rg, swap_c_low[1:0], texel_type, texel_size, 
		          palette_1d);

    repl_d = tex_form_rep(tex_d_rg, swap_d_low[1:0], texel_type, texel_size, 
		          palette_1d);

    // copy path

    copy_bus[31:0] <= {tex_c_rg, tex_d_rg};

    copy_bus[63:32] <= (texel_size[1:0] == SIZE_16BIT) ? {tex_a_rg, tex_b_rg} :
			{repl_a, repl_b, repl_c, repl_d};

    // texel-format muxes (red)

    red_a <= tex_form_red(repl_a, tex_a_rg[15:11], texel_type, texel_size); 
    
    red_b <= tex_form_red(repl_b, tex_b_rg[15:11], texel_type, texel_size); 
    
    red_c <= tex_form_red(repl_c, tex_c_rg[15:11], texel_type, texel_size); 
    
    red_d <= tex_form_red(repl_d, tex_d_rg[15:11], texel_type, texel_size); 
    
    // texel-format muxes (green)

    green_a <= tex_form_green(repl_a, tex_a_rg[10:0], texel_type, texel_size); 
    
    green_b <= tex_form_green(repl_b, tex_b_rg[10:0], texel_type, texel_size); 
    
    green_c <= tex_form_green(repl_c, tex_c_rg[10:0], texel_type, texel_size); 
    
    green_d <= tex_form_green(repl_d, tex_d_rg[10:0], texel_type, texel_size); 
    
    // texel-format muxes (blue)

    blue_a <= tex_form_blue(repl_a, tex_a_ba[15:0], swap_a_high[1], texel_type, 
			   texel_size); 

    blue_b <= tex_form_blue(repl_b, tex_b_ba[15:0], swap_b_high[1], texel_type, 
			   texel_size); 

    blue_c <= tex_form_blue(repl_c, tex_c_ba[15:0], swap_c_high[1], texel_type, 
			   texel_size); 

    blue_d <= tex_form_blue(repl_d, tex_d_ba[15:0], swap_d_high[1], texel_type, 
			   texel_size); 

    // texel-format muxes (alpha)

    alpha_a <= tex_form_alpha(repl_a, tex_a_ba[15:0], swap_a_high[1:0], 
			     texel_type, texel_size);

    alpha_b <= tex_form_alpha(repl_b, tex_b_ba[15:0], swap_b_high[1:0], 
			     texel_type, texel_size);

    alpha_c <= tex_form_alpha(repl_c, tex_c_ba[15:0], swap_c_high[1:0], 
			     texel_type, texel_size);

    alpha_d <= tex_form_alpha(repl_d, tex_d_ba[15:0], swap_d_high[1:0], 
			     texel_type, texel_size);

  end // always

endmodule // tm_mux