/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: vi_pipe.v,v 1.1 2002/05/21 23:55:45 berndt Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	vi_pipe
// description:	Pipeline for overlapped 3 by 5 by 4 components (s,r,g,b)
//		for back-end antialiasing filter for video interface.
//		Instances filter, divot, lerp, and gamma. Rand is kept
//		outside for simulation convenience.
//
// designer:	Phil Gossett
// date:	6/29/95
//
////////////////////////////////////////////////////////////////////////

module vi_pipe (vclk, type, aa_off, dither_filter_enable,
		divot_enable, gamma_enable, gamma_dither_enable, 
		rand, hfrac, vfrac,
		rgb0i, rgb1i, rgb2i, rgb3i,
		cvg0i, cvg1i, cvg2i, cvg3i,
		synci, srgb, sync);

input vclk;
input [1:0] type;	// 0 means blank
input aa_off;		// 1 means no antialiasing
input dither_filter_enable;
input divot_enable;
input gamma_enable;
input gamma_dither_enable;
input [5:0] rand;
input [4:0] hfrac;
input [4:0] vfrac;
input [7:0] rgb0i;
input [7:0] rgb1i;
input [7:0] rgb2i;
input [7:0] rgb3i;
input [2:0] cvg0i;
input [2:0] cvg1i;
input [2:0] cvg2i;
input [2:0] cvg3i;
input synci;

output [6:0] srgb;
output sync;

wire [7:0] rgb2x;
wire [7:0] rgb1e;
wire [7:0] rgb2e;
wire [7:0] rgb1x;
wire [2:0] cvg0q;
wire [2:0] cvg1q;
wire [2:0] cvg2q;
wire [2:0] cvg3q;
wire synce;
wire pipe_hold;

reg pipe_hold_reg;

reg [7:0] rgb2xx;
reg [7:0] rgb2xy;
reg [7:0] rgb2xz;
reg [7:0] rgb1d;
reg [7:0] rgb1dx;
reg [7:0] rgb1dy;
reg [7:0] rgb1dz;
reg [7:0] rgb2y;
reg [7:0] rgb2yx;
reg [7:0] rgb2yy;
reg [7:0] rgb2yz;
reg [7:0] rgb1c;

reg [7:0] rgb1ex;
reg [7:0] rgb1ey;
reg [7:0] rgb1ez;
reg [7:0] rgb2d;
reg [7:0] rgb2dx;
reg [7:0] rgb2dy;
reg [7:0] rgb2dz;
reg [7:0] rgb1a;
reg [7:0] rgb1ax;
reg [7:0] rgb1ay;
reg [7:0] rgb1az;
reg [7:0] rgb2c;
reg [7:0] rgb2cx;
reg [7:0] rgb2cy;
reg [7:0] rgb2cz;
reg [7:0] rgb1b;

reg [7:0] rgb2ex;
reg [7:0] rgb2ey;
reg [7:0] rgb2ez;
reg [7:0] rgb1f;
reg [7:0] rgb1fx;
reg [7:0] rgb1fy;
reg [7:0] rgb1fz;
reg [7:0] rgb2a;
reg [7:0] rgb2ax;
reg [7:0] rgb2ay;
reg [7:0] rgb2az;
reg [7:0] rgb1g;
reg [7:0] rgb1gx;
reg [7:0] rgb1gy;
reg [7:0] rgb1gz;
reg [7:0] rgb2b;

reg [7:0] rgb1xx;
reg [7:0] rgb1xy;
reg [7:0] rgb1xz;
reg [7:0] rgb2f;
reg [7:0] rgb2fx;
reg [7:0] rgb2fy;
reg [7:0] rgb2fz;
reg [7:0] rgb1y;
reg [7:0] rgb1yx;
reg [7:0] rgb1yy;
reg [7:0] rgb1yz;
reg [7:0] rgb2g;

reg [2:0] cvg2x;
reg [2:0] cvg1d;
reg [2:0] cvg2y;
reg [2:0] cvg1c;

reg [2:0] cvg1e;
reg [2:0] cvg2d;
reg [2:0] cvg1a;
reg [2:0] cvg2c;
reg [2:0] cvg1b;

reg [2:0] cvg2e;
reg [2:0] cvg1f;
reg [2:0] cvg2a;
reg [2:0] cvg1g;
reg [2:0] cvg2b;

reg [2:0] cvg1x;
reg [2:0] cvg2f;
reg [2:0] cvg1y;
reg [2:0] cvg2g;

reg syncex;
reg syncey;
reg syncez;
reg syncf;
reg syncfx;
reg syncfy;
reg syncfz;
reg synca;
reg syncax;
reg syncay;
reg syncaz;
reg syncg;
reg syncgx;
reg syncgy;
reg syncgz;
reg syncb;

wire [7:0] filter1rgb;
wire [7:0] filter2rgb;
wire [2:0] filter1cvg;
wire [2:0] filter2cvg;
wire filter1sync;
wire filter2sync;
wire [7:0] divot1rgb;
wire [7:0] divot2rgb;
wire divotsync;
wire [7:0] vlerp0rgb;
wire vlerp0sync;
wire vlerp_hold;

reg vlerp_hold_reg;
reg [4:0] vfraca;
reg [4:0] vfracb;
reg [4:0] vfracc;
reg [7:0] vlerp1rgb;
reg [7:0] vlerp2rgb;
reg [7:0] vlerp3rgb;
reg [7:0] vlerp4rgb;
reg vlerp1sync;
reg vlerp2sync;
reg vlerp3sync;
reg vlerp4sync;
reg [4:0] hfraca;
reg [4:0] hfracb;
reg [4:0] hfracc;
// reg [4:0] hfracd;
// reg [4:0] hfrace;
// reg [4:0] hfracf;
// reg [4:0] hfracg;

wire [7:0] hlerprgb;
wire hlerpsync;
wire [6:0] gammargb;
wire gammasync;

reg [6:0] srgb;
reg sync;

assign rgb2x = rgb0i;
assign rgb1e = rgb1i;
assign rgb2e = rgb2i;
assign rgb1x = rgb3i;
assign cvg0q = cvg0i;
assign cvg1q = cvg1i | {3{aa_off}};
assign cvg2q = cvg2i | {3{aa_off}};
assign cvg3q = cvg3i;
assign synce = synci;

always @(posedge vclk)
begin
	rgb2xx[7]   <= (pipe_hold && (| type)) ? rgb1d[7]   : rgb2x[7];
	rgb2xx[6:0] <= (pipe_hold && !synce  ) ? rgb1d[6:0] : rgb2x[6:0];
	rgb2xy <= rgb2xx;
	rgb2xz <= rgb2xy;
	rgb1d  <= rgb2xz;
	rgb1dx[7]   <= (pipe_hold && (| type)) ? rgb2y[7]   : rgb1d[7];
	rgb1dx[6:0] <= (pipe_hold && !syncf  ) ? rgb2y[6:0] : rgb1d[6:0];
	rgb1dy <= rgb1dx;
	rgb1dz <= rgb1dy;
	rgb2y  <= rgb1dz;
	rgb2yx[7]   <= (pipe_hold && (| type)) ? rgb1c[7]   : rgb2y[7];
	rgb2yx[6:0] <= (pipe_hold && !synca  ) ? rgb1c[6:0] : rgb2y[6:0];
	rgb2yy <= rgb2yx;
	rgb2yz <= rgb2yy;
	rgb1c  <= rgb2yz;

	rgb1ex[7]   <= (pipe_hold && (| type)) ? rgb2d[7]   : rgb1e[7];
	rgb1ex[6:0] <= (pipe_hold && !synce  ) ? rgb2d[6:0] : rgb1e[6:0];
	rgb1ey <= rgb1ex;
	rgb1ez <= rgb1ey;
	rgb2d  <= rgb1ez;
	rgb2dx[7]   <= (pipe_hold && (| type)) ? rgb1a[7]   : rgb2d[7];
	rgb2dx[6:0] <= (pipe_hold && !syncf  ) ? rgb1a[6:0] : rgb2d[6:0];
	rgb2dy <= rgb2dx;
	rgb2dz <= rgb2dy;
	rgb1a  <= rgb2dz;
	rgb1ax[7]   <= (pipe_hold && (| type)) ? rgb2c[7]   : rgb1a[7];
	rgb1ax[6:0] <= (pipe_hold && !synca  ) ? rgb2c[6:0] : rgb1a[6:0];
	rgb1ay <= rgb1ax;
	rgb1az <= rgb1ay;
	rgb2c  <= rgb1az;
	rgb2cx[7]   <= (pipe_hold && (| type)) ? rgb1b[7]   : rgb2c[7];
	rgb2cx[6:0] <= (pipe_hold && !syncg  ) ? rgb1b[6:0] : rgb2c[6:0];
	rgb2cy <= rgb2cx;
	rgb2cz <= rgb2cy;
	rgb1b  <= rgb2cz;

	rgb2ex[7]   <= (pipe_hold && (| type)) ? rgb1f[7]   : rgb2e[7];
	rgb2ex[6:0] <= (pipe_hold && !synce  ) ? rgb1f[6:0] : rgb2e[6:0];
	rgb2ey <= rgb2ex;
	rgb2ez <= rgb2ey;
	rgb1f  <= rgb2ez;
	rgb1fx[7]   <= (pipe_hold && (| type)) ? rgb2a[7]   : rgb1f[7];
	rgb1fx[6:0] <= (pipe_hold && !syncf  ) ? rgb2a[6:0] : rgb1f[6:0];
	rgb1fy <= rgb1fx;
	rgb1fz <= rgb1fy;
	rgb2a  <= rgb1fz;
	rgb2ax[7]   <= (pipe_hold && (| type)) ? rgb1g[7]   : rgb2a[7];
	rgb2ax[6:0] <= (pipe_hold && !synca  ) ? rgb1g[6:0] : rgb2a[6:0];
	rgb2ay <= rgb2ax;
	rgb2az <= rgb2ay;
	rgb1g  <= rgb2az;
	rgb1gx[7]   <= (pipe_hold && (| type)) ? rgb2b[7]   : rgb1g[7];
	rgb1gx[6:0] <= (pipe_hold && !syncg  ) ? rgb2b[6:0] : rgb1g[6:0];
	rgb1gy <= rgb1gx;
	rgb1gz <= rgb1gy;
	rgb2b  <= rgb1gz;

	rgb1xx[7]   <= (pipe_hold && (| type)) ? rgb2f[7]   : rgb1x[7];
	rgb1xx[6:0] <= (pipe_hold && !synce  ) ? rgb2f[6:0] : rgb1x[6:0];
	rgb1xy <= rgb1xx;
	rgb1xz <= rgb1xy;
	rgb2f  <= rgb1xz;
	rgb2fx[7]   <= (pipe_hold && (| type)) ? rgb1y[7]   : rgb2f[7];
	rgb2fx[6:0] <= (pipe_hold && !syncf  ) ? rgb1y[6:0] : rgb2f[6:0];
	rgb2fy <= rgb2fx;
	rgb2fz <= rgb2fy;
	rgb1y  <= rgb2fz;
	rgb1yx[7]   <= (pipe_hold && (| type)) ? rgb2g[7]   : rgb1y[7];
	rgb1yx[6:0] <= (pipe_hold && !synca  ) ? rgb2g[6:0] : rgb1y[6:0];
	rgb1yy <= rgb1yx;
	rgb1yz <= rgb1yy;
	rgb2g  <= rgb1yz;

        cvg2x  <= (                  synce) ? cvg0q   : cvg2x;
        cvg1d  <= (!pipe_hold_reg && syncf) ? cvg2x   : cvg1d;
        cvg2y  <= (!pipe_hold_reg && synca) ? cvg1d   : cvg2y;
        cvg1c  <= (!pipe_hold_reg && syncg) ? cvg2y   : cvg1c;

        cvg1e  <= (                  synce) ? cvg1q   : cvg1e;
        cvg2d  <= (!pipe_hold_reg && syncf) ? cvg1e   : cvg2d;
        cvg1a  <= (!pipe_hold_reg && synca) ? cvg2d   : cvg1a;
        cvg2c  <= (!pipe_hold_reg && syncg) ? cvg1a   : cvg2c;
        cvg1b  <= (!pipe_hold_reg && syncb) ? cvg2c   : cvg1b;

        cvg2e  <= (                  synce) ? cvg2q   : cvg2e;
        cvg1f  <= (!pipe_hold_reg && syncf) ? cvg2e   : cvg1f;
        cvg2a  <= (!pipe_hold_reg && synca) ? cvg1f   : cvg2a;
        cvg1g  <= (!pipe_hold_reg && syncg) ? cvg2a   : cvg1g;
        cvg2b  <= (!pipe_hold_reg && syncb) ? cvg1g   : cvg2b;

        cvg1x  <= (                  synce) ? cvg3q   : cvg1x;
        cvg2f  <= (!pipe_hold_reg && syncf) ? cvg1x   : cvg2f;
        cvg1y  <= (!pipe_hold_reg && synca) ? cvg2f   : cvg1y;
        cvg2g  <= (!pipe_hold_reg && syncg) ? cvg1y   : cvg2g;

	syncex <= synce;
	syncey <= syncex;
	syncez <= syncey;
	syncf  <= syncez;
	syncfx <= syncf;
	syncfy <= syncfx;
	syncfz <= syncfy;
	synca  <= syncfz;
	syncax <= synca;
	syncay <= syncax;
	syncaz <= syncay;
	syncg  <= syncaz;
	syncgx <= syncg;
	syncgy <= syncgx;
	syncgz <= syncgy;
	syncb  <= syncgz;

        vfraca  <= divotsync ? vfrac  : vfraca;
        vfracb  <= divotsync ? vfraca : vfracb;
        vfracc  <= divotsync ? vfracb : vfracc;
end

vi_filter vif1 (.vclk(vclk), .dither_filter_enable(dither_filter_enable),
		.rgb_o(rgb2y), .rgb_u(rgb2a), .rgb_l(rgb2d), .rgb_r(rgb2c),
		.rgb_a(rgb1a), .rgb_b(rgb1b), .rgb_c(rgb1c), .rgb_d(rgb1d),
		.rgb_e(rgb1e), .rgb_f(rgb1f), .rgb_g(rgb1g),
		.cvg_a(cvg1a), .cvg_b(cvg1b), .cvg_c(cvg1c), .cvg_d(cvg1d),
		.cvg_e(cvg1e), .cvg_f(cvg1f), .cvg_g(cvg1g),
		.sync_e(synce), .filter_rgb(filter1rgb),
		.filter_cvg(filter1cvg), .filter_sync(filter1sync));
vi_filter vif2 (.vclk(vclk), .dither_filter_enable(dither_filter_enable),
		.rgb_o(rgb1a), .rgb_u(rgb1y), .rgb_l(rgb1f), .rgb_r(rgb1g),
		.rgb_a(rgb2a), .rgb_b(rgb2b), .rgb_c(rgb2c), .rgb_d(rgb2d),
		.rgb_e(rgb2e), .rgb_f(rgb2f), .rgb_g(rgb2g),
		.cvg_a(cvg2a), .cvg_b(cvg2b), .cvg_c(cvg2c), .cvg_d(cvg2d),
		.cvg_e(cvg2e), .cvg_f(cvg2f), .cvg_g(cvg2g),
		.sync_e(synce), .filter_rgb(filter2rgb),
		.filter_cvg(filter2cvg), .filter_sync(filter2sync));
vi_divot vid1  (.vclk(vclk), .type(type), .divot_enable(divot_enable),
		.rgb(filter1rgb), .cvg(filter1cvg), .sync(filter1sync),
		.divot_rgb(divot1rgb), .divot_sync(divotsync));
vi_divot vid2  (.vclk(vclk), .type(type), .divot_enable(divot_enable),
		.rgb(filter2rgb), .cvg(filter2cvg), .sync(filter2sync),
		.divot_rgb(divot2rgb));
vi_lerp vivl   (.vclk(vclk), .frac(vfracc),
		.rgb_a(divot1rgb), .rgb_b(divot2rgb), .sync_b(divotsync),
		.lerp_rgb(vlerp0rgb), .lerp_sync(vlerp0sync));

assign pipe_hold = synce ? rgb1e[0] : pipe_hold_reg;

always @(posedge vclk)
begin
	pipe_hold_reg <= pipe_hold;

	vlerp1rgb[7]   <= (vlerp_hold && (| type)   ) ? vlerp4rgb[7] :
							vlerp0rgb[7];
	vlerp1rgb[6:0] <= (vlerp_hold && !vlerp0sync) ? vlerp4rgb[6:0] :
							vlerp0rgb[6:0];
	vlerp2rgb <= vlerp1rgb;
	vlerp3rgb <= vlerp2rgb;
	vlerp4rgb <= vlerp3rgb;

	vlerp1sync <= vlerp0sync;
	vlerp2sync <= vlerp1sync;
	vlerp3sync <= vlerp2sync;
	vlerp4sync <= vlerp3sync;

        hfraca  <= vlerp4sync ? hfrac  : hfraca;
        hfracb  <= vlerp4sync ? hfraca : hfracb;
        hfracc  <= vlerp4sync ? hfracb : hfracc;
//        hfracd  <= vlerp4sync ? hfracc : hfracd;
//        hfrace  <= vlerp4sync ? hfracd : hfrace;
//        hfracf  <= vlerp4sync ? hfrace : hfracf;
//        hfracg  <= vlerp4sync ? hfracf : hfracg;
end

vi_lerp vivh   (.vclk(vclk), .frac(hfracc),	// was hfracg
		.rgb_a(vlerp4rgb), .rgb_b(vlerp0rgb), .sync_b(vlerp0sync),
		.lerp_rgb(hlerprgb), .lerp_sync(hlerpsync));
vi_gamma vigm  (.vclk(vclk), .gamma_enable(gamma_enable),
		.gamma_dither_enable(gamma_dither_enable),
		.rgb(hlerprgb), .rand(rand), .sync(hlerpsync),
                .gamma_rgb(gammargb), .gamma_sync(gammasync));

assign vlerp_hold = vlerp0sync ? vlerp0rgb[5] : vlerp_hold_reg;

always @(posedge vclk)
begin
	vlerp_hold_reg <= vlerp_hold;
	srgb <= gammargb;
	sync <= !gammasync;
end

endmodule // vi_pipe