vi_spanbuf.v
3.59 KB
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// vi_spanbuf.v v1 Frank Berndt
// wrapper for vi span buffers;
// :set tabstop=4
// note: vclk inversion tree if synthesize
module vi_spanbuf (
clk, vclk, aa, ab, di, wen, dout
);
input clk; // write port clk;
input vclk; // read port clk
input [3:0] aa; // write address;
input [3:0] ab; // read address;
input [71:0] di; // write data;
input wen; // write enable;
output [71:0] dout; // read data;
// instantiate NEC model;
// single-port 16x72 SRAM;
// port A is write, port B is read;
wire [4:0] wa; // port A write address;
wire [4:0] ra; // port B read address;
wire csa; // write port A enable (active low);
wire csb; // read port B enable (active low);
assign wa = { 1'b0, aa };
assign ra = { 1'b0, ab };
assign csa = ~wen;
assign csb = 1'b0;
WBSRAMDHDWR32W72C2 ram (
.DO71(dout[71]),
.DO70(dout[70]),
.DO69(dout[69]),
.DO68(dout[68]),
.DO67(dout[67]),
.DO66(dout[66]),
.DO65(dout[65]),
.DO64(dout[64]),
.DO63(dout[63]),
.DO62(dout[62]),
.DO61(dout[61]),
.DO60(dout[60]),
.DO59(dout[59]),
.DO58(dout[58]),
.DO57(dout[57]),
.DO56(dout[56]),
.DO55(dout[55]),
.DO54(dout[54]),
.DO53(dout[53]),
.DO52(dout[52]),
.DO51(dout[51]),
.DO50(dout[50]),
.DO49(dout[49]),
.DO48(dout[48]),
.DO47(dout[47]),
.DO46(dout[46]),
.DO45(dout[45]),
.DO44(dout[44]),
.DO43(dout[43]),
.DO42(dout[42]),
.DO41(dout[41]),
.DO40(dout[40]),
.DO39(dout[39]),
.DO38(dout[38]),
.DO37(dout[37]),
.DO36(dout[36]),
.DO35(dout[35]),
.DO34(dout[34]),
.DO33(dout[33]),
.DO32(dout[32]),
.DO31(dout[31]),
.DO30(dout[30]),
.DO29(dout[29]),
.DO28(dout[28]),
.DO27(dout[27]),
.DO26(dout[26]),
.DO25(dout[25]),
.DO24(dout[24]),
.DO23(dout[23]),
.DO22(dout[22]),
.DO21(dout[21]),
.DO20(dout[20]),
.DO19(dout[19]),
.DO18(dout[18]),
.DO17(dout[17]),
.DO16(dout[16]),
.DO15(dout[15]),
.DO14(dout[14]),
.DO13(dout[13]),
.DO12(dout[12]),
.DO11(dout[11]),
.DO10(dout[10]),
.DO9(dout[9]),
.DO8(dout[8]),
.DO7(dout[7]),
.DO6(dout[6]),
.DO5(dout[5]),
.DO4(dout[4]),
.DO3(dout[3]),
.DO2(dout[2]),
.DO1(dout[1]),
.DO0(dout[0]),
.DI71(di[71]),
.DI70(di[70]),
.DI69(di[69]),
.DI68(di[68]),
.DI67(di[67]),
.DI66(di[66]),
.DI65(di[65]),
.DI64(di[64]),
.DI63(di[63]),
.DI62(di[62]),
.DI61(di[61]),
.DI60(di[60]),
.DI59(di[59]),
.DI58(di[58]),
.DI57(di[57]),
.DI56(di[56]),
.DI55(di[55]),
.DI54(di[54]),
.DI53(di[53]),
.DI52(di[52]),
.DI51(di[51]),
.DI50(di[50]),
.DI49(di[49]),
.DI48(di[48]),
.DI47(di[47]),
.DI46(di[46]),
.DI45(di[45]),
.DI44(di[44]),
.DI43(di[43]),
.DI42(di[42]),
.DI41(di[41]),
.DI40(di[40]),
.DI39(di[39]),
.DI38(di[38]),
.DI37(di[37]),
.DI36(di[36]),
.DI35(di[35]),
.DI34(di[34]),
.DI33(di[33]),
.DI32(di[32]),
.DI31(di[31]),
.DI30(di[30]),
.DI29(di[29]),
.DI28(di[28]),
.DI27(di[27]),
.DI26(di[26]),
.DI25(di[25]),
.DI24(di[24]),
.DI23(di[23]),
.DI22(di[22]),
.DI21(di[21]),
.DI20(di[20]),
.DI19(di[19]),
.DI18(di[18]),
.DI17(di[17]),
.DI16(di[16]),
.DI15(di[15]),
.DI14(di[14]),
.DI13(di[13]),
.DI12(di[12]),
.DI11(di[11]),
.DI10(di[10]),
.DI9(di[9]),
.DI8(di[8]),
.DI7(di[7]),
.DI6(di[6]),
.DI5(di[5]),
.DI4(di[4]),
.DI3(di[3]),
.DI2(di[2]),
.DI1(di[1]),
.DI0(di[0]),
.AA4(wa[4]),
.AA3(wa[3]),
.AA2(wa[2]),
.AA1(wa[1]),
.AA0(wa[0]),
.AB4(ra[4]),
.AB3(ra[3]),
.AB2(ra[2]),
.AB1(ra[1]),
.AB0(ra[0]),
.CSA(csa),
.CSB(csb),
.BEA(clk),
.BEB(~vclk),
.TBEA(1'b0),
.TBEB(1'b0),
.TEST(1'b0),
.BUB(1'b1)
);
endmodule