/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: vi_sync_fsm.v,v 1.4 2003/01/24 23:07:37 berndt Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	vi_sync_fsm
// description:	Sync generator FSM.
//
// designer:	Phil Gossett
// date:	6/16/95
//
////////////////////////////////////////////////////////////////////////

module vi_sync_fsm (vclk, reset_l,
	type, serrate, aa_mode, pixel_adv, origin, width,
	hsync_width, burst_width, vsync_width, burst_start,
	v_sync_period, h_sync_period, leap_pattern,
	hsync_leap_b, hsync_leap_a, h_video_end, h_video_start,
	v_video_end, v_video_start, v_burst_end, v_burst_start,
	x_scale, y_scale, x_offset, y_offset,
	block_addr, hfrac, vfrac, v_current,
	span_sel, pixel_addr, pixel_sync, horizontal_flag,
	h_blank_flag, a_blank_flag, p_blank_flag, v_blank_flag);

input vclk;
input reset_l;
input [1:0] type;
input serrate;
input [1:0] aa_mode;
input [3:0] pixel_adv;
input [23:0] origin;		// bytes
input [11:0] width;		// pixels
input [7:0] hsync_width;	// pixels
input [7:0] burst_width;	// pixels
input [3:0] vsync_width;	// half lines
input [9:0] burst_start;	// pixels
input [9:0] v_sync_period;	// half lines
input [11:0] h_sync_period;	// clocks
input [4:0] leap_pattern;	// fields
input [11:0] hsync_leap_b;	// clocks
input [11:0] hsync_leap_a;	// clocks
input [9:0] h_video_end;	// pixels
input [9:0] h_video_start;	// pixels
input [9:0] v_video_end;	// half lines
input [9:0] v_video_start;	// half lines
input [9:0] v_burst_end;	// half lines
input [9:0] v_burst_start;	// half lines
input [11:0] x_scale;		// 2.10
input [11:0] y_scale;		// 2.10
input [11:0] x_offset;		// 2.10
input [11:0] y_offset;		// 2.10

output [23:0] block_addr;
output [9:0] hfrac;
output [9:0] vfrac;
output [9:0] v_current;
output [1:0] span_sel;
output [6:0] pixel_addr;
output [7:0] pixel_sync;
output horizontal_flag;
output h_blank_flag;
output a_blank_flag;
output p_blank_flag;
output v_blank_flag;

// outputs
reg [23:0] block_addr;
reg [9:0] v_current;
reg [1:0] span_sel;
reg horizontal_flag;
reg h_blank_flag;
reg a_blank_flag;
reg p_blank_flag;
reg v_blank_flag;

reg [11:0] h_current;
reg [11:0] a_current;
reg [11:0] p_current;
reg [2:0] l_current;
reg f_current;
reg [19:0] advance_acc;	// 10.10
reg [19:0] pixel_acc;	// 10.10
reg [19:0] line_acc;	// 10.10
reg [19:0] width_acc;	// 20.0

reg h_burst_flag;
reg v_burst_flag;
reg horizontal_next;
reg v_equ_next;
reg vertical_next;
reg v_equ_flag;
reg vertical_flag;
reg composite_flag;
reg stall;
reg unblank_1d;
reg unblank_2d;
reg unblank_3d;
reg [1:0] type_1d;
reg [1:0] type_2d;
reg [1:0] type_3d;
reg [1:0] type_4d;
reg [1:0] line_delta;

wire blank_flag;
wire burst_flag;
wire hsync_flag;
wire [21:0] comp_line;
wire [11:0] comp_pixel;
wire [11:0] pre_h_current;
wire [11:0] pre_a_current;
wire [11:0] pre_p_current;
wire [9:0] pre_v_current;
wire [2:0] pre_l_current;
wire pre_f_current;
wire [1:0] pre_span_sel;
wire [7:0] blank_adv;

assign blank_flag = h_blank_flag || v_blank_flag;
assign burst_flag = h_burst_flag && v_burst_flag;
assign hsync_flag = (type != 0) && horizontal_flag;
assign pixel_sync = {blank_flag, stall, stall,
	!vertical_flag, !burst_flag, !hsync_flag, !composite_flag,
	stall};
assign hfrac = pixel_acc[9:0];
assign vfrac = line_acc[9:0];
assign pixel_addr = pixel_acc[16:10];
assign comp_line  = !type[0] ? {width_acc[19:0],1'b0} :
			       {width_acc[19:0],2'b0};
assign comp_pixel = !type[0] ? {advance_acc[19:10],1'b0} :
			       {advance_acc[19:10],2'b0};
assign pre_h_current = h_current + 1;
assign pre_a_current = a_current + 1;
assign pre_p_current = p_current + 1;
assign pre_v_current = v_current + 1;
assign pre_l_current = l_current + 1;
assign pre_f_current = f_current + 1;
assign pre_span_sel  = span_sel  + 1;
assign blank_adv = (x_scale > 12'h200) ?	// > 1/2 scale
	                       (!aa_mode[1] ? (       !type[0] ? 16 :
								 8) :
				      (!aa_mode[0] ? (!type[0] ? 32 :
								 16) :
						     (!type[0] ? 64 :
								 32))) :
	                       (!aa_mode[1] ? (       !type[0] ? 32 :
								 16) :
				      (!aa_mode[0] ? (!type[0] ? 64 :
								 32) :
						     (!type[0] ? 128 :
								 64)));

reg [19:0] pre_advance_acc;
always @(advance_acc or x_scale) begin : adv_block
   pre_advance_acc = advance_acc + x_scale; // synopsys label aa
   end


reg [19:0] pre_pixel_acc;
always @(pixel_acc or x_scale) begin : pix_block
   pre_pixel_acc = pixel_acc + x_scale; // synopsys label pa
   end


reg [19:0] pre_line_acc;
always @(line_acc or y_scale) begin : lin_block
   pre_line_acc = line_acc + y_scale; // synopsys label la
   end


reg [19:0] pre_width_acc;
always @(width_acc or width or line_delta) begin : pwa_block
   pre_width_acc  = width_acc + (width * line_delta); // synopsys label wa
   end


wire [23:0] next_block_addr;
// DW02_sum #(3, 24) U1({origin, {2'b0, comp_line}, {12'b0, comp_pixel}},
// 		     next_block_addr);
assign next_block_addr = origin + comp_line + comp_pixel;

always @(posedge vclk)
   begin
   if (reset_l == 1'b0)
      begin
      // resetable registers
      h_current <= 0;	// 1/4 pixels
      a_current <= 0;
      p_current <= 0;
      v_current <= 0;
      l_current <= 0;
      f_current <= 0;
      span_sel <= 3;	// start with sync
      stall <= 0;	// flush pipe
      horizontal_flag <= 1;
      horizontal_next = 1;	// note: blocking assignment
      h_blank_flag <= 1;
      a_blank_flag <= 1;
      p_blank_flag <= 1;
      v_blank_flag <= 1;
      advance_acc <= 0;
      pixel_acc <= 0;
      line_acc <= 0;
      width_acc <= 0;
      h_burst_flag <= 0;
      v_burst_flag <= 0;
      v_equ_next = 1;		// note: blocking assignment
      vertical_next = 1;	// note: blocking assignment
      v_equ_flag <= 1;
      vertical_flag <= 1;
      composite_flag <= 1;
      unblank_1d <= 0;
      unblank_2d <= 0;
      unblank_3d <= 0;
      type_1d <= 0;
      type_2d <= 0;
      type_3d <= 0;
      type_4d <= 0;
      line_delta <= 0;
      block_addr <= 0;
      end
   else
      begin
      // block_addr <= 24'hFFFFF8 & (origin + comp_line + comp_pixel);
      block_addr <= 24'hFFFFF8 & next_block_addr;
      line_delta <= pre_line_acc[11:10] - line_acc[11:10];
      type_1d <= type;
      type_2d <= type_1d;
      type_3d <= type_2d;
      type_4d <= type_3d;
      unblank_1d <= (type_3d != 0);
      unblank_2d <= unblank_1d;
      unblank_3d <= unblank_2d;
      if (unblank_2d && !unblank_3d)	// reset ctrs on unblank (for tests)
         begin
         h_current <= 0;        // 1/4 pixels
         v_current <= 0;        // 1/2 lines
         f_current <= 0;        // fields (mod 2)
         l_current <= 0;        // fields (mod 5)
         composite_flag <= 1;
         horizontal_next = 1;	// note: blocking assignment
         v_equ_next = 1;	// note: blocking assignment
         vertical_next = 1;	// note: blocking assignment
         span_sel <= 3;
         end
      else
         begin
         horizontal_next = horizontal_flag;	// note: blocking assignment
         v_equ_next = v_equ_flag;		// note: blocking assignment
         vertical_next = vertical_flag;		// note: blocking assignment
         if (type_3d == 0)	// null video after reset
            begin
            v_current <= 0;
            f_current <= 0;
            l_current <= 0;
            stall <= 0;			// flush pipe
            h_blank_flag <= 1;
            a_blank_flag <= 1;
            p_blank_flag <= 1;
            v_blank_flag <= 1;
            h_burst_flag <= 0;
            v_burst_flag <= 0;
            v_equ_next = 0;		// note: blocking assignment
            vertical_next = 0;		// note: blocking assignment
            composite_flag <= 0;
            if (h_current == {hsync_width,2'b0})
               begin
               horizontal_next = 0;	// note: blocking assignment
               end
            else
               begin
               if (h_current == h_sync_period)
                  begin
                  horizontal_next = 1;	// note: blocking assignment
                  end
               end
            if (h_current == h_sync_period)
               begin
               h_current <= 0;
               span_sel <= 3;
               end
            else
               begin
               h_current <= pre_h_current;
               span_sel <= pre_span_sel;
               end
            end
         else
            begin
            stall <= (pixel_acc[11:10] == pre_pixel_acc[11:10]) &&
			type_3d[1] && !h_burst_flag;
            if (h_current == h_sync_period[11:1])
               begin
               if (v_current == v_sync_period)
                  begin
                  v_current <= 0;
                  vertical_next = 1;	// note: blocking assignment
                  end
               else
                  begin
                  v_current <= pre_v_current;
                  if (v_current == vsync_width)
                     begin
                     vertical_next = 0;	// note: blocking assignment
                     end
                  end
               h_current <= pre_h_current;
               span_sel <= pre_span_sel;
               end
            else
               begin
               if (v_current[9:1] == 0)
                  begin
                  case (l_current)
                     0: begin
                        if (h_current == (leap_pattern[4] ? hsync_leap_b :
                                                            hsync_leap_a))
                           begin
                           if (v_current == v_sync_period)
                              begin
                              v_current <= 0;
                              vertical_next = 1; // note: blocking assignment
                              end
                           else
                              begin
                              v_current <= pre_v_current;
                              if (v_current == vsync_width)
                                 begin
                                 vertical_next = 0; // note: blocking assign
                                 end
                              end
                           horizontal_next = 1;	// note: blocking assignment
                           h_current <= 0;
                           span_sel <= 3;
                           end
                        else
                           begin
                           h_current <= pre_h_current;
                           if (h_current == {hsync_width,2'b0})
                              begin
                              horizontal_next = 0; // note: blocking assign
                              end
                           span_sel <= pre_span_sel;
                           end
                        end
                     1: begin
                        if (h_current == (leap_pattern[3] ? hsync_leap_b :
                                                            hsync_leap_a))
                           begin
                           if (v_current == v_sync_period)
                              begin
                              v_current <= 0;
                              vertical_next = 1; // note: blocking assignment
                              end
                           else
                              begin
                              v_current <= pre_v_current;
                              if (v_current == vsync_width)
                                 begin
                                 vertical_next = 0; // note: blocking assign
                                 end
                              end
                           horizontal_next = 1;	// note: blocking assignment
                           h_current <= 0;
                           span_sel <= 3;
                           end
                        else
                           begin
                           h_current <= pre_h_current;
                           if (h_current == {hsync_width,2'b0})
                              begin
                              horizontal_next = 0; // note: blocking assign
                              end
                           span_sel <= pre_span_sel;
                           end
                        end
                     2: begin
                        if (h_current == (leap_pattern[2] ? hsync_leap_b :
                                                            hsync_leap_a))
                           begin
                           if (v_current == v_sync_period)
                              begin
                              v_current <= 0;
                              vertical_next = 1; // note: blocking assignment
                              end
                           else
                              begin
                              v_current <= pre_v_current;
                              if (v_current == vsync_width)
                                 begin
                                 vertical_next = 0; // note: blocking assign
                                 end
                              end
                           horizontal_next = 1;	// note: blocking assignment
                           h_current <= 0;
                           span_sel <= 3;
                           end
                        else
                           begin
                           h_current <= pre_h_current;
                           if (h_current == {hsync_width,2'b0})
                              begin
                              horizontal_next = 0; // note: blocking assign
                              end
                           span_sel <= pre_span_sel;
                           end
                        end
                     3: begin
                        if (h_current == (leap_pattern[1] ? hsync_leap_b :
                                                            hsync_leap_a))
                           begin
                           if (v_current == v_sync_period)
                              begin
                              v_current <= 0;
                              vertical_next = 1; // note: blocking assignment
                              end
                           else
                              begin
                              v_current <= pre_v_current;
                              if (v_current == vsync_width)
                                 begin
                                 vertical_next = 0; // note: blocking assign
                                 end
                              end
                           horizontal_next = 1;	// note: blocking assignment
                           h_current <= 0;
                           span_sel <= 3;
                           end
                        else
                           begin
                           h_current <= pre_h_current;
                           if (h_current == {hsync_width,2'b0})
                              begin
                              horizontal_next = 0; // note: blocking assign
                              end
                           span_sel <= pre_span_sel;
                           end
                        end
                     4: begin
                        if (h_current == (leap_pattern[0] ? hsync_leap_b :
                                                            hsync_leap_a))
                           begin
                           if (v_current == v_sync_period)
                              begin
                              v_current <= 0;
                              vertical_next = 1; // note: blocking assignment
                              end
                           else
                              begin
                              v_current <= pre_v_current;
                              if (v_current == vsync_width)
                                 begin
                                 vertical_next = 0; // note: blocking assign
                                 end
                              end
                           horizontal_next = 1;	// note: blocking assignment
                           h_current <= 0;
                           span_sel <= 3;
                           end
                        else
                           begin
                           h_current <= pre_h_current;
                           if (h_current == {hsync_width,2'b0})
                              begin
                              horizontal_next = 0; // note: blocking assign
                              end
                           span_sel <= pre_span_sel;
                           end
                        end
                  endcase
                  end
               else
                  begin
                  if (h_current == h_sync_period)
                     begin
                     if (v_current == v_sync_period)
                        begin
                        v_current <= 0;
                        vertical_next = 1; // note: blocking assignment
                        end
                     else
                        begin
                        v_current <= pre_v_current;
                        if (v_current == vsync_width)
                           begin
                           vertical_next = 0;	// note: blocking assignment
                           end
                        end
                     horizontal_next = 1;	// note: blocking assignment
                     h_current <= 0;
                     span_sel <= 3;
                     end
                  else
                     begin
                     h_current <= pre_h_current;
                     if (h_current == {hsync_width,2'b0})
                        begin
                        horizontal_next = 0;	// note: blocking assignment
                        end
                     span_sel <= pre_span_sel;
                     end
                  end
               end
            if ((v_current == v_sync_period) &&
		((h_current == h_sync_period) ||
                 (h_current == h_sync_period[11:1])))
               begin
               f_current <= pre_f_current;
               if (l_current[2])
                  begin
                  l_current <= 0;
                  end
               else
                  begin
                  l_current <= pre_l_current;
                  end
               end
            if (h_current == h_sync_period)
               begin
               a_current <= {blank_adv,2'b0};
               p_current <= {pixel_adv,2'b0};
               end
            else
               begin
               a_current <= pre_a_current;
               p_current <= pre_p_current;
               end
            if ((v_current == {vsync_width,1'b1}) &&
	        ((h_current == h_sync_period) ||
		 (h_current == h_sync_period[11:1])))
               begin
               v_equ_next = 0;		// note: blocking assignment
               end
            else
               begin
               if ((v_current == (v_sync_period - vsync_width - 1)) &&
		   ((h_current == h_sync_period) ||
		    (h_current == h_sync_period[11:1])))
                  begin
                  v_equ_next = 1;	// note: blocking assignment
                  end
               end
            if (serrate)
               begin
               if (vertical_next)
                  begin
                  if ((h_current == h_sync_period) ||
		      (h_current == h_sync_period[11:1]))
                     begin
                     composite_flag <= 1;
                     end
                  else
                     begin
                     if ((h_current == (h_sync_period[11:1] -
   				     {hsync_width,2'b0})) ||
                         (h_current == (h_sync_period -
   				     {hsync_width,2'b0})))
                        begin
                        composite_flag <= 0;
                        end
                     end
                  end
               else
                  begin
                  if (v_equ_next)
                     begin
                     if ((h_current == h_sync_period) ||
			 (h_current == h_sync_period[11:1]))
                        begin
                        composite_flag <= 1;
                        end
                     else
                        begin
                        if ((h_current == {hsync_width,1'b0}) ||
                            (h_current == (h_sync_period[11:1] +
   					{hsync_width,1'b0})))
                           begin
                           composite_flag <= 0;
                           end
                        end
                     end
                  else
                     begin
                     if (h_current == {hsync_width,2'b0})
                        begin
                        composite_flag <= 0;
                        end
                     else
                        begin
                        if (h_current == h_sync_period)
                           begin
                           composite_flag <= 1;
                           end
                        end
                     end
                  end
               end
            else
               begin
               if (vertical_next)
                  begin
                  if (h_current == h_sync_period)
                     begin
                     composite_flag <= 1;
                     end
                  else
                     begin
                     if (h_current == (h_sync_period - {hsync_width,2'b0}))
                        begin
                        composite_flag <= 0;
                        end
                     end
                  end
               else
                  begin
                  if (h_current == {hsync_width,2'b0})
                     begin
                     composite_flag <= 0;
                     end
                  else
                     begin
                     if (h_current == h_sync_period)
                        begin
                        composite_flag <= 1;
                        end
                     end
                  end
               end
            if ((v_current[9:1] == v_video_end[9:1]) &&
	        (h_current == h_sync_period))
               begin
               v_blank_flag <= 1;
               end
            else
               begin
               if ((v_current[9:1] == v_video_start[9:1]) &&
		   (h_current == h_sync_period))
                  begin
                  v_blank_flag <= !type_3d[1];
                  end
	       end
            if (h_current == {h_video_end,2'b0})
               begin
               h_blank_flag <= 1;
               end
            else
               begin
               if (h_current == {h_video_start,2'b0})
                  begin
                  h_blank_flag <= !type_3d[1];
                  end
               end
            if (a_current == {h_video_end,2'b0})
               begin
               a_blank_flag <= 1;
               end
            else
               begin
               if (a_current == {h_video_start,2'b0})
                  begin
                  a_blank_flag <= !type_3d[1];
                  end
               end
            if (p_current == {h_video_end,2'b0})
               begin
               p_blank_flag <= 1;
               end
            else
               begin
               if (p_current == {h_video_start,2'b0})
                  begin
                  p_blank_flag <= !type_3d[1];
                  end
               end
            if ((h_current == h_sync_period) &&
                (v_blank_flag))
	       begin
               line_acc <= y_offset;
	       width_acc <= 0;
	       end
            else
               begin
               if (h_current == h_sync_period)
                  begin
                  width_acc <= pre_width_acc;
                  line_acc <= pre_line_acc;
                  end
               end
	    if (h_blank_flag)
	       begin
               pixel_acc <= x_offset;
	       end
            else
               begin
	       if (span_sel == 3)
                  begin
                  pixel_acc <= pre_pixel_acc;
                  end
               end
	    if (p_blank_flag)
	       begin
               advance_acc <= x_offset;
	       end
            else
               begin
	       if (span_sel == 3)
                  begin
                  advance_acc <= pre_advance_acc;
                  end
               end
            if ((v_current == v_burst_end) &&
		((h_current == h_sync_period) ||
		 (h_current == h_sync_period[11:1])))
               begin
               v_burst_flag <= 0;
               end
            else
               begin
               if ((v_current == v_burst_start) &&
		   ((h_current == h_sync_period) ||
		    (h_current == h_sync_period[11:1])))
                  begin
                  v_burst_flag <= 1;
                  end
               end
            if (h_current == ({burst_start,2'b0} + {burst_width,2'b0}))
               begin
               h_burst_flag <= 0;
               end
            else
               begin
               if (h_current == {burst_start,2'b0})
                  begin
                  h_burst_flag <= 1;
                  end
               end
            end
         end
      horizontal_flag <= horizontal_next;
      v_equ_flag <= v_equ_next;
      vertical_flag <= vertical_next;
      end
   end

endmodule // vi_sync_fsm


// synopsys translate_off
/*
module DW02_sum(in_vector, sum);

parameter NINPUTS = 'bx;
parameter WORDLENGTH = 'bx;

input [NINPUTS*WORDLENGTH-1:0] in_vector;
output [WORDLENGTH-1:0] sum;

integer i;
reg [WORDLENGTH-1:0] sum, addend;

always @(in_vector) begin
   sum = 0;
   for (i = 0; i < NINPUTS; i = i + 1) begin
      addend = in_vector >> (i * WORDLENGTH); // get the correct number of bits
      sum = sum + addend;                     // accumulate the result
      end
   end

endmodule
*/
// synopsys translate_on