/*
*************************************************************************
*									*
*  Project Reality							*
*									*
*  module:	dp_regmx16.v						*
*  description:	16 bit register with 4 to 1 mux to implement		*
*		2 to 1 data mux, reset and clock enable functionalty.	*
*		If both selects are low or both high then register	*
*		its old value.						*
*									*
*		The mux cell used is the high performance j_me41 cells.*
*									*
*  designer:	Brian Ferguson						*
*  date:	3/17/95							*
*									*
*************************************************************************
*/

module dp_regmx16 ( clk, reset_l, input0, input1, select, output_data );

input	clk;
input	reset_l;
input	[15:0]	input0;
input	[15:0]	input1;
input	[1:0]	select;

output	[15:0]	output_data;
reg	[15:0]	output_data;

always @(posedge clk)
begin
	if(reset_l == 1'b0)
		output_data <= 16'd0;
	else if (&select)
		output_data <= 16'd0;
	else if(select[0])
		output_data <= input0;
	else if(select[1])
		output_data <= input1;
end

endmodule  //  dp_regmx16