// Module instances modified by /home/rws/workarea/rf/sw/bbplayer/tools/necprimfix 
//
//    1 instance of an02d1h changed to j_an02.
//    1 instance of ao01d2 changed to j_ao01.
//    7 instances of mx21d1h changed to j_mx21.
//    2 instances of ni01d7 changed to j_ni01.
//

/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vuctlsl.v,v 1.3 2003/01/24 23:07:37 berndt Exp $


/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vuctlsl						*
*	Description:	vector unit control slice for individual	* 
*			vector unit datapath.  This module is		*
*			instantiated eight times in vuctl, once		*
*			for each vector unit datapath.			*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		8/13/94						*
*									*
*************************************************************************
*/

// vuctlsl.v: 	RSP vector unit control

`timescale 1ns / 10ps

module	vuctlsl (	clk, reset_l, 

			su_instvld_rd,

			vct_instvld_mu, 
			vct_pralucmpvt_mu,
			vct_addcop_mu, vct_subcop_mu,
			vct_addop_mu, vct_subop_mu,
			vct_vs_sgnmu_mu, vct_vt_sgnmu_mu,
			vct_stltop_mu, vct_steqop_mu, vct_stneop_mu,
			vct_stgeop_mu, vct_stchop_mu, vct_stclop_mu, 
			vct_stchrop_mu, vct_stcrop_mu,
			vct_substclop_mu,
			vct_absop_mu,
			vct_rndop_mu,
			vct_rndpop_mu, vct_rndnop_mu, 
			vct_mulqop_mu,
			vct_mulfop_mu,
			vct_muluop_mu,
			vct_vseqone_mu,
			vct_aluprecin_rd,
			vct_cryoutld_mu, vct_cmpcdld_mu, vct_cmpcdadld_mu,
			vdp_vs_zero_mu, vdp_vt_zero_mu,
			vdp_vs_sign_mu,
			vdp_vt_sign_mu,
			vdp_aluovr_mu, vdp_aluco_mu, 
			vdp_aluzero_mu, vdp_aluone_mu, 
			vct_prsmlwrsl_mu,

			vct_instvld_ac,
			vct_prcslwbsl_ac,
			vct_prcsupbsl_ac,
			vct_prcsupcen_ac,
			vct_stchop_ac, vct_stclop_ac,
			vct_stnclrdop_ac, vct_stclrdop_ac,
			vct_multtypop_ac,
			vct_rndop_ac,
			vct_macqop_ac,
			vct_mudlop_ac, vct_madlop_ac,
			vct_mulfop_ac, vct_muluop_ac,
			vct_rndpop_ac, vct_rndnop_ac, 

			vct_absop_ac,
			vct_vseqone_ac,
			vdp_addlwco_ac, vdp_addlwov_ac,
			vdp_csupco_ac, vdp_addupco_ac,
			vmu_co_clal_ac, vmu_co_clah_ac,

			vct_praclwsl_ac, vct_pracupsl_ac,
			vct_multactyp_ac, vct_multincop_ac,


			su_wrcmpcd_wb, su_wrcmpcdad_wb, su_wrcryout_wb,
			su_datainlo_wb, su_datainhi_wb,	
			vdp_accbit15_wb, vdp_accbit21_wb, 
			vdp_accbit31_wb, vdp_accbit47_wb, 
			vdp_acchizero_wb, vdp_acchione_wb,
			vdp_accmizero_wb,
			vct_acchighsl_wb, vct_accmidsl_wb,
			vct_acclowsl_wb, vct_accshftsl_wb,
			vct_divrsltsl_wb,
			vct_clpsgn16_wb, vct_clpsgn31_wb,
			vct_clpsgn32_wb, vct_clpuns31_wb,
			vct_adscl16op_wb, 

			vct_alucin_mu, 
			vct_alucmpvt_mu,
			vct_compvt_mu,
			vct_smlwrsl_mu,

			vct_cryout_ac, vct_opdneql_ac,
			vct_cmpcdlo_ac, vct_cmpcdhi_ac,
			vct_cmpcdad_ac,

			vct_rndvlu_ac,
			vct_cslwbsl_ac,
			vct_addlwci_ac,
			vct_csupbsl_ac,
			vct_csupcen_ac,
			vct_incrdwn_ac, vct_incrci_ac,
			vct_incrmxsl_ac,
			vct_aclwsl_ac, vct_acupsl_ac,

			vct_rsltsl_wb,
			vct_clprslt_wb

		);

/*
*	The following signals are the input signals to the 
*	vector unit control block.
*
*	The first group are input signals to the control block 
*	which provide general control such as clocks, reset
*	hold and instruction decoding.
*
*/


	input	clk;			/* vu clock */
	input	reset_l;		/* active low reset signal */

/*
*	The following are signals to the control slice from the scalar unit 
*	directly.	
*/
	input	su_instvld_rd;		/* valid CP2 instruction for vu */

/*
*	The next group are input signals to the control block from
*	the register file read stage of the vector unit datapaths.
*/

/*
*	The next group are input signals to the control slice from
*	the multiply stage of the vector unit control block.
*/
	input	vct_instvld_mu;			/* valid instruction in multiply stage */
	input	vct_pralucmpvt_mu;	/* complement vt for subtact in ALU in MU stage */
	input	vct_addcop_mu;			/* ADDC instruction in MU */
	input	vct_subcop_mu;			/* SUBC instruction in MU */
	input	vct_addop_mu;			/* ADD instruction in MU */
	input	vct_subop_mu;			/* SUB instruction in MU */
	input	vct_vs_sgnmu_mu;		/* Multiply instruction with operand s signed */
	input	vct_vt_sgnmu_mu;		/* Multiply instruction with operand t signed */

	input	vct_stltop_mu;			/* VS < VT select instruction in MU stage */
	input	vct_steqop_mu;			/* VS == VT select instruction in MU stage */
	input	vct_stneop_mu;			/* VS != VT select instruction in MU stage */
	input	vct_stgeop_mu;			/* VS >= VT select instruction in MU stage */
	input	vct_stchop_mu;			/* -VT <= VS <= VT SP select instruction 2's comp */
	input	vct_stclop_mu;			/* -VT <= VS <= VT DP select instruction 2's comp */
	input	vct_stcrop_mu;			/* -VT <= VS <= VT select instruction 1's comp */
	input	vct_stchrop_mu;			/* -VT <= VS <= VT select instruction 2's or 1's comp */
	input	vct_substclop_mu;	/* sub or -VT<=VS<=VT select instruction 2's comp double precision*/
	input	vct_absop_mu;			/* ABS instruction in MU stage. */
	input	vct_rndop_mu;			/* RNDP or RNDN instruction in MU stage. */
	input	vct_rndpop_mu;			/* RNDP instruction in MU stage. */
	input	vct_rndnop_mu;			/* RNDN instruction in MU stage. */
	input	vct_mulqop_mu;			/* MULQ instruction in MU stage. */
	input	vct_mulfop_mu;			/* MULF instruction in MU stage. */
	input	vct_muluop_mu;			/* MULU instruction in MU stage. */
	input	vct_vseqone_mu;			/* vs field of instruction equal to 1 in MU */
	input	vct_aluprecin_rd;		/* carry in to alu decoded subtract instructions */

	input	vct_cryoutld_mu;		/* Load enable for Vector carry out/equal to register */
	input	vct_cmpcdld_mu;			/* Load enable for vector compare code register */
	input	vct_cmpcdadld_mu;		/* Load enable for vector compare add register */

/*
*	The next group are input signals to the control block from
*	the multiply stage of the vector unit datapaths.
*/
	input	vdp_vs_zero_mu;			/* vs operand is equal to zero */
	input	vdp_vt_zero_mu;			/* vt operand is equal to zero */
	input	vdp_vs_sign_mu;			/* vs sign bit */
	input	vdp_vt_sign_mu;			/* vt sign bit */
	input	vdp_aluovr_mu;			/* overflow bit from alu */
	input	vdp_aluco_mu;			/* carry out from alu */
	input	vdp_aluzero_mu;			/* alu result is equal to zero */
	input	vdp_aluone_mu;			/* alu result is equal to all ones (minus one) */

	input	[1:0]	vct_prsmlwrsl_mu;	/* pre-selects for multiply lower sum out */

/*
*	The next group are input signals to the control slice from
*	the accumulate stage of the vector unit control block.
*/
	input	[2:0]	vct_prcslwbsl_ac;	/* MU stage mux select for input b of lower CSA */
	input	[1:0]	vct_prcsupbsl_ac;	/* MU stage mux select for input b of upper CSA */
	input	vct_prcsupcen_ac;		/* predecoded signal for enabling c input of upper csa */

	input	vct_instvld_ac;			/* valid instruction in accumulate stage */
	input	vct_multtypop_ac;		/* Multiply type op in AC */
	input	vct_rndop_ac;			/* RNDP or RNDN instruction in AC stage. */
	input	vct_macqop_ac;			/* Mucq instruction in AC */
	input	vct_mudlop_ac;			/* MUDL instruction in AC stage. */
	input	vct_madlop_ac;			/* MADL instruction in AC stage. */
	input	vct_mulfop_ac;			/* MULF instruction in AC stage. */
	input	vct_muluop_ac;			/* MULU instruction in AC stage. */
	input	vct_rndpop_ac;			/* RNDP instruction in AC stage. */
	input	vct_rndnop_ac;			/* RNDN instruction in AC stage. */

	input	vct_stchop_ac;		/* -VT<=VS<=VT select op 2's comp single precison */
	input	vct_stclop_ac;		/* -VT<=VS<=VT select op 2's comp double precison */

	input	vct_stnclrdop_ac;		/* Select instruction that is not CL, CLD or CR */
	input	vct_stclrdop_ac;		/* Select instruction that is CL, CLD or CR */

	input	vct_absop_ac;			/* ABS instruction in AC stage. */
	input	vct_vseqone_ac;			/* vs field of instruction equal to 1 in AC */

	input	[1:0]	vct_praclwsl_ac;	/* selects input for lower mux of accumulator */
	input	[1:0]	vct_pracupsl_ac;	/* selects input for upper mux of accumulator */
	input	vct_multactyp_ac;		/* mux select for incrementer output all vectors */
	input	vct_multincop_ac;		/* MACF, MACU, MADL, MADM and MADN type ops */



/*
*	The next group are input signals to the control slice from
*	the accumulate stage of the vector unit datapaths.
*/
	input	vdp_addlwco_ac;		/* carry out from low adder */
	input	vdp_addlwov_ac;		/* overflow from low adder */
	input	vdp_csupco_ac;		/* carry out from high csa */
	input	vdp_addupco_ac;		/* carry out from high adder */
	input	vmu_co_clal_ac;		/* carry out from 16 bit product of multiplier */
	input	vmu_co_clah_ac;		/* false carry out from multiplier */

/*
*	The next group are input signals to the control slice from
*	the Scalar unit.
*/
	input	su_wrcmpcd_wb;		/* write vector compare code register */
	input	su_wrcmpcdad_wb;	/* write vector compare add register */
	input	su_wrcryout_wb;		/* write vector carry out register */
	input	su_datainlo_wb;		/* Data in to low half of VCC, VCA and VCO registers */
	input	su_datainhi_wb;		/* Data in to high half of VCC, VCA and VCO registers */
/*
*	The next group are input signals to the control slice from
*	the writeback stage of the vector unit datapaths.
*/
	input	vdp_accbit15_wb;	/* bit 15 of accumulator used to determine sign */
	input	vdp_accbit21_wb;	/* bit 21 of accumulator used to determine sign */
	input	vdp_accbit31_wb;	/* bit 31 of accumulator used to determine sign */
	input	vdp_accbit47_wb;	/* bit 47 of accumulator used to determine sign */

	input	vdp_acchizero_wb;		/* 47:32 of accumulator equal zero */
	input	vdp_acchione_wb;		/* 47:32 of accumulator equal one */
	input	vdp_accmizero_wb;		/* 31:16 of accumulator equal zero */


/*
*	The next group are input signals to the control slice from
*	the writeback stage of the vector unit control.
*/
	input	vct_acchighsl_wb;	/* select high portion of accumulator */
	input	vct_accmidsl_wb;	/* select mid portion of accumulator */
	input	vct_acclowsl_wb;	/* select low portion of accumulator */
	input	vct_accshftsl_wb;	/* select shifted high/mid portion of accumulator */
	input	vct_divrsltsl_wb;	/* select result from divide unit */
	input	vct_clpsgn16_wb;	/* instruction requiring signed clamping on 15 to 0 */
	input	vct_clpsgn31_wb;	/* instruction requiring signed clamping on 31 to MSB */
	input	vct_clpsgn32_wb;	/* instruction requiring signed clamping on 32 to MSB */
	input	vct_clpuns31_wb;	/* instruction requiring unsigned clamping on 31 to MSB */
	input	vct_adscl16op_wb;	/* 16 bit ADD, SUB or ABS instruction in WB */


/*
*	The following signals are the output signals for the 
*	vector unit control block.
*
*/

/*
*	The next group are output control signals for the
*	multiply stage of the vector unit datapath.
*/

	output	vct_alucin_mu;			/* carry in to alu vector */
	output	vct_alucmpvt_mu;		/* complement vt subtact in ALU */
	output	vct_compvt_mu;			/* complement vt for writing -VT for CL, CLD, CR */

	output	[1:0]	vct_smlwrsl_mu;		/* selects for multiply lower sum out all vectors */


/*
*	The next group are output control signals for the
*	accumulate stage of the vector unit datapath.
*/

	output	vct_cryout_ac;		/* Carry out flag from Vector Carry Out register */
	output	vct_opdneql_ac;		/* Data equal flag from Vector Carry Out register */
	output	vct_cmpcdlo_ac;		/* Flag for low half of Vector Compare Code register */
	output	vct_cmpcdhi_ac;		/* Flag for high half of Vector Compare Code register */
	output	vct_cmpcdad_ac;		/* Flag for Vector Compare Add register */

	output	[3:0]	vct_rndvlu_ac;		/* round value for multiplies */
	output	[1:0]	vct_cslwbsl_ac;		/* selects for input b of lower csa  */
	output	vct_addlwci_ac;			/* carry in to lower adder  */

	output	[1:0]	vct_csupbsl_ac;		/* selects for input b of upper csa  */
	output	vct_csupcen_ac;			/* output c enable for upper csa */
	output	vct_incrdwn_ac;			/* increment/decrement control signal  */
	output	vct_incrci_ac;			/* increment/decrement enable signal  */
	output	vct_incrmxsl_ac;		/* mux select for incrementer output */

	output	[1:0]	vct_aclwsl_ac;		/* selects input for lower mux of accumulator */
	output	[1:0]	vct_acupsl_ac;		/* selects input for upper mux of accumulator */


/*
*	The next group are output control signals for the
*	write back stage of the vector unit datapath.
*/


	output	[2:0]	vct_rsltsl_wb;		/* selects for result mux  */

	output	[2:0]	vct_clprslt_wb;		/* clamp value for all clamping */


/*
*	The following are the flip-flops used by the vector unit control block.
*	The flags contain such information as the signs of the input operands,
*	sign of the result of ALU or ADD/SUB operations in the mu stage and
*	
*
*	All flip-flops use the asdffen flip-flop from Compasses's library.
*	asdffen #(size, reset_val) instance_name (q, d, load_enable, clk, reset_l);
*
*/

/*
*	Operand sign flip-flops
*/

/*
*	This group of signals are for the pipechain of the operand signs.
*/
	wire	vct_vs_sign_ac;		/* sign of s operand in AC */
	wire	vct_vt_sign_ac;		/* sign of t operand in AC */

	asdffen #(1, 0)	vctopssignffac (vct_vs_sign_ac, vdp_vs_sign_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctoptsignffac (vct_vt_sign_ac, vdp_vt_sign_mu, vct_instvld_mu, clk, reset_l );

 

/*
*	Overflow detection from ALU - used for clamping. 
*/
	wire	vct_aluovfl_mu;		/* overflow flag from ALU in MU stage */
	wire	vct_aluovflrg_ac;	/* overflow flag from ALU piped to AC stage */
	wire	vct_aluovfl_ac;		/* overflow flag from ALU piped and adder in AC stage */
	wire	vct_aluovfl_wb;		/* overflow flag from ALU piped to WB stage */

	assign	vct_aluovfl_mu =	( vct_addop_mu || vct_subop_mu ) && 
					( vdp_aluco_mu ^ vdp_aluovr_mu ) ;

	asdffen #(1, 0)	vctaluovflffac (vct_aluovflrg_ac, vct_aluovfl_mu, vct_instvld_mu, clk, reset_l );

/*
*	Since 2's complementing of abs instruction is done in ac state we need to keep track of overflow
*	from ac stage to ensure proper clamping when doing -VT when VT=8000.  We want to clamp to max
*	sign value of 7fff.
*/

	assign	vct_aluovfl_ac =	( vct_absop_ac && (vdp_addlwco_ac ^ vdp_addlwov_ac) ) ||
					( vct_stclrdop_ac && (vct_vs_sign_ac ^ vct_vt_sign_ac) &&
					  (vdp_addlwco_ac ^ vdp_addlwov_ac)
					) ||
					vct_aluovflrg_ac ;


	asdffen #(1, 0)	vctaluovflffwb (vct_aluovfl_wb, vct_aluovfl_ac, vct_instvld_ac, clk, reset_l );


/*
*	Multiplication product sign flip-flop
*/

	wire	vct_muvs_sign_mu;	/* sign of multiply/round/vcl VS operand in MU stage */
	wire	vct_muvt_sign_mu;	/* sign of multiply/round/vcl VT operand in MU stage */

	wire	vct_pdtsign_mu;		/* sign of multiply/round/vcl product in MU stage */
	wire	vct_pdtsign_ac;		/* sign of multiply/round/vcl product in AC stage */


	assign	vct_muvs_sign_mu =	vct_vs_sgnmu_mu && vdp_vs_sign_mu ;

	assign	vct_muvt_sign_mu =	vct_vt_sgnmu_mu && vdp_vt_sign_mu ;

	assign	vct_pdtsign_mu =	( vct_rndop_mu && vdp_vt_sign_mu ) ||
					( vct_stclop_mu && vct_cryout_ac ) ||
					( ( vct_stchop_mu || vct_stcrop_mu ) && 
					  ( vdp_vs_sign_mu ^ vdp_vt_sign_mu ) 
					) ||
					( !vdp_vs_zero_mu && !vdp_vt_zero_mu &&	/* if either opnd */
					  (vct_muvs_sign_mu ^ vct_muvt_sign_mu) /* 0 then positive */
					) ;
					


	asdffen #(1, 0)	vctpdtsignffac (vct_pdtsign_ac, vct_pdtsign_mu, vct_instvld_mu, clk, reset_l );



/*
*	Vector Carry Out flip-flops
*/
	wire	vct_cndexrsgn_mu;	/* Exor of VS and VT sign bits for use in CL and CR */
	wire	vct_cryout_mu;		/* Data input to low bit of Vector Carry Out register */
	wire	vct_opdneql_mu;		/* Data input to high bit of Vector Carry Out register */

	assign	vct_cryout_mu =	( vct_instvld_mu &&
				  ( ( vdp_aluco_mu && vct_addcop_mu ) ||
				    ( !vdp_aluco_mu && vct_subcop_mu ) ||
				    ( vct_cndexrsgn_mu && vct_stchop_mu ) 
				  )
				) ||
				( su_datainlo_wb && su_wrcryout_wb ) ;

			/* Always reset unless addc, subc or move to */

	asdffen #(1, 0)	vctcryoutffac (vct_cryout_ac, vct_cryout_mu, vct_cryoutld_mu, clk, reset_l );

	assign	vct_opdneql_mu = ( vct_instvld_mu && !vdp_aluzero_mu && 
				    ( vct_subcop_mu ||
				      ( !vct_cndexrsgn_mu && vct_stchop_mu ) ||
				      ( vct_cndexrsgn_mu && vct_stchop_mu && !vdp_aluone_mu )
				    )
				 ) ||
				 (  su_datainhi_wb && su_wrcryout_wb ) ;	
			/* Always reset unless addc, subc or move to */

	asdffen #(1, 0)	vctopdneqlffac (vct_opdneql_ac, vct_opdneql_mu, vct_cryoutld_mu, clk, reset_l );


/*
*	Vector Compare Code flip-flops
*/
	wire	vct_cmpcdlo_mu;		/* Data input to low bit of Vector compare code register */
	wire	vct_cmpcdhi_mu;		/* Data input to high bit of Vector compare code register */

	wire	vct_cndvsltvt_mu;	/* Compare condition VS < VT */
	wire	vct_cndvseqvt_mu;	/* Compare condition VS == VT */
	wire	vct_cndvsnevt_mu;	/* Compare condition VS != VT */
	wire	vct_cndvsgevt_mu;	/* Compare condition VS >= VT */
	wire	vct_cndclsplo_mu;	/* Compare condition low single precision -VT<=VS<=VT 2's comp */
	wire	vct_cndcldplo_mu;	/* Compare condition low double precision -VT<=VS<=VT 2's comp */
	wire	vct_cndclsphi_mu;	/* Compare condition high single precision -VT<=VS<=VT 2's comp */
	wire	vct_cndcldphi_mu;	/* Compare condition high double precision -VT<=VS<=VT 2's comp */
	wire	vct_cndcrlo_mu;		/* Compare condition low -VT <= VS <= VT 1's complement */
	wire	vct_cndcrhi_mu;		/* Compare condition high -VT <= VS <= VT 1's complement */
	wire	vct_cndvslenvt_mu;	/* Compare condition VS <= VT */


	assign	vct_cndexrsgn_mu =	vdp_vs_sign_mu ^ vdp_vt_sign_mu ;

	assign	vct_compvt_mu	=	!( vct_absop_mu && vdp_vs_sign_mu ) &&
					!( ( vct_stchop_mu || vct_stcrop_mu ) && vct_cndexrsgn_mu ) &&
					!( vct_stclop_mu && vct_cryout_ac ) ;

	assign	vct_cndvsltvt_mu =	( vdp_vs_sign_mu && !vdp_vt_sign_mu ) ||
					( !vdp_aluco_mu && !vdp_aluzero_mu && !vct_cndexrsgn_mu ) ||
					( vdp_aluzero_mu && !vct_cndexrsgn_mu &&
					  vct_opdneql_ac && vct_cryout_ac
					) ;

	assign	vct_cndvseqvt_mu =	vdp_aluzero_mu && !vct_opdneql_ac && !vct_cndexrsgn_mu ;

	assign	vct_cndvsnevt_mu =	!vdp_aluzero_mu || vct_opdneql_ac || vct_cndexrsgn_mu ;

	assign	vct_cndvsgevt_mu =	( !vdp_vs_sign_mu && vdp_vt_sign_mu ) ||
					( vdp_aluco_mu && !vdp_aluzero_mu && !vct_cndexrsgn_mu ) || 
					( vdp_aluzero_mu && !vct_cndexrsgn_mu &&
					  ( !vct_opdneql_ac || !vct_cryout_ac ) 
					) ;

	assign	vct_cndvslenvt_mu =	!vdp_aluco_mu || vdp_aluzero_mu ;


/* signs different AND VS+VT<=0 */
	assign	vct_cndclsplo_mu =	( !vct_cndexrsgn_mu && vdp_vt_sign_mu ) ||
					( vct_cndexrsgn_mu && vct_cndvslenvt_mu  ) ;

/* signs same AND VS-VT>=0 */
	assign	vct_cndclsphi_mu =	( vct_cndexrsgn_mu && vdp_vt_sign_mu ) ||
					( !vct_cndexrsgn_mu && vdp_aluco_mu ) || 
					( !vct_cndexrsgn_mu && vdp_aluzero_mu ) ;

	assign	vct_cndcldplo_mu =	( ( !vct_cryout_ac || vct_opdneql_ac ) && vct_cmpcdlo_ac ) 
					||  
					( vct_cryout_ac && !vct_opdneql_ac && 
					  vct_cmpcdad_ac && !vdp_aluco_mu 
					)
					||
					( vct_cryout_ac && !vct_opdneql_ac && vdp_aluzero_mu && 
					    ( ( !vct_cmpcdad_ac && !vdp_aluco_mu ) || vct_cmpcdad_ac )
					) ;


	assign	vct_cndcldphi_mu =	( ( vct_cryout_ac || vct_opdneql_ac ) && vct_cmpcdhi_ac ) ||  
					( !vct_cryout_ac && !vct_opdneql_ac && vdp_aluco_mu ) ;
/*	WHY is BORROW INVERSE OF carry??????????????
*					( !vct_cryout_ac && !vct_opdneql_ac && !vdp_aluco_mu ) ;
*/


/* signs different AND VS<=~VT */
	assign	vct_cndcrlo_mu =	( !vct_cndexrsgn_mu && vdp_vt_sign_mu ) ||
					( vct_cndexrsgn_mu && vct_cndvslenvt_mu  ) ;

/* signs same AND VS>=VT */
	assign	vct_cndcrhi_mu =	( vct_cndexrsgn_mu && vdp_vt_sign_mu ) ||
					( !vct_cndexrsgn_mu && vdp_aluco_mu ) ||
					( !vct_cndexrsgn_mu && vdp_aluzero_mu ) ;

/*
*	The data to the vector unit control register is a timing critical path therefore valid
*	is taken into account at the instruction decode level to eliminate it from the critical
*	timing of the data.
*/
	assign	vct_cmpcdlo_mu =	( ( vct_cndvsltvt_mu && vct_stltop_mu ) || /* VS<VT */
					  ( vct_cndvseqvt_mu && vct_steqop_mu ) || /* VS==VT */
					  ( vct_cndvsnevt_mu && vct_stneop_mu ) || /* VS!=VT */
					  ( vct_cndvsgevt_mu && vct_stgeop_mu ) || /* VS>=VT */
					  ( vct_cndclsplo_mu && vct_stchop_mu ) || /* -VT<=VS<=VT SP 2s comp */
					  ( vct_cndcldplo_mu && vct_stclop_mu ) || /* -VT<=VS<=VT DP 2s comp */
					  ( vct_cndcrlo_mu && vct_stcrop_mu )      /* -VT<=VS<=VT 1s comp */
					) ||
					( su_datainlo_wb && su_wrcmpcd_wb ) ;


	assign	vct_cmpcdhi_mu =	( ( vct_cndclsphi_mu && vct_stchop_mu ) || /* -VT<=VS<=VT SP 2s comp */
					  ( vct_cndcldphi_mu && vct_stclop_mu ) || /* -VT<=VS<=VT DP 2s comp */
					  ( vct_cndcrhi_mu && vct_stcrop_mu )      /* -VT<=VS<=VT 1's comp */
					) ||
					( su_datainhi_wb && su_wrcmpcd_wb ) ;

	asdffen #(1, 0)	vctcmpcdloffac (vct_cmpcdlo_ac, vct_cmpcdlo_mu, vct_cmpcdld_mu, clk, reset_l );

	asdffen #(1, 0)	vctcmpcdhiffac (vct_cmpcdhi_ac, vct_cmpcdhi_mu, vct_cmpcdld_mu, clk, reset_l );


/*
*	Vector Compare Add flip-flops
*/
	wire	vct_cmpcdad_mu;		/* Data input to Vector Code Add register */

	assign	vct_cmpcdad_mu =	( vct_instvld_mu && vct_stchop_mu &&	/* Always reset unless VCL */
					  vdp_aluone_mu && vct_cndexrsgn_mu	/* result of ADD is minus one */
					) ||
					( su_datainlo_wb && su_wrcmpcdad_wb ) ;

	asdffen #(1, 0)	vctcmpcdadffac (vct_cmpcdad_ac, vct_cmpcdad_mu, vct_cmpcdadld_mu, clk, reset_l );



/*	??????
*	The following code defines the logic for all the output signals for this
*	block.
*/


/*
*	This portion controls the operation of the ALU in the MU stage.
*
*/

/*
*	The complementing of vt data for subtract and alu carry in signals  are timing 
*	critical since they dependent on signals that are not available until that clock.
*/

/*
*	assign	vct_aluctl_mu[0] =	  vct_pralucmpvt_mu || 
*  					( vct_absop_mu && vdp_vs_sign_mu ) ||
*					( vct_stclop_mu && !vct_cryout_ac ) || 
*					( vct_stchrop_mu && !vct_cndexrsgn_mu ) ;
*
*					  vct_aluctllsb_mu ||
*					( vct_stclop_mu && !vct_cryout_ac ) || 
*					( vct_stchrop_mu && !vct_cndexrsgn_mu ) ;
*/

	wire	vct_aluctlmxtmp_mu;	/* input to alu control mux */
	wire	vct_aluctlmx0_mu;	/* input to alu control mux */
	wire	vct_aluctlmx1_mu;	/* input to alu control mux */

	assign	vct_aluctlmxtmp_mu =	vct_pralucmpvt_mu || 
					( vct_stclop_mu && !vct_cryout_ac ) ; 

	assign	vct_aluctlmx1_mu =	vct_aluctlmxtmp_mu ;

	assign	vct_aluctlmx0_mu =	vct_aluctlmxtmp_mu || vct_stchrop_mu ;


/*
*	This was redundant logic that was discoverd late on in rev2.0 design.
*
*	assign	vct_aluctlmx1_mu =	vct_aluctlmxtmp_mu || 
*  					( vct_absop_mu && vdp_vs_sign_mu ) ; 
*
*	assign	vct_aluctlmx0_mu =	vct_aluctlmxtmp_mu || vct_stchrop_mu ||
*					( vct_absop_mu && vdp_vs_sign_mu ) ;
*
*	ao04d1  vctaluctlin1mu	(	.zn		(vct_aluctlmx1_mu),
*					.a1		(vct_vs_sign_mu),??????
*					.a2		(vct_absop_mu),
*					.b		(vct_aluctlmxtmp_mu)
*				);
*
*	ao05d1  vctaluctlin0mu	(	.zn		(vct_aluctlmx0_mu),
*					.a1		(vct_vs_sign_mu),??????
*					.a2		(vct_absop_mu),
*					.b		(vct_aluctlmxtmp_mu),
*					.c		(vct_stchrop_mu)
*				);
*/

	wire vct_alucmpvtcomp_mu;	

	j_mx21	vctaluctlmx0mu	(
					.z		(vct_alucmpvtcomp_mu), 
					.i0		(vct_aluctlmx0_mu), 
					.i1		(vct_aluctlmx1_mu), 
					.s		(vct_cndexrsgn_mu) 
				) ;

	j_ni01 vctalucmpvtinvmu	( 	.z		(vct_alucmpvt_mu),
					.i		(vct_alucmpvtcomp_mu)
				) ;

	wire	vct_aluprecin_mu;	/* carry in to alu decoded subtract instructions */

	asdffen #(1, 0)	vctalucinffmu (vct_aluprecin_mu, vct_aluprecin_rd, su_instvld_rd, clk, reset_l );

/*
*	assign	vct_alucin_mu =		( vct_addop_mu && vct_cryout_ac ) ||
*					( vct_substclop_mu && !vct_cryout_ac ) || 
*					( vct_stchop_mu && !vct_cndexrsgn_mu ) || 
*					( vct_absop_mu && vdp_vs_sign_mu ) ||
*					vct_aluprecin_mu ;
*/

	wire	vct_alucinmxtmp_mu;	/* input to alu carry in mux */
	wire	vct_alucinmx0_mu;	/* input to alu carry in mux */
	wire	vct_alucinmx1_mu;	/* input to alu carry in mux */

	assign	vct_alucinmxtmp_mu =	vct_aluprecin_mu || 
					( vct_addop_mu && vct_cryout_ac ) ||
					( vct_substclop_mu && !vct_cryout_ac ) ; 

	assign	vct_alucinmx1_mu =	vct_alucinmxtmp_mu ;

	assign	vct_alucinmx0_mu =	vct_alucinmxtmp_mu || vct_stchop_mu ;


/*
*	This was redundant logic that was discoverd late on in rev2.0 design.
*
*	assign	vct_alucinmx1_mu =	( vct_absop_mu && vdp_vs_sign_mu ) ||
*					vct_alucinmxtmp_mu ;
*
*	assign	vct_alucinmx0_mu =	( vct_absop_mu && vdp_vs_sign_mu ) ||
*					vct_alucinmxtmp_mu || vct_stchop_mu ;
*
*	ao04d1  vctalucinin1mu	(	.zn		(vct_alucinmx1_mu),
*					.a1		(vct_vs_sign_mu),??????
*					.a2		(vct_absop_mu),
*					.b		(vct_alucinmxtmp_mu)
*				);
*
*	ao05d1  vctalucinin0mu	(	.zn		(vct_alucinmx0_mu),
*					.a1		(vct_vs_sign_mu),??????
*					.a2		(vct_absop_mu),
*					.b		(vct_alucinmxtmp_mu),
*					.c		(vct_stchop_mu)
*				);
*
*/

	wire	vct_alucincomp_mu;

	j_mx21	vctalucinmxmu	(
					.z		(vct_alucincomp_mu), 
					.i0		(vct_alucinmx0_mu), 
					.i1		(vct_alucinmx1_mu), 
					.s		(vct_cndexrsgn_mu) 
				) ;

	j_ni01 vctalucininvmu	( 	.z		(vct_alucin_mu),
					.i		(vct_alucincomp_mu)
				) ;



	assign	vct_smlwrsl_mu[0] =
					vct_prsmlwrsl_mu[0] ||
					( vct_instvld_mu && !vct_prsmlwrsl_mu[1] && 
					  !( vct_absop_mu && !vdp_vs_zero_mu )
					) ;

	assign	vct_smlwrsl_mu[1] =
					( vct_instvld_mu &&
					  ( vct_prsmlwrsl_mu[1] || 
					    ( vct_absop_mu && !vdp_vs_zero_mu )
					  )
					) ||
					!vct_prsmlwrsl_mu[0] ;


/*
*	This portion controls the value used for rounding when loading the accumulator.
*	This appears extremely obtuse due to changes for timing improvements.
*	The old code is shown below which specifies functionally what is happening
*	to produce the round value.
*
*	assign	vct_rndvlu_ac =		( vct_macqop_ac && vct_oddfyneg_ac ) ? 4'h2 :
*					    ( vct_macqop_ac && vct_oddfypos_ac ) ? 4'hE :
*						( vct_rndpsl_ac && !vdp_accbit47_wb ) ? 4'h8 : 
*						    ( vct_rndnsl_ac && vdp_accbit47_wb ) ? 4'h8 : 
*							( vct_mulfop_ac || vct_muluop_ac ) ? 4'h8 :
*							    vct_mulqsgn_ac ? 4'h1 :
*								0 ;
*
*/

	wire	vct_rndpsl_mu;		/* selection of round value for rndp op in MU stage. */
	wire	vct_rndnsl_mu;		/* selection of round value for rndn op in MU stage. */

	assign	vct_rndpsl_mu =		vct_rndpop_mu && !vct_vseqone_mu && vdp_vt_sign_mu ;

	assign	vct_rndnsl_mu =		vct_rndnop_mu && !vct_vseqone_mu && vdp_vt_sign_mu ;

	wire	vct_mulqsgn_mu;		/* selection of round value for mulq op in MU stage. */

	assign	vct_mulqsgn_mu =	vct_mulqop_mu && vct_pdtsign_mu ;

	wire	[1:0]	vct_prerndvlu_mu;	/* predecoded round value for multiplies  */
	wire	[1:0]	vct_prerndvlu_ac;	/* predecoded round value for multiplies  */

	assign	vct_prerndvlu_mu[0] =	vct_mulqsgn_mu ;

	assign	vct_prerndvlu_mu[1] =	vct_rndpsl_mu || vct_rndnsl_mu || 
					vct_mulfop_mu || vct_muluop_mu ;

	asdffen #(2, 0)	vctprerndvluffac (vct_prerndvlu_ac, vct_prerndvlu_mu, vct_instvld_mu, clk, reset_l );


/*????
*	Removed to improve timing of round value.
*
*	assign	vct_oddfypos_ac	=	!vdp_accbit47_wb && !vdp_accbit21_wb &&
*					!(vdp_acchizero_wb && vdp_accmizero_wb) ;  
*/  /* 47-21 not zero */

/*????
*	assign	vct_oddfyneg_ac	=	vdp_accbit47_wb && !vdp_accbit21_wb &&
*					!(vdp_acchizero_wb && vdp_accmizero_wb) ;
*/  /* 47-21 not zero */


	wire	vct_oddfyposnc_ac;	/* non timing critical Oddify positive accumulator for macq op */
	wire	vct_oddfyneg_ac;	/* Oddify negative accumulator for macq op */

	assign	vct_oddfyposnc_ac =	vct_macqop_ac && !vdp_accbit47_wb && !vdp_accbit21_wb ;

	assign	vct_oddfyneg_ac	=	vct_macqop_ac && vdp_accbit47_wb && !vdp_accbit21_wb ;


	assign	vct_rndvlu_ac[0] =	vct_prerndvlu_ac[0] ;

	wire	vct_rndvlu1in_ac;	/* Mux Input to round value bit mux  */
	wire	vct_rndvlu1out_ac;	/* Mux Input to round value bit mux  */
	wire	vct_rndvlusl_ac;	/* Mux select to round value bit mux  */
	wire	vct_rndvlu2out_ac;	/* Mux Input to round value bit mux  */

	assign	vct_rndvlu1in_ac =	vct_oddfyposnc_ac || vct_oddfyneg_ac ;

/*	
*	Replace with high performance cells
*
*	assign	vct_rndvlusl_ac =	(vdp_acchizero_wb && vdp_accmizero_wb) ;
*/

	j_an02	vctrndvlu1anac	(
					.z		(vct_rndvlusl_ac), 
					.a1		(vdp_acchizero_wb), 
					.a2		(vdp_accmizero_wb) 
				) ;	 /* 47-21 not zero */

	j_mx21	vctrndvlu1mxac	(
					.z		(vct_rndvlu1out_ac), 
					.i0		(vct_rndvlu1in_ac), 
					.i1		(vct_oddfyneg_ac), 
					.s		(vct_rndvlusl_ac) 
				) ;

	assign	vct_rndvlu_ac[1] =	vct_rndvlu1out_ac ;


	j_ao01	vctrndvlu2aoac	(
					.zn		(vct_rndvlu2out_ac), 
					.a1		(!vdp_accmizero_wb), 
					.a2		(vct_oddfyposnc_ac), 
					.b1		(!vdp_acchizero_wb), 
					.b2		(vct_oddfyposnc_ac) 
				) ;	 /* 47-21 not zero */

	assign	vct_rndvlu_ac[2] =	!vct_rndvlu2out_ac ;

/*
*	assign	vct_rndvlu_ac[3] =	vct_prerndvlu_ac[1] || ( vct_oddfyposnc_ac && !vct_rndvlusl_ac ) ;
*/

	wire	vct_rndvlu3in_ac;	/* Mux Input to round value bit mux  */

	assign	vct_rndvlu3in_ac =	vct_prerndvlu_ac[1] || vct_oddfyposnc_ac ;

	j_mx21	vctrndvlu3mxac	(
					.z		(vct_rndvlu_ac[3]), 
					.i0		(vct_rndvlu3in_ac), 
					.i1		(vct_prerndvlu_ac[1]), 
					.s		(vct_rndvlusl_ac) 
				) ;

/*
*	Replaced by mux structure for timing reasons.  Select is controlled 
*	by vdp_acchizero_wb
*
*	assign	vct_rndvlu_ac[1] =	vct_oddfypos_ac || vct_oddfyneg_ac ;
*
*	assign	vct_rndvlu_ac[2] =	vct_oddfypos_ac ;
*	assign	vct_rndvlu_ac[2] =	vct_oddfyposnc_ac && !vct_rndvlusl_ac ;
*
*	assign	vct_rndvlu_ac[3] =	vct_prerndvlu_ac[1] || vct_oddfypos_ac ;
*
*/

/*
*	This portion controls the muxing into the lower 3 input adder in 
*	the AC stage.
*/

	wire	vct_cslwb0mx_ac;	/* mux select to low CSA inb assumes vdp_accbit47_wb=0 */
	wire	vct_cslwb1mx_ac;	/* mux select to low CSA inb assumes vdp_accbit47_wb=1 */

	assign	vct_cslwb0mx_ac =	vct_prcslwbsl_ac[0] ;

	assign	vct_cslwb1mx_ac =	vct_prcslwbsl_ac[1] ;

	j_mx21	vctcslwb0slmxac	(
					.z		(vct_cslwbsl_ac[0]), 
					.i0		(vct_cslwb0mx_ac), 
					.i1		(vct_cslwb1mx_ac), 
					.s		(vdp_accbit47_wb) 
				) ;
/*
*	The code below was replaced by a mux structure for timing reasons
*
*	assign	vct_cslwbsl_ac[0] =	( vct_rndpop_ac && !vdp_accbit47_wb && !vct_vseqone_ac ) ||
*					( vct_rndnop_ac && vdp_accbit47_wb && !vct_vseqone_ac ) ||
*					vct_prcslwbsl_ac[0] ;
*/

	assign	vct_cslwbsl_ac[1] =	vct_prcslwbsl_ac[2] ;


	wire	vct_cndexrsgn_ac;	/* Exor of VS and VT sign bits for use in CL and CR */

	assign	vct_cndexrsgn_ac =	vct_vs_sign_ac ^ vct_vt_sign_ac ;


	assign	vct_addlwci_ac =	( vct_absop_ac && vct_vs_sign_ac ) ||
					( ( vct_stchop_ac || vct_stclop_ac ) && 
					  vct_pdtsign_ac && vct_cmpcdlo_ac 
					) ||
					( ( vct_mudlop_ac || vct_madlop_ac ) && vmu_co_clal_ac );

/*
*	This portion controls the muxing into the upper 3 input adder in 
*	the AC stage.
*/


	assign	vct_csupbsl_ac[0] =	( vct_rndpop_ac && !vdp_accbit47_wb && vct_vseqone_ac ) ||
					( vct_rndnop_ac && vdp_accbit47_wb && vct_vseqone_ac ) ||
					vct_prcsupbsl_ac[0] ;

  	assign	vct_csupbsl_ac[1] =	( vct_rndpop_ac && !vdp_accbit47_wb && !vct_vseqone_ac ) ||
					( vct_rndnop_ac && vdp_accbit47_wb && !vct_vseqone_ac ) ||
					vct_prcsupbsl_ac[1] ;

	assign	vct_csupcen_ac =	vct_prcsupcen_ac ;
	


/*
*	This portion controls the incrementer/decrementer in the AC stage.
*/

	assign	vct_incrdwn_ac =	( vct_multtypop_ac || vct_rndpop_ac || 
					  vct_rndnop_ac ) && vct_pdtsign_ac ;

	assign	vct_incrci_ac =		vct_multincop_ac ||
					( vct_rndpop_ac && !vdp_accbit47_wb ) ||
					( vct_rndnop_ac && vdp_accbit47_wb ) ;


/*
*	Removed for area saving to allow vdpincremxac mux to be reduced from 
*	a 4to1 mux to a 2to1 mux.
*
*	assign	vct_incrmxsl_ac[0] =	!vct_multactyp_ac &&	*  not positive mulu/f result *
*					!( (vct_mulfop_ac || vct_muluop_ac || vct_mudlop_ac) &&
*					   !vct_pdtsign_ac 
*					 ) ;  
*/				

	assign	vct_incrmxsl_ac =	vct_multactyp_ac ;


	assign	vct_aclwsl_ac[0] =
					( vct_instvld_ac &&
					  ( vct_praclwsl_ac[0] || vct_praclwsl_ac[1] || 
					    ( vct_stnclrdop_ac && !vct_cmpcdlo_ac ) ||
					    ( vct_stclrdop_ac && !vct_pdtsign_ac && vct_cmpcdhi_ac ) ||
					    ( vct_stclrdop_ac && vct_pdtsign_ac && vct_cmpcdlo_ac )
					  )
					) ;

/*
*	Note that vct_pdtsign_ac holds the value of carryout flag for VCL instructions since
*	this instruction resets carryout in the MU stage but we need to keep it around to
*	determine the sign of the operation.
*/

	assign	vct_aclwsl_ac[1] =
					( vct_instvld_ac &&
					  ( vct_praclwsl_ac[1] ||
					    ( vct_stnclrdop_ac && vct_cmpcdlo_ac ) ||
					    ( vct_stclrdop_ac && !vct_pdtsign_ac && !vct_cmpcdhi_ac ) ||
					    ( vct_stclrdop_ac && vct_pdtsign_ac && !vct_cmpcdlo_ac )
					  )
					) ;

	
/*
*	We only select a new value for the upper half of the accumulator if
*	there is a true carry out from the csa/adder and the resulting 
*	product being added to the accumulator is positive or there is no
*	carry out and the resulting product being added to the accumulator 
*	is negative.
*/
	wire 	vct_truecoutnc_ac;	/* Non timing critical True carry out from lower 32 bits */

	assign	vct_truecoutnc_ac =	vct_pdtsign_ac ^ vdp_csupco_ac ^ 
					(!vct_rndop_ac && vmu_co_clah_ac) ;
/*
*	vmu_co_clah_ac needs qualified with round instruction since we need to ignore 
*	value from mult since no proper multiply is occurring but round is treated 
*	like a multiply op.  This change was only required for 2nd tapeout since in
*	first tapeout VS was zeroed in the rd stage therefore multiplier always 
*	multiplied vt by zero during a round instruction.  This zeroing could not
*	occur on 2nd tapeout due to new register file implementaiton therefore the
*	above equation was required.
*/

	wire 	vct_acup1innc_ac;	/* Non-timing critical data inputs to acup0slmx */
	wire 	vct_acup1ina_ac;	/* Non-timing critical data input a to acup1slmx */
	wire 	vct_acup1inb_ac;	/* Non-timing critical data input b to acup1slmx */
	wire 	vct_acup1outnc_ac;	/* Non-timing critical data output of acup1slmx */


	assign	vct_acup1innc_ac =
					( vct_instvld_ac && vct_pracupsl_ac[0] ) ;

	assign	vct_acup1ina_ac =	vct_acup1innc_ac ||
					( vct_instvld_ac && 
					  vct_multactyp_ac && vct_truecoutnc_ac
					) ;

	assign	vct_acup1inb_ac =	vct_acup1innc_ac ||
					( vct_instvld_ac && 
					  vct_multactyp_ac && !vct_truecoutnc_ac
					) ;

	j_mx21	vctacup1slmxac	(
					.z	(vct_acup1out_ac), 
					.i0	(vct_acup1ina_ac), 
					.i1	(vct_acup1inb_ac), 
					.s	(vdp_addupco_ac)
				) ;

	assign	vct_acupsl_ac[0] =	vct_acup1out_ac ;


	assign	vct_acupsl_ac[1] =
					( vct_instvld_ac && vct_pracupsl_ac[1] ) ||
					( vct_instvld_ac &&
					   (vct_mulfop_ac || vct_muluop_ac || vct_mudlop_ac) &&
					   !vct_pdtsign_ac 
					) ;  


/*
*	This portion controls the various clamp values and when clamping is 
*	required.
*/

	wire	vct_clpsgnmu_wb;	/* clamped signed multiply */
	wire	vct_clpunsmu_wb;	/* clamped unsigned multiply */
	wire	vct_clpmnsgas_wb;	/* 16 bit signed add/subtract underflowed */
	wire	vct_clpmxsgas_wb;	/* 16 bit signed add/subtract overflowed */

	wire	vct_clpsgnmx0_wb;	/* input to clamped signed control mux data 0 */
	wire	vct_clpsgnmx1_wb;	/* input to clamped signed control mux data 1 */

	assign	vct_clpsgnmx0_wb =	( vct_clpsgn31_wb && !vdp_accbit31_wb ) /* clamp signed 31 to MSB */ 
					||
					( ( vct_clpsgn31_wb || vct_clpsgn32_wb ) && /* clamp on 32 to MSB */ 
					  !vdp_acchione_wb			/* Not all ones */
					) ;

	assign	vct_clpsgnmx1_wb =	( vct_clpsgn31_wb &&		/* clamp signed on 31 to MSB */ 
					  vdp_accbit31_wb 		/* Not all zeroes including mux sel */
					) ;
/*
*  Not all ones test not necessary since vdp_acchizero_wb we know is one
*  && !( vdp_accbit31_wb && !vdp_acchione_wb ) ) ;
*/					

	j_mx21	vctclpsgnmuwb	(
					.z		(vct_clpsgnmu_wb), 
					.i0		(vct_clpsgnmx0_wb), 
					.i1		(vct_clpsgnmx1_wb), 
					.s		(vdp_acchizero_wb) 
				) ;

/*	Modified toimprove timing of acchizero signal.
*
*	assign	vct_clpsgnmu_wb =	( vct_clpsgn31_wb &&
*					  !( !vdp_accbit31_wb && vdp_acchizero_wb ) &&
*					  !( vdp_accbit31_wb && vdp_acchione_wb )
*					) 
*					||
*					( vct_clpsgn32_wb && 			//
*					  !vdp_acchizero_wb && !vdp_acchione_wb	//
*					) ;
*/

/*	Replaced to improve timing of acchihero signal.
*
*	assign	vct_clpunsmu_wb =	( vct_clpsgn16_wb &&		   
*					  !( !vdp_accbit31_wb && vdp_acchizero_wb ) &&
*					  !( vdp_accbit31_wb && vdp_acchione_wb )	
*					) ||
*					( vct_clpuns31_wb &&
*					  !( !vdp_accbit31_wb && vdp_acchizero_wb )
*					) ; 
*/

	assign	vct_clpunsmu_wb =	!( !vdp_accbit31_wb && vdp_acchizero_wb ) &&  /* Not all zeroes */
					(
					  ( vct_clpsgn16_wb &&		   /* clamp unsigned on 31 to MSB */ 
					    !( vdp_accbit31_wb && vdp_acchione_wb ) 	/* Not all ones */
					  )
					  || vct_clpuns31_wb 
					) ; 


/*
*	???? simplified unsigned clamping to help timing of vdp_accbit47_wb.
*					( vct_clpuns31_wb && vdp_accbit47_wb ) || 
*					( vct_clpuns31_wb && !vdp_accbit47_wb &&
*					  (vdp_accbit31_wb || !vdp_acchizero_wb)
*					) ; 
*/


	assign	vct_clpmnsgas_wb =	vct_adscl16op_wb && vct_aluovfl_wb && !vdp_accbit15_wb ;

	assign	vct_clpmxsgas_wb =	vct_adscl16op_wb && vct_aluovfl_wb && vdp_accbit15_wb ;


	wire	vct_clprsltsl_wb;	/* clamping required for result */

	assign	vct_clprsltsl_wb =	vct_clpsgnmu_wb || vct_clpunsmu_wb || vct_clpmnsgas_wb || 
					vct_clpmxsgas_wb ;


	wire	vct_clpminsgn_wb;	/* clamped result to 16 bit signed minimum */
	wire	vct_clpmaxsgn_wb;	/* clamped result to 16 bit signed maximum */
	wire	vct_clpmxun16_wb;	/* clamped result to 16 bit unsigned maximum */
	wire	vct_clpmxsgn32_wb;	/* clamped result to 16 bit signed maximum for mulq/macq */
	wire	vct_clpmnsgn32_wb;	/* clamped result to 16 bit signed minimum for mulq/macq */

/*
* 16 bit signed underflow
*
*/

	assign	vct_clpminsgn_wb =	( vct_clpsgn31_wb && vdp_accbit47_wb &&  /* ACC -ve */
					  (!vdp_accbit31_wb || !vdp_acchione_wb)  /* Not all ones */
					) ;

/*
* 16 bit signed overflow
*/
	assign	vct_clpmaxsgn_wb =	( vct_clpsgn31_wb && !vdp_accbit47_wb && /* ACC +ve */
					  (vdp_accbit31_wb || !vdp_acchizero_wb) /* Not all zeroes */
					) ;

/*
* 16 bit unsigned overflow
*/
	assign	vct_clpmxun16_wb =	( ( vct_clpuns31_wb || vct_clpsgn16_wb ) && 
					  !vdp_accbit47_wb &&  /* ACC +ve */
					  !(!vdp_accbit31_wb && vdp_acchizero_wb) /* Not all zeroes */
					) ;

	assign	vct_clpmxsgn32_wb =	( vct_clpsgn32_wb && !vdp_accbit47_wb && /* clamp on 32 to MSB */ 
					  !vdp_acchizero_wb			 /* Not all zeroes */
					) ;

	assign	vct_clpmnsgn32_wb =	( vct_clpsgn32_wb && vdp_accbit47_wb &&	/* clamp on 32 to MSB */ 
					  !vdp_acchione_wb			/* Not all ones */
					) ;

/*
*	Replaced following for timing reasons since synopsys really did not do a 
*	good job with it.
*
*	assign	vct_clprslt_wb =	(vct_clpminsgn_wb || vct_clpmnsgn32_wb) ? 3'h4 :
*					    vct_clpmaxsgn_wb ? 3'h3 :
*						vct_clpmxun16_wb ? 3'h7 :
*						    vct_clpmxsgn32_wb ? 3'h2 : 3'h0 ;
*/

	assign	vct_clprslt_wb[0] =	vct_clpmxsgas_wb || vct_clpmaxsgn_wb || vct_clpmxun16_wb ;

	assign	vct_clprslt_wb[1] =	vct_clpmxsgas_wb || vct_clpmaxsgn_wb || 
					vct_clpmxun16_wb || vct_clpmxsgn32_wb ;
					
	assign	vct_clprslt_wb[2] =	vct_clpmnsgas_wb || vct_clpminsgn_wb || 
					vct_clpmnsgn32_wb || vct_clpmxun16_wb ;


/*
*	This portion controls the muxing into the result bus to be written back
*	into the VU register file in the Wb stage.
*????? other terms for low portion of accumulator need to go in here.
*/

	assign	vct_rsltsl_wb[0] =	( vct_acchighsl_wb && !vct_clprsltsl_wb && !vct_divrsltsl_wb ) ||
					( vct_acclowsl_wb && !vct_clprsltsl_wb && !vct_divrsltsl_wb ) ||
					( vct_clprsltsl_wb && !vct_divrsltsl_wb ) ;

	assign	vct_rsltsl_wb[1] =	( vct_accmidsl_wb && !vct_clprsltsl_wb && !vct_divrsltsl_wb ) || 
					( vct_acclowsl_wb && !vct_clprsltsl_wb && !vct_divrsltsl_wb ) ||
					vct_divrsltsl_wb ;

	assign	vct_rsltsl_wb[2] =	( vct_accshftsl_wb && !vct_clprsltsl_wb && !vct_divrsltsl_wb ) ||
					( vct_clprsltsl_wb && !vct_divrsltsl_wb ) ||
					vct_divrsltsl_wb ;


endmodule