/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vurf.v,v 1.4 2003/01/24 23:07:37 berndt Exp $

/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vurf						*
*	Description:	Vector unit custom register file block where	*
*			the register file is implemented as a 32 word	*
*			by 128 monolithic structure.			*
*									*
*			which contain address decoding, address 	*
*			transpose logic for load/store addresses,	*
*			scalar muxing on VT read port and read data	*
*			registers for all three read ports.		*
*									*
*			This partitioning was decided upon for 		*
*			physical partitioning.				*
*									*
*			This version is for the standard cell		*
*			implementation of the datapath.			*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		3/30/95						*
*									*
*************************************************************************
*/

// vurf.v: 	RSP vector unit register file 

`timescale 1ns / 10ps

module	vurf (	
		preclk_in0,
		preclk_in1,
		reset_l, 
		su_instvld_rd,

		su_vs_addr_rd,
		su_vt_addr_rd,
		su_vd_addr_wb,
		su_st_rnum_rd,
		su_xp_rnum_rd,
		su_ld_rnum_wb,

		su_sclrdatasl_rd,
		su_qrtdatasl_rd,
		su_hlfdatasl_rd,
		su_whldatasl_rd,

		vct_wbv_wr_en_wb,
		su_bwe_wb,
		su_xposeop_rd,
		su_xposeop_wb,

		vdp_datatristen_rd,
		vdp_rslt_data_wb,


		vrf_div_input_rd,
		vrf_vs_data_mu,
		vrf_vt_data_mu,
		vu_ls_data,
		su_data_to_from

	   ) ;


	input	preclk_in0;			/* pre-buffered clock for new clocking scheme */
	input	preclk_in1;			/* pre-buffered clock for new clocking scheme */
	input	reset_l;			/* vu active low reset */
	input	su_instvld_rd;			/* valid CP2 instruction for vu */

	input	[4:0]	su_vs_addr_rd;		/* register number for vs read */
	input	[4:0]	su_vt_addr_rd;		/* decoded register number for vt read */
	input	[4:0]	su_vd_addr_wb;		/* register number for datapath writeback */
	input	[4:0]	su_st_rnum_rd;		/* register number for stores */
	input	[4:0]	su_xp_rnum_rd;		/* register number for xpose stores */
	input	[4:0]	su_ld_rnum_wb;		/* register number for load */

	input   [3:0]	su_sclrdatasl_rd;	/* selcts for vector, quarter, half or whole scalar data */
	input   [1:0]	su_qrtdatasl_rd;	/* selects for scalar quarter data */
	input   [3:0]	su_hlfdatasl_rd;	/* selects for scalar half data */
	input   [7:0]	su_whldatasl_rd;	/* selects for scalar whole data */

	input	[7:0]	vct_wbv_wr_en_wb;	/* short word write enable for datapath results */
	input	[15:0]	su_bwe_wb;		/* load port byte write enable */
	input	su_xposeop_rd;			/* transpose op for rd stage (store) */
	input	su_xposeop_wb;			/* transpose op for ac stage (load) */

	input	vdp_datatristen_rd;		/* tristate enable for load/store data bus */

	input	[127:0]	vdp_rslt_data_wb;	/* VU computational result from data path */


/*
*	The following output signals are data from the register file.
*/

	output	[15:0]	vrf_div_input_rd;	/* data for divide unit */
	output	[127:0]	vrf_vs_data_mu;		/* read data for vs port */
	output	[127:0]	vrf_vt_data_mu;		/* read data for vt port after scalar muxes */

	output	[127:0]	vu_ls_data;		/* data field to   su */
	input	[127:0]	su_data_to_from;	/* data field from su */

/*
*	reg and wire variables for use within this module.
*/

	reg	[127:0]	vrf_vs_datarg_mu;	/* read data for vs port */
	reg	[127:0]	vrf_vt_datarg_mu;	/* read data for vt port after scalar muxes */
	reg	[127:0]	vrf_data_from_mu;	/* read data for store data port */

	reg	[127:0]	vrf_vt_data_rd;		/* read data for vt port after scalar muxes */
	reg	[15:0]	vrf_qrtdata01_rd;	/* quarter data for slices 0 and 1 */
	reg	[15:0]	vrf_qrtdata23_rd;	/* quarter data for slices 2 and 3 */
	reg	[15:0]	vrf_qrtdata45_rd;	/* quarter data for slices 4 and 5 */
	reg	[15:0]	vrf_qrtdata67_rd;	/* quarter data for slices 6 and 7 */
	reg	[15:0]	vrf_hlfdata03_rd;	/* half data for slices 0,1,2 and 3 */
	reg	[15:0]	vrf_hlfdata47_rd;	/* half data for slices 4,5,6 and 7 */
	reg	[15:0]	vrf_whldata_rd;		/* whole data for all slices */

	reg	write_conflict;			/* flag warning of two writes to same location */

	wire	[127:0]	vrf_vs_rfout_rd;	/* vs read data port of register file */
	wire	clk;				/* vu clock */

	assign	clk =	preclk_in0;

	wire	[127:0]	vrf_data_rd;
	wire	[7:0]	datsl0hi =	vrf_data_rd[127:120];
	wire	[7:0]	datsl0lo =	vrf_data_rd[119:112];
	wire	[7:0]	datsl1hi =	vrf_data_rd[111:104];
	wire	[7:0]	datsl1lo =	vrf_data_rd[103:96];
	wire	[7:0]	datsl2hi =	vrf_data_rd[95:88];
	wire	[7:0]	datsl2lo =	vrf_data_rd[87:80];
	wire	[7:0]	datsl3hi =	vrf_data_rd[79:72];
	wire	[7:0]	datsl3lo =	vrf_data_rd[71:64];
	wire	[7:0]	datsl4hi =	vrf_data_rd[63:56];
	wire	[7:0]	datsl4lo =	vrf_data_rd[55:48];
	wire	[7:0]	datsl5hi =	vrf_data_rd[47:40];
	wire	[7:0]	datsl5lo =	vrf_data_rd[39:32];
	wire	[7:0]	datsl6hi =	vrf_data_rd[31:24];
	wire	[7:0]	datsl6lo =	vrf_data_rd[23:16];
	wire	[7:0]	datsl7hi =	vrf_data_rd[15:8];
	wire	[7:0]	datsl7lo =	vrf_data_rd[7:0];

/*
*	load write port functionality
*/

	wire	[4:0]	vrf_load_addrsl0_wb;	/* register number for write load data slice 0 */
	wire	[4:0]	vrf_load_addrsl1_wb;	/* register number for write load data slice 1 */
	wire	[4:0]	vrf_load_addrsl2_wb;	/* register number for write load data slice 2 */
	wire	[4:0]	vrf_load_addrsl3_wb;	/* register number for write load data slice 3 */
	wire	[4:0]	vrf_load_addrsl4_wb;	/* register number for write load data slice 4 */
	wire	[4:0]	vrf_load_addrsl5_wb;	/* register number for write load data slice 5 */
	wire	[4:0]	vrf_load_addrsl6_wb;	/* register number for write load data slice 6 */
	wire	[4:0]	vrf_load_addrsl7_wb;	/* register number for write load data slice 7 */


	assign	vrf_load_addrsl0_wb =	su_ld_rnum_wb ;

	assign	vrf_load_addrsl1_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h1)&3'h7
						  } ;

	assign	vrf_load_addrsl2_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h2)&3'h7
						  } ;

	assign	vrf_load_addrsl3_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h3)&3'h7
						  } ;

	assign	vrf_load_addrsl4_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h4)&3'h7
						  } ;

	assign	vrf_load_addrsl5_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h5)&3'h7
						  } ;

	assign	vrf_load_addrsl6_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h6)&3'h7
						  } ;

	assign	vrf_load_addrsl7_wb =	!su_xposeop_wb ? su_ld_rnum_wb 
						: { su_ld_rnum_wb[4:3],
						    (su_ld_rnum_wb[2:0] + 3'h7)&3'h7
						  } ;

/*
*	Collision detection if two write ports try to write the same address.
*	Write x data and set error flag if writes collide.
*/

// synopsys translate_off

	always @(negedge clk)
		begin

		    write_conflict = 0;

			if ( (vct_wbv_wr_en_wb[7] == 1'b1) && 
			     ( (su_bwe_wb[15] == 1'b1) || (su_bwe_wb[14] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl0_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 0 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[6] == 1'b1) && 
			     ( (su_bwe_wb[13] == 1'b1) || (su_bwe_wb[12] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl1_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 1 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[5] == 1'b1) && 
			     ( (su_bwe_wb[11] == 1'b1) || (su_bwe_wb[10] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl2_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 2 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[4] == 1'b1) && 
			     ( (su_bwe_wb[9] == 1'b1) || (su_bwe_wb[8] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl3_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 3 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[3] == 1'b1) && 
			     ( (su_bwe_wb[7] == 1'b1) || (su_bwe_wb[6] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl4_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 4 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[2] == 1'b1) && 
			     ( (su_bwe_wb[5] == 1'b1) || (su_bwe_wb[4] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl5_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 5 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[1] == 1'b1) && 
			     ( (su_bwe_wb[3] == 1'b1) || (su_bwe_wb[2] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl6_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 6 for 3R/2W regfile"); 
			    end

			if ( (vct_wbv_wr_en_wb[0] == 1'b1) && 
			     ( (su_bwe_wb[1] == 1'b1) || (su_bwe_wb[0] == 1'b1) ) &&
			     ( su_vd_addr_wb == vrf_load_addrsl7_wb )
			   )
			    begin
				write_conflict = 1;
				$display($time,"  ERROR:Write Conflict slice 7 for 3R/2W regfile"); 
			    end

		end

// synopsys translate_on

/*
*	vt read port data access including scalar mux functionality
*/


	always @(
		 su_qrtdatasl_rd or su_hlfdatasl_rd or 
		 su_whldatasl_rd or su_sclrdatasl_rd or
		 datsl0hi or datsl0lo or datsl1hi or datsl1lo or
		 datsl2hi or datsl2lo or datsl3hi or datsl3lo or
		 datsl4hi or datsl4lo or datsl5hi or datsl5lo or
		 datsl6hi or datsl6lo or datsl7hi or datsl7lo 
		)
		begin

		    case ( su_qrtdatasl_rd )

			2'h1: begin
				vrf_qrtdata01_rd = {datsl0hi,datsl0lo} ;
				vrf_qrtdata23_rd = {datsl2hi,datsl2lo} ;
				vrf_qrtdata45_rd = {datsl4hi,datsl4lo} ;
				vrf_qrtdata67_rd = {datsl6hi,datsl6lo} ;
			      end

			2'h2: begin
				vrf_qrtdata01_rd = {datsl1hi,datsl1lo} ;
				vrf_qrtdata23_rd = {datsl3hi,datsl3lo} ;
				vrf_qrtdata45_rd = {datsl5hi,datsl5lo} ;
				vrf_qrtdata67_rd = {datsl7hi,datsl7lo} ;
			      end

			default :
			      begin
				vrf_qrtdata01_rd = 16'hxxxx ;
				vrf_qrtdata23_rd = 16'hxxxx ;
				vrf_qrtdata45_rd = 16'hxxxx ;
				vrf_qrtdata67_rd = 16'hxxxx ;
			      end

		    endcase  // su_qrtdatasl_rd


		    case ( su_hlfdatasl_rd )

			4'h1: begin
				vrf_hlfdata03_rd = {datsl0hi,datsl0lo} ;
				vrf_hlfdata47_rd = {datsl4hi,datsl4lo} ;
			      end

			4'h2: begin
				vrf_hlfdata03_rd = {datsl1hi,datsl1lo} ;
				vrf_hlfdata47_rd = {datsl5hi,datsl5lo} ;
			      end

			4'h4: begin
				vrf_hlfdata03_rd = {datsl2hi,datsl2lo} ;
				vrf_hlfdata47_rd = {datsl6hi,datsl6lo} ;
			      end

			4'h8: begin
				vrf_hlfdata03_rd = {datsl3hi,datsl3lo} ;
				vrf_hlfdata47_rd = {datsl7hi,datsl7lo} ;
			      end

			default :
			      begin
				vrf_hlfdata03_rd = 16'hxxxx ;
				vrf_hlfdata47_rd = 16'hxxxx ;
			      end

		    endcase  // su_hlfdatasl_rd


		    case ( su_whldatasl_rd )

			8'h01: begin
				vrf_whldata_rd = {datsl0hi,datsl0lo} ;
			       end

			8'h02: begin
				vrf_whldata_rd = {datsl1hi,datsl1lo} ;
			       end

			8'h04: begin
				vrf_whldata_rd = {datsl2hi,datsl2lo} ;
			       end

			8'h08: begin
				vrf_whldata_rd = {datsl3hi,datsl3lo} ;
			       end

			8'h10: begin
				vrf_whldata_rd = {datsl4hi,datsl4lo} ;
			       end

			8'h20: begin
				vrf_whldata_rd = {datsl5hi,datsl5lo} ;
			       end

			8'h40: begin
				vrf_whldata_rd = {datsl6hi,datsl6lo} ;
			       end

			8'h80: begin
				vrf_whldata_rd = {datsl7hi,datsl7lo} ;
			       end

			default :
			      begin
				vrf_whldata_rd = 16'hxxxx ;
			      end

		    endcase  // su_whldatasl_rd


		    case ( su_sclrdatasl_rd )

			4'h1: begin
					vrf_vt_data_rd = {
						datsl0hi, datsl0lo,
						datsl1hi, datsl1lo,
						datsl2hi, datsl2lo,
						datsl3hi, datsl3lo,
						datsl4hi, datsl4lo,
						datsl5hi, datsl5lo,
						datsl6hi, datsl6lo,
						datsl7hi, datsl7lo
					       } ;
					end

			4'h2: begin
					vrf_vt_data_rd = {
						vrf_qrtdata01_rd, vrf_qrtdata01_rd,
						vrf_qrtdata23_rd, vrf_qrtdata23_rd,
						vrf_qrtdata45_rd, vrf_qrtdata45_rd,
						vrf_qrtdata67_rd, vrf_qrtdata67_rd
					       } ;
					end

			4'h4: begin
					vrf_vt_data_rd = {
						vrf_hlfdata03_rd, vrf_hlfdata03_rd,
						vrf_hlfdata03_rd, vrf_hlfdata03_rd,
						vrf_hlfdata47_rd, vrf_hlfdata47_rd,
						vrf_hlfdata47_rd, vrf_hlfdata47_rd
					       } ;
					end

			4'h8: begin
					vrf_vt_data_rd = {
						vrf_whldata_rd, vrf_whldata_rd,
						vrf_whldata_rd, vrf_whldata_rd,
						vrf_whldata_rd, vrf_whldata_rd,
						vrf_whldata_rd, vrf_whldata_rd
					       } ;
					end

			default : begin
					vrf_vt_data_rd = 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ;
					end
		    endcase  // su_sclrdatasl_rd

		end

	assign vrf_div_input_rd =  vrf_whldata_rd[15:0];

	always @(posedge clk)
	begin
		if(reset_l == 1'b0)
			vrf_vt_datarg_mu <= {128{1'b0}};
		else if(su_instvld_rd)
			vrf_vt_datarg_mu <= vrf_vt_data_rd;
 	end

	assign	vrf_vt_data_mu =	vrf_vt_datarg_mu ;

	always @(posedge clk)
	begin
		if(reset_l == 1'b0)
			vrf_vs_datarg_mu <= {128{1'b0}};
		else if(su_instvld_rd)
			vrf_vs_datarg_mu <= vrf_vs_rfout_rd;
	end


	assign vrf_vs_data_mu =	vrf_vs_datarg_mu ;


/*
*	Store read port read data access
*/

	wire	[4:0]	vrf_store_addrsl0_rd;	/* register number for store read data slice 0 */
	wire	[4:0]	vrf_store_addrsl1_rd;	/* register number for store read data slice 1 */
	wire	[4:0]	vrf_store_addrsl2_rd;	/* register number for store read data slice 2 */
	wire	[4:0]	vrf_store_addrsl3_rd;	/* register number for store read data slice 3 */
	wire	[4:0]	vrf_store_addrsl4_rd;	/* register number for store read data slice 4 */
	wire	[4:0]	vrf_store_addrsl5_rd;	/* register number for store read data slice 5 */
	wire	[4:0]	vrf_store_addrsl6_rd;	/* register number for store read data slice 6 */
	wire	[4:0]	vrf_store_addrsl7_rd;	/* register number for store read data slice 7 */

	assign	vrf_store_addrsl0_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: su_xp_rnum_rd ;

	assign	vrf_store_addrsl1_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h1)&3'h7
						  } ;

	assign	vrf_store_addrsl2_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h2)&3'h7
						  } ;

	assign	vrf_store_addrsl3_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h3)&3'h7
						  } ;

	assign	vrf_store_addrsl4_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h4)&3'h7
						  } ;

	assign	vrf_store_addrsl5_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h5)&3'h7
						  } ;

	assign	vrf_store_addrsl6_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h6)&3'h7
						  } ;

	assign	vrf_store_addrsl7_rd =	!su_xposeop_rd ? su_st_rnum_rd 
						: { su_xp_rnum_rd[4:3],
						    (su_xp_rnum_rd[2:0] + 3'h7)&3'h7
						  } ;

	wire	[127:0]	nxt_vrf_data_from_mu;


	always @(posedge clk)
		vrf_data_from_mu <= nxt_vrf_data_from_mu;

/*
*	Tristate control for su_data_to_from bus. (removed)
*/

	wire	vrf_datatristen_mu;	/* tristate enable for load/store data bus */

	asdff #(1, 0)	vrfdatatristenffmu (vrf_datatristen_mu, vdp_datatristen_rd, clk, reset_l );

	assign	vu_ls_data[127:0] = vrf_datatristen_mu ? vrf_data_from_mu[127:0] : 128'b0;

/*
*	Instantiate the 16 32x8-bit 3Read/2Write Port RAMs
*/

	wire	clk_b = ~clk;

vu_buf	memsl0lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[15]),
		.waa		(vrf_load_addrsl0_wb),
		.dina		(su_data_to_from[127:120]),
		.web		(vct_wbv_wr_en_wb[7]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[127:120]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[127:120]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[127:120]),
		.rae		(vrf_store_addrsl0_rd),
		.rde		(nxt_vrf_data_from_mu[127:120])
		);

vu_buf	memsl0hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[14]),
		.waa		(vrf_load_addrsl0_wb),
		.dina		(su_data_to_from[119:112]),
		.web		(vct_wbv_wr_en_wb[7]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[119:112]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[119:112]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[119:112]),
		.rae		(vrf_store_addrsl0_rd),
		.rde		(nxt_vrf_data_from_mu[119:112])
		);

vu_buf	memsl1lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[13]),
		.waa		(vrf_load_addrsl1_wb),
		.dina		(su_data_to_from[111:104]),
		.web		(vct_wbv_wr_en_wb[6]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[111:104]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[111:104]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[111:104]),
		.rae		(vrf_store_addrsl1_rd),
		.rde		(nxt_vrf_data_from_mu[111:104])
		);

vu_buf	memsl1hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[12]),
		.waa		(vrf_load_addrsl1_wb),
		.dina		(su_data_to_from[103:96]),
		.web		(vct_wbv_wr_en_wb[6]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[103:96]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[103:96]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[103:96]),
		.rae		(vrf_store_addrsl1_rd),
		.rde		(nxt_vrf_data_from_mu[103:96])
		);

vu_buf	memsl2lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[11]),
		.waa		(vrf_load_addrsl2_wb),
		.dina		(su_data_to_from[95:88]),
		.web		(vct_wbv_wr_en_wb[5]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[95:88]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[95:88]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[95:88]),
		.rae		(vrf_store_addrsl2_rd),
		.rde		(nxt_vrf_data_from_mu[95:88])
		);

vu_buf	memsl2hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[10]),
		.waa		(vrf_load_addrsl2_wb),
		.dina		(su_data_to_from[87:80]),
		.web		(vct_wbv_wr_en_wb[5]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[87:80]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[87:80]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[87:80]),
		.rae		(vrf_store_addrsl2_rd),
		.rde		(nxt_vrf_data_from_mu[87:80])
		);

vu_buf	memsl3lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[9]),
		.waa		(vrf_load_addrsl3_wb),
		.dina		(su_data_to_from[79:72]),
		.web		(vct_wbv_wr_en_wb[4]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[79:72]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[79:72]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[79:72]),
		.rae		(vrf_store_addrsl3_rd),
		.rde		(nxt_vrf_data_from_mu[79:72])
		);

vu_buf	memsl3hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[8]),
		.waa		(vrf_load_addrsl3_wb),
		.dina		(su_data_to_from[71:64]),
		.web		(vct_wbv_wr_en_wb[4]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[71:64]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[71:64]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[71:64]),
		.rae		(vrf_store_addrsl3_rd),
		.rde		(nxt_vrf_data_from_mu[71:64])
		);

vu_buf	memsl4lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[7]),
		.waa		(vrf_load_addrsl4_wb),
		.dina		(su_data_to_from[63:56]),
		.web		(vct_wbv_wr_en_wb[3]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[63:56]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[63:56]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[63:56]),
		.rae		(vrf_store_addrsl4_rd),
		.rde		(nxt_vrf_data_from_mu[63:56])
		);

vu_buf	memsl4hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[6]),
		.waa		(vrf_load_addrsl4_wb),
		.dina		(su_data_to_from[55:48]),
		.web		(vct_wbv_wr_en_wb[3]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[55:48]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[55:48]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[55:48]),
		.rae		(vrf_store_addrsl4_rd),
		.rde		(nxt_vrf_data_from_mu[55:48])
		);

vu_buf	memsl5lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[5]),
		.waa		(vrf_load_addrsl5_wb),
		.dina		(su_data_to_from[47:40]),
		.web		(vct_wbv_wr_en_wb[2]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[47:40]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[47:40]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[47:40]),
		.rae		(vrf_store_addrsl5_rd),
		.rde		(nxt_vrf_data_from_mu[47:40])
		);

vu_buf	memsl5hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[4]),
		.waa		(vrf_load_addrsl5_wb),
		.dina		(su_data_to_from[39:32]),
		.web		(vct_wbv_wr_en_wb[2]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[39:32]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[39:32]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[39:32]),
		.rae		(vrf_store_addrsl5_rd),
		.rde		(nxt_vrf_data_from_mu[39:32])
		);

vu_buf	memsl6lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[3]),
		.waa		(vrf_load_addrsl6_wb),
		.dina		(su_data_to_from[31:24]),
		.web		(vct_wbv_wr_en_wb[1]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[31:24]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[31:24]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[31:24]),
		.rae		(vrf_store_addrsl6_rd),
		.rde		(nxt_vrf_data_from_mu[31:24])
		);

vu_buf	memsl6hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[2]),
		.waa		(vrf_load_addrsl6_wb),
		.dina		(su_data_to_from[23:16]),
		.web		(vct_wbv_wr_en_wb[1]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[23:16]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[23:16]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[23:16]),
		.rae		(vrf_store_addrsl6_rd),
		.rde		(nxt_vrf_data_from_mu[23:16])
		);

vu_buf	memsl7lo (
		.clk		(clk_b),
		.wea		(su_bwe_wb[1]),
		.waa		(vrf_load_addrsl7_wb),
		.dina		(su_data_to_from[15:8]),
		.web		(vct_wbv_wr_en_wb[0]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[15:8]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[15:8]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[15:8]),
		.rae		(vrf_store_addrsl7_rd),
		.rde		(nxt_vrf_data_from_mu[15:8])
		);

vu_buf	memsl7hi (
		.clk		(clk_b),
		.wea		(su_bwe_wb[0]),
		.waa		(vrf_load_addrsl7_wb),
		.dina		(su_data_to_from[7:0]),
		.web		(vct_wbv_wr_en_wb[0]),
		.wab		(su_vd_addr_wb),
		.dinb		(vdp_rslt_data_wb[7:0]),
		.rac		(su_vt_addr_rd),
		.rdc		(vrf_data_rd[7:0]),
		.rad		(su_vs_addr_rd),
		.rdd		(vrf_vs_rfout_rd[7:0]),
		.rae		(vrf_store_addrsl7_rd),
		.rde		(nxt_vrf_data_from_mu[7:0])
		);

endmodule  // vurf.v