/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vusl.v,v 1.2 2002/10/22 19:32:46 doug Exp $

/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vusl						*
*	Description:	Vector unit slice which incorporates two vector	* 
*			unit standard datapaths, two multipliers and  	*
*			one control unit.  The register file is 	*
*			implemented in a seperate block from this vusl	*
*			and is hooked up at the top level.  This 	*
*			partitioning was decided upon for physical	*
*			partitioning.					*
*									*
*			This version is for the standard cell		*
*			implementation of the datapath.			*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		4/6/95						*
*									*
*************************************************************************
*/

// eds_vusl.v: 	RSP vector unit top level - instantiation of datapath and control

`timescale 1ns / 10ps

module	vusl (	
		clk,
		reset_l, 
		vrf_vsdata0_mu,
		vrf_vtdata0_mu,
		vrf_vsdata1_mu,
		vrf_vtdata1_mu,

		su_instvld_rd,
		su_instvldk_rd,
		su_vseqone_rd,
		su_instelem_rd,
		su_instfunc_rd, 
		su_rdcmpcd_rd,
		su_rdcryout_rd,
		su_rdcmpcdad_rd,
		su_wrcmpcd_wb,
		su_wrcryout_wb,
		su_wrcmpcdad_wb,

		su_vs_addr_rd,
		su_vd_addr_ac,

		vdi_divrslt0_wb,
		vdi_divrslt1_wb,

		vct_instvld_ac,

		vct_dvtypop_ac,
		vct_vs_addr_ac,

		vdp_rslt_data0_wb,
		vdp_rslt_data1_wb,

		vu_ls_data,
		su_cont_from

	   ) ;


	input	clk;				/* vu clock */
	input	reset_l;			/* vu active low reset */


	input	[15:0]	vrf_vsdata0_mu;		// vs port read data slice 0 from register file
	input	[15:0]	vrf_vtdata0_mu;		// vt port read data slice 0 from register file
	input	[15:0]	vrf_vsdata1_mu;		// vs port read data slice 1 from register file
	input	[15:0]	vrf_vtdata1_mu;		// vt port read data slice 1 from register file

/*
*	The next group are input signals to the control block from
*	the register file read stage of the vector unit datapaths.
*/

	input	su_instvld_rd;			/* valid CP2 instruction for vu */
	input	su_instvldk_rd;			/* valid CP2 instruction for vu with kill */
	input	su_vseqone_rd;			/* vs field of instruction equal to 1 */
	input   [3:0] su_instelem_rd;		/* element field of instruction */
	input   [5:0] su_instfunc_rd;		/* function field of instruction */

	input	su_rdcmpcd_rd;			/* read vector compare code register */
	input	su_rdcryout_rd;			/* read vector carry out register */
	input	su_rdcmpcdad_rd;		/* read vector compare add register */

	input	su_wrcmpcd_wb;			/* write vector compare code register */
	input	su_wrcryout_wb;			/* write vector carry out register */
	input	su_wrcmpcdad_wb;		/* write vector compare add register */

/*
*	The following input signals are for register file address decoding
*	only.
*/

	input	[4:0]	su_vs_addr_rd;		/* register number for vs read */
	input	[4:0]	su_vd_addr_ac;		/* register number for datapath writeback */

	input	[15:0]	vdi_divrslt0_wb;	/* result from divide unit to even datapath */
	input	[15:0]	vdi_divrslt1_wb;	/* result from divide unit to odd datapath */


	output	vct_instvld_ac;			/* valid CP2 instruction in AC */

	output	vct_dvtypop_ac;		/* divide or move type instruction in AC */
	output	[2:0]	vct_vs_addr_ac;	/* register number for vs read used as element field for div */

	output	[15:0]	vdp_rslt_data0_wb;	/* VU result data for even slice */
	output	[15:0]	vdp_rslt_data1_wb;	/* VU result data for odd slice */

	output	[3:0]	vu_ls_data;	/* data for control register moves */
	input	[3:0]	su_cont_from;	/* data for control register moves */
	
/*
*	The following signals are the input signals to the 
*	vector unit control block.
*
*	The first group are input signals to the control block 
*	which provide general control such as clocks, reset
*	hold and instruction decoding.
*
*/

/*
*	The next group of signals are outputs from the RD stage of the
*	datapath which drive data to other datapaths in the case of 
*	passing scalar data to other datapaths.
*/

	wire	[15:0]	vdp_opndt0_rd;	/* vt data from rf in RD stage in vector 0 */
	wire	[15:0]	vdp_opndt1_rd;	/* vt data from rf in RD stage in vector 1 */

/*
*	The next group are input signals to the control block from
*	the multiply stage of the vector unit datapaths.
*/

	wire	vdp_aluovr0_mu;		/* overflow bit from alu vector 0 */
	wire	vdp_aluco0_mu;		/* carry out from alu vector 0 */
	wire	vdp_vs_zero0_mu;	/* vs operand is equal to zero vector 0 */
	wire	vdp_vt_zero0_mu;	/* vt operand is equal to zero vector 0 */
	wire	vdp_aluzero0_mu;	/* alu result is equal to zero vector 0 */
	wire	vdp_aluone0_mu;		/* alu result is equal to all ones vector 0 */

	wire	vdp_aluovr1_mu;		/* overflow bit from alu vector 1 */
	wire	vdp_aluco1_mu;		/* carry out from alu vector 1 */
	wire	vdp_vs_zero1_mu;	/* vs operand is equal to zero vector 1 */
	wire	vdp_vt_zero1_mu;	/* vt operand is equal to zero vector 1 */
	wire	vdp_aluzero1_mu;	/* alu result operand s is equal to zero vector 1 */
	wire	vdp_aluone1_mu;		/* alu result is equal to all ones vector 1 */



/*
*	The next group are input signals to the control block from
*	the accumulate stage of the vector unit datapaths.
*/

	wire	vdp_cslwco0_ac;		/* carry out from low csa vector 0 */
	wire	vdp_csupco0_ac;		/* carry out from high csa vector 0 */
	wire	vdp_addlwco0_ac;	/* carry out from low adder vector 0 */
	wire	vdp_addlwov0_ac;	/* overflow from low adder vector 0 */
	wire	vdp_addupco0_ac;	/* carry out from high adder vector 0 */
	wire	vdp_addupov0_ac;	/* overflow from high adder vector 0 */
	wire	vdp_incrco0_ac;		/* carry out from incrementer vector 0 */

	wire	vdp_cslwco1_ac;		/* carry out from low csa vector 1 */
	wire	vdp_csupco1_ac;		/* carry out from high csa vector 1 */
	wire	vdp_addlwco1_ac;	/* carry out from low adder vector 1 */
	wire	vdp_addlwov1_ac;	/* overflow from low adder vector 1 */
	wire	vdp_addupco1_ac;	/* carry out from high adder vector 1 */
	wire	vdp_addupov1_ac;	/* overflow from high adder vector 1 */
	wire	vdp_incrco1_ac;		/* carry out from incrementer vector 1 */

	wire	vmu_co_clal0_ac;	/* carry out from 16 bit product of multiplier vector 0 */
	wire	vmu_co_clal1_ac;	/* carry out from 16 bit product of multiplier vector 1 */
	wire	vmu_co_clah0_ac;	/* false carry out from multiplier vector 0 */
	wire	vmu_co_clah1_ac;	/* false carry out from multiplier vector 1 */

/*
*	The next group are input signals to the control block from
*	the writeback stage of the vector unit datapaths.
*/


	wire	vdp_acc0bit15_wb;	/* bit 15 of accumulator used to determine sign vector 0 */
	wire	vdp_acc0bit21_wb;	/* bit 21 of accumulator used for macq vector 0 */
	wire	vdp_acc0bit31_wb;	/* bit 31 of accumulator used to determine sign vector 0 */
	wire	vdp_acc0bit47_wb;	/* bit 47 of accumulator used to determine sign vector 0 */

	wire	vdp_achizero0_wb;	/* 47:32 of accumulator equal zero vector 0 */
	wire	vdp_acmizero0_wb;	/* 31:16 of accumulator equal zero vector 0 */
	wire	vdp_achione0_wb;	/* 47:32 of accumulator equal one vector 0 */


	wire	vdp_acc1bit15_wb;	/* bit 15 of accumulator used to determine sign vector 1*/
	wire	vdp_acc1bit21_wb;	/* bit 21 of accumulator used for macq vector 1 */
	wire	vdp_acc1bit31_wb;	/* bit 31 of accumulator used to determine sign vector 1 */
	wire	vdp_acc1bit47_wb;	/* bit 47 of accumulator used to determine sign vector 1 */

	wire	vdp_achizero1_wb;	/* 47:32 of accumulator equal zero vector 1 */
	wire	vdp_acmizero1_wb;	/* 31:16 of accumulator equal zero vector 1 */
	wire	vdp_achione1_wb;	/* 47:32 of accumulator equal one vector 1 */


/*
*	The following signals are the output signals for the 
*	vector unit control block.
*/

/*
*	The next group are output control signals for the
*	multiply stage of the vector unit datapath.
*/

	wire	[1:0]	vct_couprsl0_mu;	/* selects for multiply upper carry out all vectors */
	wire	[1:0]	vct_couprsl1_mu;	/* selects for multiply upper carry out all vectors */

	wire	[1:0]	vct_smuprsl0_mu;	/* selects for multiply upper sum out all vectors */
	wire	[1:0]	vct_smuprsl1_mu;	/* selects for multiply upper sum out all vectors */

	wire	[1:0]	vct_colwrsl0_mu;	/* selects for multiply lower carry out register all vectors */
	wire	[1:0]	vct_colwrsl1_mu;	/* selects for multiply lower carry out register all vectors */

	wire	[1:0]	vct_smlwrsl0_mu;	/* selects for multiply lower sum out vector 0 */
	wire	[1:0]	vct_smlwrsl1_mu;	/* selects for multiply lower sum out vector 1 */

	wire	[2:0]	vct_aluctl0_mu;		/* control for alu vector 0 */
	wire	vct_alucin0_mu;			/* carry in to alu vector 0 */

	wire	[2:0]	vct_aluctl1_mu;		/* control for alu vector 1 */
	wire	vct_alucin1_mu;			/* carry in to alu vector 1 */


/*
*	The next group of signals are inputs to the MU stage of the
*	datapath from the multiplier block which was done as a seperate module.
*/

	wire	[15:0]	vmu_sumlower0_mu;	/* lower sum vector for multiplier to datapath element 0 */
	wire	[15:0]	vmu_carrylower0_mu;	/* lower carry vector for multiplier to datapath element 0 */
	wire	[15:0]	vmu_sumupper0_mu;	/* upper sum vector for multiplier to datapath element 0 */
	wire	[15:0]	vmu_carryupper0_mu;	/* upper carry vector for multiplier to datapath element 0 */

	wire	[15:0]	vmu_sumlower1_mu;	/* lower sum vector for multiplier to datapath element 1 */
	wire	[15:0]	vmu_carrylower1_mu;	/* lower carry vector for multiplier to datapath element 1 */
	wire	[15:0]	vmu_sumupper1_mu;	/* upper sum vector for multiplier to datapath element 1 */
	wire	[15:0]	vmu_carryupper1_mu;	/* upper carry vector for multiplier to datapath element 1 */


/*
*	The next group of signals are outputs from the vu control block
*	control the multiplier block which was done as a seperate module.
*/

	wire		vct_sgnmplcnd_mu;	/* multiplicand is signed */
	wire		vct_sgnmplr_mu;		/* multiplier is signed */
	wire		vct_shftlftone0_mu;	/* shift multiply product left by one */
	wire		vct_shftlftone1_mu;	/* shift multiply product left by one */


/*
*	The next group of signals are outputs from the MU stage of the
*	datapath which drive data to the multiplier block which was 
*	done as a seperate module.
*/

	wire	[15:0]	vdp_mplcnd0_mu;	/* multiplicand from datapath in vector 0 */
	wire	[15:0]	vdp_mplr0_mu;	/* multiplier from datapath in vector 0 */

	wire	[15:0]	vdp_mplcnd1_mu;	/* multiplicand from datapath in vector 1 */
	wire	[15:0]	vdp_mplr1_mu;	/* multiplier from datapath in vector 1 */


/*
*	The next group are output control signals for the
*	accumulate stage of the vector unit datapath.
*/

	wire	[1:0]	vct_aclwsl0_ac;		/* selects input for lower mux of accumulator vector 0 */
	wire	[1:0]	vct_aclwsl1_ac;		/* selects input for lower mux of accumulator vector 1 */

	wire	vct_cslwcsl0_ac;		/* select for input c of lower csa all vectors */
	wire	vct_cslwcsl1_ac;		/* select for input c of lower csa all vectors */


	wire	[1:0]	vct_acmisl0_ac;		/* selects for middle mux of accumulator vector 0 */
	wire	[1:0]	vct_acmisl1_ac;		/* selects for middle mux of accumulator vector 1 */

	wire	[1:0]	vct_acupsl0_ac;		/* selects input for upper mux of accumulator vector 0 */
	wire	[1:0]	vct_acupsl1_ac;		/* selects input for upper mux of accumulator vector 1 */

	wire	[3:0]	vct_rndvlu0_ac;	/* round value for multiplies/byte adds vector 0 */
	wire	[1:0]	vct_cslwasl0_ac;	/* selects for input a of lower csa vector 0 */
	wire	[1:0]	vct_cslwbsl0_ac;	/* selects for input b of lower csa vector 0 */
	wire	vdp_csalwci0_ac;		/* carry in to lower csa vector 0 */
	wire	vct_addlwci0_ac;		/* carry in to lower adder vector 0 */
	wire	[1:0]	vct_csupasl0_ac;	/* selects for input a of upper csa vector 0 */
	wire	[1:0]	vct_csupbsl0_ac;	/* selects for input b of upper csa vector 0 */
	wire	vct_csupcen0_ac;		/* input c enable for upper csa even vectors */
	wire	vdp_csaupci0_ac;		/* carry in to upper csa vector 0 */
	wire	vdp_addupci0_ac;		/* carry in to upper adder vector 0 */
	wire	vct_incrdwn0_ac;		/* increment/decrement control signal vector 0 */
	wire	vct_incrci0_ac;			/* increment/decrement enable signal vector 0 */
	wire	vct_incrmxsl0_ac;	/* mux selects for incrementer output vector 0 */

	wire	[3:0]	vct_rndvlu1_ac;	/* round value for multiplies/byte adds vector 1 */
	wire	[1:0]	vct_cslwasl1_ac;	/* selects for input a of lower csa vector 1 */
	wire	[1:0]	vct_cslwbsl1_ac;	/* selects for input b of lower csa vector 1 */
	wire	vdp_csalwci1_ac;		/* carry in to lower csa vector 1 */
	wire	vct_addlwci1_ac;		/* carry in to lower adder vector 1 */
	wire	[1:0]	vct_csupasl1_ac;	/* selects for input a of upper csa vector 1 */
	wire	[1:0]	vct_csupbsl1_ac;	/* selects for input b of upper csa vector 1 */
	wire	vct_csupcen1_ac;		/* input c enable for upper csa odd vectors */
	wire	vdp_csaupci1_ac;		/* carry in to upper csa vector 1 */
	wire	vdp_addupci1_ac;		/* carry in to upper adder vector 1 */
	wire	vct_incrdwn1_ac;		/* increment/decrement control signal vector 1 */
	wire	vct_incrci1_ac;			/* increment/decrement enable signal vector 1 */
	wire	vct_incrmxsl1_ac;	/* mux select for incrementer output vector 1 */


/*
*	The next group are output control signals for the
*	write back stage of the vector unit datapath.
*/

	wire	[2:0]	vct_rsltsl0_wb;		/* selects for result mux vector 0 */
	wire	[2:0]	vct_rsltsl1_wb;		/* selects for result mux vector 1 */

	wire	[2:0]	vct_clprslt0_wb;	/* clamp value for all clamping vector 0 */
	wire	[2:0]	vct_clprslt1_wb;	/* clamp value for all clamping vector 1 */


/*
*	???? Need to ensure feedthroughs for all signals
*	coming out of the top of the datapath and going 
*	into the bottom.
*/

	assign	vdp_csalwci0_ac =	0 ;
	assign	vdp_csalwci1_ac =	0 ;


	wire	[4:0]	su_vd_addr_wb;	/* vd address in WB stage */
	wire	su_wbv_wr_en_wb;	/* write enable for datapath results */
	wire	[3:0]	su_bwe_wb;	/* load port byte write enable */



vuctl	vuctl1 (	

		.clk				(clk),
		.reset_l			(reset_l),
		.su_instvld_rd			(su_instvld_rd),
		.su_instvldk_rd			(su_instvldk_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd),
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.vdp_vs_sign0_mu		(vrf_vsdata0_mu[15]),
		.vdp_vt_sign0_mu		(vrf_vtdata0_mu[15]),
		.vdp_vs_zero0_mu		(vdp_vs_zero0_mu),
		.vdp_vt_zero0_mu		(vdp_vt_zero0_mu),
		.vdp_aluovr0_mu			(vdp_aluovr0_mu),
		.vdp_aluco0_mu			(vdp_aluco0_mu),
		.vdp_aluzero0_mu		(vdp_aluzero0_mu),
		.vdp_aluone0_mu			(vdp_aluone0_mu),

		.vdp_vs_sign1_mu		(vrf_vsdata1_mu[15]),
		.vdp_vt_sign1_mu		(vrf_vtdata1_mu[15]),
		.vdp_vs_zero1_mu		(vdp_vs_zero1_mu),
		.vdp_vt_zero1_mu		(vdp_vt_zero1_mu),
		.vdp_aluovr1_mu			(vdp_aluovr1_mu),
		.vdp_aluco1_mu			(vdp_aluco1_mu),
		.vdp_aluzero1_mu		(vdp_aluzero1_mu),
		.vdp_aluone1_mu			(vdp_aluone1_mu),

		.vdp_addlwco0_ac		(vdp_addlwco0_ac),
		.vdp_addlwov0_ac		(vdp_addlwov0_ac),
		.vdp_csupco0_ac			(vdp_csupco0_ac),
		.vdp_addupco0_ac		(vdp_addupco0_ac),

		.vdp_addlwco1_ac		(vdp_addlwco1_ac),
		.vdp_addlwov1_ac		(vdp_addlwov1_ac),
		.vdp_csupco1_ac			(vdp_csupco1_ac),
		.vdp_addupco1_ac		(vdp_addupco1_ac),

		.vmu_co_clal0_ac		(vmu_co_clal0_ac),
		.vmu_co_clal1_ac		(vmu_co_clal1_ac),
		.vmu_co_clah0_ac		(vmu_co_clah0_ac),
		.vmu_co_clah1_ac		(vmu_co_clah1_ac),

		.vdp_acc0bit15_wb		(vdp_acc0bit15_wb),
		.vdp_acc0bit21_wb		(vdp_acc0bit21_wb),
		.vdp_acc0bit31_wb		(vdp_acc0bit31_wb),
		.vdp_acc0bit47_wb		(vdp_acc0bit47_wb),
		.vdp_achizero0_wb		(vdp_achizero0_wb),
		.vdp_acmizero0_wb		(vdp_acmizero0_wb),
		.vdp_achione0_wb		(vdp_achione0_wb),

		.vdp_acc1bit15_wb		(vdp_acc1bit15_wb),
		.vdp_acc1bit21_wb		(vdp_acc1bit21_wb),
		.vdp_acc1bit31_wb		(vdp_acc1bit31_wb),
		.vdp_acc1bit47_wb		(vdp_acc1bit47_wb),
		.vdp_achizero1_wb		(vdp_achizero1_wb),
		.vdp_acmizero1_wb		(vdp_acmizero1_wb),
		.vdp_achione1_wb		(vdp_achione1_wb),

		.vct_couprsl0_mu		(vct_couprsl0_mu),
		.vct_couprsl1_mu		(vct_couprsl1_mu),
		.vct_smuprsl0_mu		(vct_smuprsl0_mu),
		.vct_smuprsl1_mu		(vct_smuprsl1_mu),
		.vct_colwrsl0_mu		(vct_colwrsl0_mu),
		.vct_colwrsl1_mu		(vct_colwrsl1_mu),
		.vct_smlwrsl0_mu		(vct_smlwrsl0_mu),
		.vct_smlwrsl1_mu		(vct_smlwrsl1_mu),

		.vct_sgnmplr_mu			(vct_sgnmplr_mu),
		.vct_sgnmplcnd_mu		(vct_sgnmplcnd_mu),
		.vct_shftlftone0_mu		(vct_shftlftone0_mu),
		.vct_shftlftone1_mu		(vct_shftlftone1_mu),

		.vct_aluctl0_mu			(vct_aluctl0_mu),
		.vct_alucin0_mu			(vct_alucin0_mu),
		.vct_alucmpvt0_mu		(vct_alucmpvt0_mu), 
		.vct_cmpvt0_mu			(vct_cmpvt0_mu), 

		.vct_aluctl1_mu			(vct_aluctl1_mu),
		.vct_alucin1_mu			(vct_alucin1_mu),
		.vct_alucmpvt1_mu		(vct_alucmpvt1_mu), 
		.vct_cmpvt1_mu			(vct_cmpvt1_mu), 

		.vct_instvld_ac			(vct_instvld_ac),
		.vct_aclwsl0_ac			(vct_aclwsl0_ac), 
		.vct_aclwsl1_ac			(vct_aclwsl1_ac), 

		.vct_cslwcsl0_ac		(vct_cslwcsl0_ac),
		.vct_cslwcsl1_ac		(vct_cslwcsl1_ac),
		.vct_csupcen0_ac		(vct_csupcen0_ac),
		.vct_csupcen1_ac		(vct_csupcen1_ac),

		.vct_acmisl0_ac			(vct_acmisl0_ac),
		.vct_acmisl1_ac			(vct_acmisl1_ac),

		.vct_acupsl0_ac			(vct_acupsl0_ac), 
		.vct_acupsl1_ac			(vct_acupsl1_ac), 

		.vct_rndvlu0_ac			(vct_rndvlu0_ac),
		.vct_cslwasl0_ac		(vct_cslwasl0_ac),
		.vct_cslwbsl0_ac		(vct_cslwbsl0_ac),
		.vct_addlwci0_ac		(vct_addlwci0_ac),
		.vct_csupasl0_ac		(vct_csupasl0_ac),
		.vct_csupbsl0_ac		(vct_csupbsl0_ac),
		.vct_incrdwn0_ac		(vct_incrdwn0_ac),
		.vct_incrci0_ac			(vct_incrci0_ac),
		.vct_incrmxsl0_ac		(vct_incrmxsl0_ac),

		.vct_rndvlu1_ac			(vct_rndvlu1_ac),
		.vct_cslwasl1_ac		(vct_cslwasl1_ac),
		.vct_cslwbsl1_ac		(vct_cslwbsl1_ac),
		.vct_addlwci1_ac		(vct_addlwci1_ac),
		.vct_csupasl1_ac		(vct_csupasl1_ac),
		.vct_csupbsl1_ac		(vct_csupbsl1_ac),
		.vct_incrdwn1_ac		(vct_incrdwn1_ac),
		.vct_incrci1_ac			(vct_incrci1_ac),
		.vct_incrmxsl1_ac		(vct_incrmxsl1_ac),

		.vct_rsltsl0_wb			(vct_rsltsl0_wb),
		.vct_rsltsl1_wb			(vct_rsltsl1_wb),

		.vct_clprslt0_wb		(vct_clprslt0_wb),
		.vct_clprslt1_wb		(vct_clprslt1_wb),

		.vu_ls_data			(vu_ls_data), 
		.su_cont_from			(su_cont_from), 

/*
*	The following signals are for register file address decoding
*	only.
*/

		.su_vs_addr_rd			(su_vs_addr_rd),

		.vct_dvtypop_ac			(vct_dvtypop_ac),
		.vct_vs_addr_ac			(vct_vs_addr_ac)

		);


vudp_nonrf vudp0 (
			.clk				(clk),
			.reset_l			(reset_l),

			.vrf_vsdata_mu			(vrf_vsdata0_mu),
			.vrf_vtdata_mu			(vrf_vtdata0_mu),

			.vdpcoutlwrmu			(vct_colwrsl0_mu),
			.vdpsumlwrmu			(vct_smlwrsl0_mu),
			.vdpcoutuprmu			(vct_couprsl0_mu),
			.vdpsumuprmu			(vct_smuprsl0_mu),

			.vdpalumu_cin			(vct_alucin0_mu),
			.vdpalumu			(vct_aluctl0_mu),
			.vdp_aluctl_vt_mu		(vct_alucmpvt0_mu),
			.vdpcompvtmu			(vct_cmpvt0_mu), 


			.vumsumlowermu			(vmu_sumlower0_mu),
			.vumcarrylowermu		(vmu_carrylower0_mu),
			.vumsumuppermu			(vmu_sumupper0_mu),
			.vumcarryuppermu		(vmu_carryupper0_mu),

			.vdprundvluac			(vct_rndvlu0_ac),

			.vdpcsalwrainac			(vct_cslwasl0_ac),
			.vdpcsalwrbinac			(vct_cslwbsl0_ac),
			.vdpcsalwrcinac			(vct_cslwcsl0_ac),
			.vdpcsauprcinnandac		(vct_csupcen0_ac),

			.vdpcsaac_cin			(vdp_csalwci0_ac),

			.vdpaccumlwrac			(vct_aclwsl0_ac),

			.vdpcsauprainac			(vct_csupasl0_ac),
		        .vdpcsauprbinac			(vct_csupbsl0_ac),

		        .vdpcsaac_cout			(vdp_csupco0_ac),

			.vdpadderlwrac_cin		(vct_addlwci0_ac),

		        .vdpincremac_cin		(vct_incrci0_ac),

			.vdpaccummidac			(vct_acmisl0_ac),

		        .vdpincremac_dwn		(vct_incrdwn0_ac),
			.vdpincremxac			(vct_incrmxsl0_ac),
 
		        .vdpaccuprmxac			(vct_acupsl0_ac),


			.vdpslctmxwb			(vct_rsltsl0_wb),
			.vdpclprsltwb			(vct_clprslt0_wb),
			.vdpdivrsltwb			(vdi_divrslt0_wb),



		        .vdpalumu_ovr			(vdp_aluovr0_mu),
			.vdpalumu_cout			(vdp_aluco0_mu),
			.vdpzerodetvsmu_z		(vdp_vs_zero0_mu),
			.vdpzerodetvtmu_z		(vdp_vt_zero0_mu),
			.vdpzerodetalumu_z		(vdp_aluzero0_mu),
			.vdponedetalumu_z		(vdp_aluone0_mu),


		        .vdpadderlwrac_cout		(vdp_addlwco0_ac),
			.vdpadderlwrac_ovr		(vdp_addlwov0_ac),
		        .vdpadderuprac_cout		(vdp_addupco0_ac),
			.vdpadderuprac_ovr		(vdp_addupov0_ac),
			.vdpincremac_cout		(vdp_incrco0_ac),

			.vdpaccmidzerowb_z		(vdp_acmizero0_wb),
			.vdpacchighzerowb_z		(vdp_achizero0_wb),
			.vdpacchighonewb_z		(vdp_achione0_wb),

			.vdpaccsign15wb			(vdp_acc0bit15_wb),
			.vdpaccsign21wb			(vdp_acc0bit21_wb),
			.vdpaccsign31wb			(vdp_acc0bit31_wb),
			.vdpaccsign47wb			(vdp_acc0bit47_wb),

			.vdp_rslt_data_wb		(vdp_rslt_data0_wb)

	      );


vmult	vmult0 (
		.clk				(clk),
		.vum_mplcnd_mu			(vrf_vtdata0_mu),
		.vum_mplr_mu			(vrf_vsdata0_mu),
		.vum_sgnmplcnd_mu		(vct_sgnmplcnd_mu),
		.vum_sgnmplr_mu			(vct_sgnmplr_mu),
		.vum_shiftleft1_mu		(vct_shftlftone0_mu),

		.vum_carryupper_mu		(vmu_carryupper0_mu),
		.vum_carrylower_mu		(vmu_carrylower0_mu),
		.vum_sumupper_mu		(vmu_sumupper0_mu),
		.vum_sumlower_mu		(vmu_sumlower0_mu),

		.vum_col_cla_acc		(vmu_co_clal0_ac),
		.vum_coh_cla_acc		(vmu_co_clah0_ac)
	       );


vudp_nonrf vudp1 (
			.clk				(clk),
			.reset_l			(reset_l),

			.vrf_vsdata_mu			(vrf_vsdata1_mu),
			.vrf_vtdata_mu			(vrf_vtdata1_mu),

			.vdpcoutlwrmu			(vct_colwrsl1_mu),
			.vdpsumlwrmu			(vct_smlwrsl1_mu),
			.vdpcoutuprmu			(vct_couprsl1_mu),
			.vdpsumuprmu			(vct_smuprsl1_mu),

			.vdpalumu_cin			(vct_alucin1_mu),
			.vdpalumu			(vct_aluctl1_mu),
			.vdp_aluctl_vt_mu		(vct_alucmpvt1_mu),
			.vdpcompvtmu			(vct_cmpvt1_mu), 

			.vumsumlowermu			(vmu_sumlower1_mu),
			.vumcarrylowermu		(vmu_carrylower1_mu),
			.vumsumuppermu			(vmu_sumupper1_mu),
			.vumcarryuppermu		(vmu_carryupper1_mu),

			.vdprundvluac			(vct_rndvlu1_ac),

			.vdpcsalwrainac			(vct_cslwasl1_ac),
			.vdpcsalwrbinac			(vct_cslwbsl1_ac),
			.vdpcsalwrcinac			(vct_cslwcsl1_ac),
			.vdpcsauprcinnandac		(vct_csupcen1_ac),

			.vdpcsaac_cin			(vdp_csalwci1_ac),

			.vdpaccumlwrac			(vct_aclwsl1_ac),

			.vdpcsauprainac			(vct_csupasl1_ac),
		        .vdpcsauprbinac			(vct_csupbsl1_ac),

		        .vdpcsaac_cout			(vdp_csupco1_ac),

			.vdpadderlwrac_cin		(vct_addlwci1_ac),

		        .vdpincremac_cin		(vct_incrci1_ac),

			.vdpaccummidac			(vct_acmisl1_ac),

		        .vdpincremac_dwn		(vct_incrdwn1_ac),
			.vdpincremxac			(vct_incrmxsl1_ac),
 
		        .vdpaccuprmxac			(vct_acupsl1_ac),


			.vdpslctmxwb			(vct_rsltsl1_wb),
			.vdpclprsltwb			(vct_clprslt1_wb),
			.vdpdivrsltwb			(vdi_divrslt1_wb),



		        .vdpalumu_ovr			(vdp_aluovr1_mu),
			.vdpalumu_cout			(vdp_aluco1_mu),
			.vdpzerodetvsmu_z		(vdp_vs_zero1_mu),
			.vdpzerodetvtmu_z		(vdp_vt_zero1_mu),
			.vdpzerodetalumu_z		(vdp_aluzero1_mu),
			.vdponedetalumu_z		(vdp_aluone1_mu),

		        .vdpadderlwrac_cout		(vdp_addlwco1_ac),
			.vdpadderlwrac_ovr		(vdp_addlwov1_ac),
		        .vdpadderuprac_cout		(vdp_addupco1_ac),
			.vdpadderuprac_ovr		(vdp_addupov1_ac),
			.vdpincremac_cout		(vdp_incrco1_ac),

			.vdpaccmidzerowb_z		(vdp_acmizero1_wb),
			.vdpacchighzerowb_z		(vdp_achizero1_wb),
			.vdpacchighonewb_z		(vdp_achione1_wb),

			.vdpaccsign15wb			(vdp_acc1bit15_wb),
			.vdpaccsign21wb			(vdp_acc1bit21_wb),
			.vdpaccsign31wb			(vdp_acc1bit31_wb),
			.vdpaccsign47wb			(vdp_acc1bit47_wb),

			.vdp_rslt_data_wb		(vdp_rslt_data1_wb)

	      );


vmult	vmult1 (
		.clk				(clk),
		.vum_mplcnd_mu			(vrf_vtdata1_mu),
		.vum_mplr_mu			(vrf_vsdata1_mu),
		.vum_sgnmplcnd_mu		(vct_sgnmplcnd_mu),
		.vum_sgnmplr_mu			(vct_sgnmplr_mu),
		.vum_shiftleft1_mu		(vct_shftlftone1_mu),

		.vum_carryupper_mu		(vmu_carryupper1_mu),
		.vum_carrylower_mu		(vmu_carrylower1_mu),
		.vum_sumupper_mu		(vmu_sumupper1_mu),
		.vum_sumlower_mu		(vmu_sumlower1_mu),

		.vum_col_cla_acc		(vmu_co_clal1_ac),
		.vum_coh_cla_acc		(vmu_co_clah1_ac)
	       );



endmodule  // vusl