#####################################################################
## Copyright 2000 VAutomation Inc. Nashua NH USA. All rights reserved.
## This software is provided under license and contains proprietary
## and confidential material which is the property of VAutomation Inc.
## HTTP://www.vautomation.com
######################################################################
## File Name: $ $
## Revision: $Name:  $
## Description:
##
##      Script For Leonardo Spectrum
##
##      Synthesis script for vusb 2.0 and ARC processor in Virtex.
##
#######################################################################

# init
clean_all
set part xcv1000ehq240
set process 6
set wire_load xcve1000-6_wc
set virtex_map_iob_registers TRUE
# exemplar constraint file is limited - don't bother
set novendor_constraint_file TRUE
load_library xcv

# vusb files 
analyze -format verilog ../verilog/vusb_fifo.v
analyze -format verilog ../verilog/vusb_up_int_bvci.v
analyze -format verilog ../verilog/vusb_ratematch.v
analyze -format verilog ../verilog/vusb_dpllnrzi.v
analyze -format verilog ../verilog/vusb_sie.v
analyze -format verilog ../verilog/vusb_bvci.v

elaborate vusb_bvci 

# constraints
set_clock -net -name clk -clock_cycle 27.00
set_clock -net -name usb_clk48 -clock_cycle 18.00

# I/O General Constraints - Most I/O don't matter
set input2register 15
set register2output 15

# pre-compile
set no_boundary_optimization FALSE
pre_optimize -boundary
set no_boundary_optimization TRUE

# compile
optimize -target xcv
write -format XDB vusb_bvci.xdb

# save design
auto_write -format EDIF vusb_bvci.edf