/*--------------------------------------------------------------------
-- Copyright 1999 VAutomation Inc. Nashua NH USA. All rights reserved.
-- This software is provided under license and contains proprietary
-- and confidential material which is the property of VAutomation Inc.
-- HTTP://www.vautomation.com
----------------------------------------------------------------------
-- File Name: $file: vusb2.dc $
-- Revision: $Name:  $
-- Description:
--
--      Synopsys Script
--
--      Synthesis script for VUSB 1.1.
--
---------------------------------------------------------------------*/
/* Libaries used are LSI 10K which are typically shipped with Synopsys
 * Replace these with your desired target technology
 */

user_source_file_type = "verilog" /* vhdl | verilog */
user_source_file_ext = .v
user_source_dir = ../verilog

search_path = {. \
get_unix_variable("SYNOPSYS") + "/libraries/syn"};
link_library = { "*" lsi_10k.db }
target_library = { lsi_10k.db }
symbol_library = { lsi_10k.sdb};

 
hdlin_translate_off_skip_text="true"


/* core files */
analyze -f user_source_file_type user_source_dir + /vusb_ratematch + user_source_file_ext
analyze -f user_source_file_type user_source_dir + /vusb_fifo + user_source_file_ext
analyze -f user_source_file_type user_source_dir + /vusb_up_int_bvci + user_source_file_ext
analyze -f user_source_file_type user_source_dir + /vusb_sie + user_source_file_ext
analyze -f user_source_file_type user_source_dir + /vusb_dpllnrzi + user_source_file_ext

/* top level file */
analyze -f user_source_file_type user_source_dir + /vusb_bvci + user_source_file_ext

elaborate vusb_bvci

current_design vusb_bvci

verilogout_no_tri= true
/*dont_touch_network rst*/

create_clock  "clk" -period 40
set_clock_skew -plus_uncertainty 0.2 -minus_uncertainty 0.2 clk
set_drive 0 clk

create_clock  "usb_clk48" -period 20
set_clock_skew -plus_uncertainty 0.2 -minus_uncertainty 0.2 usb_clk48
set_drive 0 usb_clk48

/* prevent synopsys from buffering the clock */
dont_touch_network "clk"
dont_touch_network "usb_clk48"

/* are there any async inputs
set_false_path -from sig_async */

/* input signal delays */
set_input_delay -clock clk 2.0 vusb_i_cmdack
set_input_delay -clock clk 2.0 vusb_i_rdata    
set_input_delay -clock clk 2.0 vusb_i_reop      
set_input_delay -clock clk 2.0 vusb_i_rspval    

set_input_delay -clock clk 2.0 vusb_t_address     
set_input_delay -clock clk 2.0 vusb_t_be
set_input_delay -clock clk 2.0 vusb_t_cmd
set_input_delay -clock clk 2.0 vusb_t_cmdval
set_input_delay -clock clk 2.0 vusb_t_eop
set_input_delay -clock clk 2.0 vusb_t_rspack
set_input_delay -clock clk 2.0 vusb_t_wdata

set_input_delay -clock usb_clk48 2.0 usb_rcv
set_input_delay -clock usb_clk48 2.0 usb_dp
set_input_delay -clock usb_clk48 2.0 usb_dm

/* output delays */

set_output_delay 2 -clock clk vusb_i_address
set_output_delay 2 -clock clk vusb_i_be
set_output_delay 2 -clock clk vusb_i_cmd
set_output_delay 2 -clock clk vusb_i_cmdval
set_output_delay 2 -clock clk vusb_i_eop
set_output_delay 2 -clock clk vusb_i_rspack
set_output_delay 2 -clock clk vusb_i_wdata

set_output_delay 2 -clock clk vusb_t_cmdack
set_output_delay 2 -clock clk vusb_t_rdata
set_output_delay 2 -clock clk vusb_t_reop
set_output_delay 2 -clock clk vusb_t_rspval

set_output_delay 2 -clock clk vusb_irq

set_output_delay 2 -clock usb_clk48  usb_oe_n
set_output_delay 2 -clock clk        usb_speed
set_output_delay 2 -clock usb_clk48  usb_dpo
set_output_delay 2 -clock usb_clk48  usb_dmo


/* compile */
link
check_design
uniquify
set_flatten true
set_cost_priority -delay
/*compile -map_effort medium */
compile -map_effort high -boundary_optimization /*-ungroup_all*/

write -hierarchy -format vhdl -output ./vusb_bvci.vhd
write -hierarchy -output ./vusb_bvci.db

report_design > ./vusb_bvci.syn_rpt
report_hierarchy -full >> ./vusb_bvci.syn_rpt
report_reference >> ./vusb_bvci.syn_rpt
report_resources >> ./vusb_bvci.syn_rpt
report_cell >> ./vusb_bvci.syn_rpt
report_area >> ./vusb_bvci.syn_rpt
report_clock -attributes >> ./vusb_bvci.syn_rpt
report_constraint >> ./vusb_bvci.syn_rpt
check_timing
report_timing -path full -delay max -max_paths 5 > ./vusb_bvci.timing
report_constraints -all_violators >> ./vusb_bvci.syn_rpt
quit