OS Version 5.0 build 00000893
Platform: Win32 on Windows NT

Directory: c:\usb320tg-rev3.0200207-verilog
Bytes per sector = 512
Sectors per cluster = 32
Free clusters = 1470391
Total clusters = 2441157
File 1 of 70
  name:autorun.inf
  ft:01be74ad.77bd2000
  45 -> 45
  txt:1
  dst:c:\usb320tg-rev3.0200207-verilog\autorun.inf
  CopyFile(autorun.inf, c:\usb320tg-rev3.0200207-verilog\autorun.inf)
File 2 of 70
  name:license.txt
  ft:01bd37e9.fb580800
  304 -> 304
  txt:1
  dst:c:\usb320tg-rev3.0200207-verilog\license.txt
  CopyFile(license.txt, c:\usb320tg-rev3.0200207-verilog\license.txt)
File 3 of 70
  name:readme.txt
  ft:01bdf213.237df680
  1610 -> 1610
  txt:1
  dst:c:\usb320tg-rev3.0200207-verilog\readme.txt
  CopyFile(readme.txt, c:\usb320tg-rev3.0200207-verilog\readme.txt)
File 4 of 70
  name:vauto.ico
  ft:01be74ad.6411b980
  766 -> 766
  txt:1
  dst:c:\usb320tg-rev3.0200207-verilog\vauto.ico
  CopyFile(vauto.ico, c:\usb320tg-rev3.0200207-verilog\vauto.ico)
File 5 of 70
  name:doc\pdf\VUSBrelnotes.pdf
  ft:01c23319.a4b01f80
  121519 -> 146539
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\doc\pdf\VUSBrelnotes.pdf
  createDir(c:\usb320tg-rev3.0200207-verilog\doc\pdf)
    00000003
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\doc) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\doc\pdf) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\doc\pdf\VUSBrelnotes.pdf)
  Decode()
  Done
File 6 of 70
  name:doc\pdf\vusb_rf.pdf
  ft:01c22cf0.d29539ae
  517350 -> 600319
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\doc\pdf\vusb_rf.pdf
  createDir(c:\usb320tg-rev3.0200207-verilog\doc\pdf)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\doc\pdf\vusb_rf.pdf)
  Decode()
  Done
File 7 of 70
  name:HCMAPTBL.IDX
  ft:01c22d12.79730806
  12 -> 12
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\HCMAPTBL.IDX
  createDir(c:\usb320tg-rev3.0200207-verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\HCMAPTBL.IDX)
  Decode()
  Done
File 8 of 70
  name:makefile
  ft:01c22cf2.5e016d1b
  811 -> 2315
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\makefile
  createDir(c:\usb320tg-rev3.0200207-verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\makefile)
  Decode()
  Done
File 9 of 70
  name:read_me.txt
  ft:01c22cf0.b6f11906
  96 -> 109
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\read_me.txt
  createDir(c:\usb320tg-rev3.0200207-verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\read_me.txt)
  Decode()
  Done
File 10 of 70
  name:scripts\Exemplar\vusb_bvci.tcl
  ft:01c22cf2.fb5e3d72
  718 -> 1607
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\scripts\Exemplar\vusb_bvci.tcl
  createDir(c:\usb320tg-rev3.0200207-verilog\scripts\Exemplar)
    00000003
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\scripts) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\scripts\Exemplar) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\scripts\Exemplar\vusb_bvci.tcl)
  Decode()
  Done
File 11 of 70
  name:scripts\nc_verilog\cds.lib
  ft:01c22cf3.000fd8ba
  25 -> 27
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog\cds.lib
  createDir(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog\cds.lib)
  Decode()
  Done
File 12 of 70
  name:scripts\nc_verilog\hdl.var
  ft:01c22cf3.046478c1
  23 -> 22
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog\hdl.var
  createDir(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog\hdl.var)
  Decode()
  Done
File 13 of 70
  name:scripts\nc_verilog\script.tcl
  ft:01c22cf3.09114f5b
  82 -> 96
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog\script.tcl
  createDir(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\scripts\nc_verilog\script.tcl)
  Decode()
  Done
File 14 of 70
  name:scripts\Synopsys\vusb_bvci.dc
  ft:01c22cf2.fac3455b
  1337 -> 4248
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\scripts\Synopsys\vusb_bvci.dc
  createDir(c:\usb320tg-rev3.0200207-verilog\scripts\Synopsys)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\scripts\Synopsys) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\scripts\Synopsys\vusb_bvci.dc)
  Decode()
  Done
File 15 of 70
  name:sim\makefile
  ft:01c22cf2.f9e0c712
  1432 -> 4354
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\makefile
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\sim) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\makefile)
  Decode()
  Done
File 16 of 70
  name:sim\nc_verilog_runtest.gccsparcOS5
  ft:01c22cf3.121eb1af
  454 -> 1081
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\nc_verilog_runtest.gccsparcOS5
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\nc_verilog_runtest.gccsparcOS5)
  Decode()
  Done
File 17 of 70
  name:sim\nc_verilog_runtest.linux
  ft:01c22cf3.0db23a42
  440 -> 1005
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\nc_verilog_runtest.linux
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\nc_verilog_runtest.linux)
  Decode()
  Done
File 18 of 70
  name:sim\runtest.bat
  ft:01c22cf2.fa2aaf9b
  339 -> 656
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\runtest.bat
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\runtest.bat)
  Decode()
  Done
File 19 of 70
  name:sim\runtest.sh
  ft:01c22cf2.fa048a2b
  411 -> 905
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\runtest.sh
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\runtest.sh)
  Decode()
  Done
File 20 of 70
  name:sim\startup.do
  ft:01c22cf0.e640876e
  106 -> 133
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\startup.do
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\startup.do)
  Decode()
  Done
File 21 of 70
  name:sim\vcs_verilog_runtest.gccsparcOS5
  ft:01c22cf3.1b4d74c5
  230 -> 385
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\vcs_verilog_runtest.gccsparcOS5
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\vcs_verilog_runtest.gccsparcOS5)
  Decode()
  Done
File 22 of 70
  name:sim\vcs_verilog_runtest.linux
  ft:01c22cf3.16c1feed
  225 -> 380
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\vcs_verilog_runtest.linux
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\vcs_verilog_runtest.linux)
  Decode()
  Done
File 23 of 70
  name:sim\wave.do
  ft:01c22cf0.e14e8cf9
  483 -> 2696
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\sim\wave.do
  createDir(c:\usb320tg-rev3.0200207-verilog\sim)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\sim\wave.do)
  Decode()
  Done
File 24 of 70
  name:software\arc\APILevelTestCode\CMemorySegment.cpp
  ft:01c1e19d.c4be3780
  1371 -> 6885
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\CMemorySegment.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode)
    00000003
    00000003
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\arc) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\CMemorySegment.cpp)
  Decode()
  Done
File 25 of 70
  name:software\arc\APILevelTestCode\CMemorySegment.h
  ft:01c1d676.17640380
  1147 -> 3719
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\CMemorySegment.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\CMemorySegment.h)
  Decode()
  Done
File 26 of 70
  name:software\arc\APILevelTestCode\MainEntry.cpp
  ft:01c228e7.7842df00
  5905 -> 34021
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\MainEntry.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\MainEntry.cpp)
  Decode()
  Done
File 27 of 70
  name:software\arc\APILevelTestCode\USB1_Common.h
  ft:01c1ea0e.2be5b280
  1611 -> 5300
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\USB1_Common.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\USB1_Common.h)
  Decode()
  Done
File 28 of 70
  name:software\arc\APILevelTestCode\usb_init.cpp
  ft:01c2287e.b9eb6f80
  3550 -> 15592
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\usb_init.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\APILevelTestCode\usb_init.cpp)
  Decode()
  Done
File 29 of 70
  name:software\arc\arc_src\arc_vector_table.s
  ft:01c0dd57.17595e80
  386 -> 1220
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\arc_vector_table.s
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\arc_vector_table.s)
  Decode()
  Done
File 30 of 70
  name:software\arc\arc_src\DeviceSpecificInclude.h
  ft:01c1eb07.38016b00
  527 -> 1352
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\DeviceSpecificInclude.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\DeviceSpecificInclude.h)
  Decode()
  Done
File 31 of 70
  name:software\arc\arc_src\InterruptControllerInterface.cpp
  ft:01c0f5b5.b1f6c880
  1701 -> 6453
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\InterruptControllerInterface.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\InterruptControllerInterface.cpp)
  Decode()
  Done
File 32 of 70
  name:software\arc\arc_src\Makefile
  ft:01c19944.ef051c80
  443 -> 1259
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\Makefile
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\Makefile)
  Decode()
  Done
File 33 of 70
  name:software\arc\arc_src\MessageIO.cpp
  ft:01c1fa91.2c172200
  1325 -> 4771
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\MessageIO.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\MessageIO.cpp)
  Decode()
  Done
File 34 of 70
  name:software\arc\arc_src\SystemAccess.cpp
  ft:01c1f5cc.bc0a2700
  1530 -> 3700
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\SystemAccess.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\SystemAccess.cpp)
  Decode()
  Done
File 35 of 70
  name:software\arc\arc_src\VirtualComponentInterface.cpp
  ft:01c1fab9.056ce180
  1767 -> 6226
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\VirtualComponentInterface.cpp
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\arc_src\VirtualComponentInterface.cpp)
  Decode()
  Done
File 36 of 70
  name:software\arc\common_include\DataTypes.h
  ft:01c1bee2.73563380
  484 -> 1078
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\DataTypes.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\DataTypes.h)
  Decode()
  Done
File 37 of 70
  name:software\arc\common_include\InterruptControllerInterface.h
  ft:01c1beda.8402ab80
  1469 -> 3980
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\InterruptControllerInterface.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\InterruptControllerInterface.h)
  Decode()
  Done
File 38 of 70
  name:software\arc\common_include\MainEntry.h
  ft:01c1bee0.89fb8b00
  685 -> 1356
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\MainEntry.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\MainEntry.h)
  Decode()
  Done
File 39 of 70
  name:software\arc\common_include\MessageIO.h
  ft:01c1f539.b6173600
  1016 -> 2813
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\MessageIO.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\MessageIO.h)
  Decode()
  Done
File 40 of 70
  name:software\arc\common_include\SystemAccess.h
  ft:01c1d4f9.e5c62d80
  1846 -> 4974
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\SystemAccess.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\SystemAccess.h)
  Decode()
  Done
File 41 of 70
  name:software\arc\common_include\VirtualComponentInterface.h
  ft:01c1dcdb.ce4a2a00
  2336 -> 7346
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\VirtualComponentInterface.h
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\common_include\VirtualComponentInterface.h)
  Decode()
  Done
File 42 of 70
  name:software\arc\makefile
  ft:01c1567b.ecfc2c00
  335 -> 697
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\makefile
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\makefile)
  Decode()
  Done
File 43 of 70
  name:software\arc\vusbtest.map
  ft:01c15678.45c9c580
  427 -> 931
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\arc\vusbtest.map
  createDir(c:\usb320tg-rev3.0200207-verilog\software\arc)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\arc\vusbtest.map)
  Decode()
  Done
File 44 of 70
  name:software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\libstdc++.so.2.10.0
  ft:01c22cf2.00bc4392
  579321 -> 2065516
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\libstdc++.so.2.10.0
  createDir(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5)
    00000003
    00000003
    00000003
    00000003
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\libstdc++.so.2.10.0)
  Decode()
  Done
File 45 of 70
  name:software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\SimSocket.dll
  ft:01c22cf1.bcaa95a7
  4436917 -> 19469196
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\SimSocket.dll
  createDir(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\SimSocket.dll)
  Decode()
  Done
File 46 of 70
  name:software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\SimSocketNCVerilog.so
  ft:01c22cf1.f5704d57
  4231688 -> 18935564
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\SimSocketNCVerilog.so
  createDir(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-gccsparcOS5\SimSocketNCVerilog.so)
  Decode()
  Done
File 47 of 70
  name:software\bfm\co_simulation\tests\vusb\lib-linux\SimSocket.dll
  ft:01c22cf2.14463090
  1738631 -> 5679392
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux\SimSocket.dll
  createDir(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux\SimSocket.dll)
  Decode()
  Done
File 48 of 70
  name:software\bfm\co_simulation\tests\vusb\lib-linux\SimSocketNCVerilog.so
  ft:01c22cf2.266a7e94
  1734106 -> 5670470
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux\SimSocketNCVerilog.so
  createDir(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-linux\SimSocketNCVerilog.so)
  Decode()
  Done
File 49 of 70
  name:software\bfm\co_simulation\tests\vusb\lib-VC60\SimSocket.dll
  ft:01c22cf2.30618636
  340521 -> 1466471
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-VC60\SimSocket.dll
  createDir(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-VC60)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-VC60) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\bfm\co_simulation\tests\vusb\lib-VC60\SimSocket.dll)
  Decode()
  Done
File 50 of 70
  name:software\vcs\gccsparcOS5\co_simulation_vcs_verilog.a
  ft:01c22cf3.540019bd
  4972081 -> 21810632
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\vcs\gccsparcOS5\co_simulation_vcs_verilog.a
  createDir(c:\usb320tg-rev3.0200207-verilog\software\vcs\gccsparcOS5)
    00000003
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\vcs) succeeded
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\vcs\gccsparcOS5) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\vcs\gccsparcOS5\co_simulation_vcs_verilog.a)
  Decode()
  Done
File 51 of 70
  name:software\vcs\linux\co_simulation_vcs_verilog.a
  ft:01c22cf3.868ad412
  3452647 -> 14998824
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\vcs\linux\co_simulation_vcs_verilog.a
  createDir(c:\usb320tg-rev3.0200207-verilog\software\vcs\linux)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\software\vcs\linux) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\vcs\linux\co_simulation_vcs_verilog.a)
  Decode()
  Done
File 52 of 70
  name:software\vusb_bfm.tar
  ft:01c22cf1.78cfbd8d
  13337408 -> 54297088
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\software\vusb_bfm.tar
  createDir(c:\usb320tg-rev3.0200207-verilog\software)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\software\vusb_bfm.tar)
  Decode()
  Done
File 53 of 70
  name:verilog\pli.tab
  ft:01c22cf3.8bdc2c1f
  71 -> 151
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\pli.tab
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateDirectory(c:\usb320tg-rev3.0200207-verilog\verilog) succeeded
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\pli.tab)
  Decode()
  Done
File 54 of 70
  name:verilog\pvic_connection_interface.v
  ft:01c22cf2.f5c55f33
  1143 -> 4446
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\pvic_connection_interface.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\pvic_connection_interface.v)
  Decode()
  Done
File 55 of 70
  name:verilog\vcs_default.cfg
  ft:01c22cf3.90b8b185
  782 -> 2982
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vcs_default.cfg
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vcs_default.cfg)
  Decode()
  Done
File 56 of 70
  name:verilog\verilog_source.file
  ft:01c22cf3.956a4ccd
  132 -> 368
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\verilog_source.file
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\verilog_source.file)
  Decode()
  Done
File 57 of 70
  name:verilog\vusb_bias.v
  ft:01c22cf2.f5e9224c
  1371 -> 3771
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_bias.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_bias.v)
  Decode()
  $name$ begins @ 1172
  $name$ contains 60 bytes
  $name$ ends @ 1228
  Done
File 58 of 70
  name:verilog\vusb_bvci.v
  ft:01c22cf2.f61b336f
  7696 -> 28003
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_bvci.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_bvci.v)
  Decode()
  $name$ begins @ 1675
  $name$ contains 60 bytes
  $name$ ends @ 1730
  Done
File 59 of 70
  name:verilog\vusb_bvci_tb.v
  ft:01c22cf2.f64ae23b
  4314 -> 15660
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_bvci_tb.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_bvci_tb.v)
  Decode()
  $name$ begins @ 1575
  $name$ contains 60 bytes
  $name$ ends @ 1630
  Done
File 60 of 70
  name:verilog\vusb_cfg.v
  ft:01c22cf2.f6900616
  1643 -> 3790
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_cfg.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_cfg.v)
  Decode()
  Done
File 61 of 70
  name:verilog\vusb_dpllnrzi.v
  ft:01c22cf2.f6d529f1
  12368 -> 42019
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_dpllnrzi.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_dpllnrzi.v)
  Decode()
  $name$ begins @ 6584
  $name$ contains 60 bytes
  $name$ ends @ 6639
  Done
File 62 of 70
  name:verilog\vusb_fifo.v
  ft:01c22cf2.f6fb4f61
  2497 -> 7651
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_fifo.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_fifo.v)
  Decode()
  $name$ begins @ 2071
  $name$ contains 60 bytes
  $name$ ends @ 2126
  Done
File 63 of 70
  name:verilog\vusb_host_ctl.v
  ft:01c22cf2.f780d269
  112393 -> 522902
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_host_ctl.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_host_ctl.v)
  Decode()
  $name$ begins @ 1034
  $name$ contains 60 bytes
  $name$ ends @ 1089
  Done
File 64 of 70
  name:verilog\vusb_otg_lpbck.v
  ft:01c22cf2.f7ee7e0b
  2632 -> 7971
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_otg_lpbck.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_otg_lpbck.v)
  Decode()
  $name$ begins @ 1143
  $name$ contains 60 bytes
  $name$ ends @ 1198
  Done
File 65 of 70
  name:verilog\vusb_p11.v
  ft:01c22cf2.f8124124
  1714 -> 4025
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_p11.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_p11.v)
  Decode()
  $name$ begins @ 1020
  $name$ contains 60 bytes
  $name$ ends @ 1076
  Done
File 66 of 70
  name:verilog\vusb_ratematch.v
  ft:01c22cf2.f83ac8eb
  5697 -> 23332
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_ratematch.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_ratematch.v)
  Decode()
  $name$ begins @ 1243
  $name$ contains 60 bytes
  $name$ ends @ 1298
  Done
File 67 of 70
  name:verilog\vusb_sie.v
  ft:01c22cf2.f8909d27
  38425 -> 151088
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_sie.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_sie.v)
  Decode()
  $name$ begins @ 1092
  $name$ contains 60 bytes
  $name$ ends @ 1147
  Done
File 68 of 70
  name:verilog\vusb_tb_clk_gen.v
  ft:01c22cf2.f8c2ae4a
  1389 -> 4187
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_tb_clk_gen.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_tb_clk_gen.v)
  Decode()
  $name$ begins @ 1036
  $name$ contains 60 bytes
  $name$ ends @ 1091
  Done
File 69 of 70
  name:verilog\vusb_tst.v
  ft:01c22cf2.f8e8d3ba
  4079 -> 13158
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_tst.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_tst.v)
  Decode()
  $name$ begins @ 1601
  $name$ contains 60 bytes
  $name$ ends @ 1656
  Done
File 70 of 70
  name:verilog\vusb_up_int_bvci.v
  ft:01c22cf2.f926d090
  29579 -> 154536
  txt:0
  dst:c:\usb320tg-rev3.0200207-verilog\verilog\vusb_up_int_bvci.v
  createDir(c:\usb320tg-rev3.0200207-verilog\verilog)
  CreateFile(c:\usb320tg-rev3.0200207-verilog\verilog\vusb_up_int_bvci.v)
  Decode()
  $name$ begins @ 2150
  $name$ contains 60 bytes
  $name$ ends @ 2205
  Done