makefile
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#####################################################################
# Copyright 2000 VAutomation Inc. Nashua NH USA. All rights reserved.
## This software is provided under license and contains proprietary
## and confidential material which is the property of VAutomation Inc.
## HTTP://www.vautomation.com
######################################################################
## File Name: $Workfile: makefile$
## Revision: $Revision: 1.1.1.1 $
## $NoKeywords$
##
## This is the VUSB2 Top Level Simulation Makefile.
##
#######################################################################
#######################################################################
# This file is a UNIX Makefile. It is assumed that the reader has some
# experience with Makefiles. See the man pages for more info on make.
#######################################################################
default: usage
usage:
@echo "USAGE:"
@echo " make sim ; Create VUSB-BFM Simulation database."
# MAKERELEASE REMOVE OFF
# location of VHDL Code
SRC_DIR=../verilog
########################################################################
#
# HDL Compiler & Dependencies
#
########################################################################
# The ANALYZE variable is the command used to "analyze" or compile your
# design for simulation. Replace it with the CAE tool command of choice.
# For MTI:
ANALYZE=vlog +incdir+$(SRC_DIR) -work work.lib
# The L variable is needed so make can figure out what files are
# out of date and need to be recompiled. L is usually the path
# down the current "work" directory.
# For MTI:
L=work.lib/
# The R variable is also needed by make. It simply picks a file
# in the "work" directory which will have it's date stamp compared
# with the source file. This is usually a file created by the analyzer.
# For MTI:
R=/_primary.dat
# The HDL variable is "vhdl" for vhdl and "v" for Verilog.
# Use vhd for old vauto files
HDL=v
# We rely on the dependency list to find all of the other targets.
# Make sure there is a MTI "work" directory. Create one if it's not there.
# Create a MTI simulation database
sim : work.lib $(L)vusb_bvci_tb$(R)
work.lib :
vlib work.lib
vmap work work.lib
vmap arc work.lib
vmap user work.lib
#insert this below
$(L)vusb_bvci_tb$(R) : $(SRC_DIR)/vusb_bvci_tb.$(HDL) \
$(L)vusb_bvci$(R) $(L)pvic_connection_interface$(R) $(L)vusb_tst$(R)
$(ANALYZE) $(SRC_DIR)/vusb_bvci_tb.$(HDL)
$(L)vusb_tst$(R) : $(SRC_DIR)/vusb_tst.$(HDL) \
$(L)vusb_host_ctl$(R) $(L)vusb_p11$(R) $(L)vusb_tb_clk_gen$(R) $(L)vusb_bias$(R) $(L)vusb_otg_lpbck$(R)
$(ANALYZE) $(SRC_DIR)/vusb_tst.$(HDL)
$(L)vusb_bvci$(R) : $(SRC_DIR)/vusb_bvci.$(HDL) \
$(L)vusb_up_int_bvci$(R) $(L)vusb_fifo$(R) \
$(L)vusb_sie$(R) $(L)vusb_dpllnrzi$(R) $(L)vusb_ratematch$(R)
$(ANALYZE) $(SRC_DIR)/vusb_bvci.$(HDL)
$(L)vusb_up_int_bvci$(R) : $(SRC_DIR)/vusb_up_int_bvci.$(HDL) \
$(ANALYZE) $(SRC_DIR)/vusb_up_int_bvci.$(HDL)
: $(SRC_DIR)/vusb_cfg.$(HDL)
$(ANALYZE) $(SRC_DIR)/vusb_cfg.$(HDL)
$(L)vusb_fifo$(R) : $(SRC_DIR)/vusb_fifo.$(HDL) \
$(ANALYZE) $(SRC_DIR)/vusb_fifo.$(HDL)
$(L)vusb_sie$(R) : $(SRC_DIR)/vusb_sie.$(HDL) \
$(ANALYZE) $(SRC_DIR)/vusb_sie.$(HDL)
$(L)vusb_dpllnrzi$(R) : $(SRC_DIR)/vusb_dpllnrzi.$(HDL) \
$(ANALYZE) $(SRC_DIR)/vusb_dpllnrzi.$(HDL)
$(L)vusb_ratematch$(R) : $(SRC_DIR)/vusb_ratematch.$(HDL) \
$(ANALYZE) $(SRC_DIR)/vusb_ratematch.$(HDL)
$(L)pvic_connection_interface$(R) : $(SRC_DIR)/pvic_connection_interface.$(HDL)
$(ANALYZE) $(SRC_DIR)/pvic_connection_interface.$(HDL)
$(L)vusb_host_ctl$(R) : $(SRC_DIR)/vusb_host_ctl.$(HDL) \
$(ANALYZE) $(SRC_DIR)/vusb_host_ctl.$(HDL)
$(L)vusb_p11$(R) : $(SRC_DIR)/vusb_p11.$(HDL)
$(ANALYZE) $(SRC_DIR)/vusb_p11.$(HDL)
$(L)vusb_tb_clk_gen$(R) : $(SRC_DIR)/vusb_tb_clk_gen.$(HDL)
$(ANALYZE) $(SRC_DIR)/vusb_tb_clk_gen.$(HDL)
$(L)vusb_bias$(R) : $(SRC_DIR)/vusb_bias.$(HDL)
$(ANALYZE) $(SRC_DIR)/vusb_bias.$(HDL)
$(L)vusb_otg_lpbck$(R) : $(SRC_DIR)/vusb_otg_lpbck.$(HDL)
$(ANALYZE) $(SRC_DIR)/vusb_otg_lpbck.$(HDL)
########################################################################
#
# Cleanup
#
########################################################################
kill : clean
rm -rf work.lib
clean :
rm -f core *~ transcript vsim.wlf