// Copyright 1994, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
//
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
//
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

module NEC_18M_RDRAM(BusCtrl, BusData, BusEnable, SOut, SIn, TxClk, RxClk, VRef);

// This is an interposer module which wraps around the rdram model
// generated from the schematics and presents the standard rambus rdram
// interface to the user. The wrapper is needed for three reasons:
// 1. maps bus BusData[8:0] to scalar pins {BusData[8]..BusData[0]}
//    the netlister breaks up buses into individual scalar signals
// 2. changes name of rdram from device specific schematic name (e.g. u5top)
//    to generic name rdram.

// wire declarations for standard Rambus rdram interface
inout               BusCtrl;
inout [8:0]         BusData;
input               BusEnable;
output              SOut;
input               SIn;
input               TxClk;
input               RxClk;
input               VRef;

`protect
// u5Top is name of rdram in model created from device schematics
// this model has BusData[8:0] bus broken into individual pins.
u5Top top(
	.BusCtrl(BusCtrl),
	.BusData_8_(BusData[8]),
	.BusData_7_(BusData[7]),
	.BusData_6_(BusData[6]),
	.BusData_5_(BusData[5]),
	.BusData_4_(BusData[4]),
	.BusData_3_(BusData[3]),
	.BusData_2_(BusData[2]),
	.BusData_1_(BusData[1]),
	.BusData_0_(BusData[0]),
	.BusEnable(BusEnable),
	.SOut(SOut),
	.SIn(SIn),
	.TxClk(TxClk),
	.RxClk(RxClk),
	.VRef(VRef));

endmodule

// rdram.v
// Copyright 1992, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
//
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
//
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

/*
// $Log: NEC_18M_Rev.C.0_RDRAM.v,v $
// Revision 1.1  2002/03/28 00:26:11  berndt
//
//
// Initial checkin of rcp hw and behavioral simulation tree from N64 source.
// Cleaned up Makefile.
// Created new top-level make definitions and rules.
// Created top-level directory 'ecad' for tool repository.
// Removed all sgi c,make,os specialties and redirected into ecad.
// Stiched the stdcell library because pieces were missing from the Nintendo source.
// Created stdcell modules that did not exist which only had delay differences.
// Removed all synthesis and gate-level related files, make targets and other code.
//
# Revision 1.2  1994/05/26  01:10:04  hayes
# replacement RAMBUS model, non-encoded for use by VCS RAMBUS Proprietary.
#
# Revision 1.2  1994/04/08  20:44:34  harlan
# Put comment strings around RCS log so doesn't cause
# verilog errors.
#
//Revision 4.55  1994/04/01  23:57:40  lai
//Revision C.0 step tapeout netlist.
//
*/

// Verilog netlist of
//"/home/earth/usr2/u5/revC.0/chip/u5Top"

// HDL models

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5CCAna/u5CCAna.v"
module u5CCAna (ictrl, done, control, resetCap, powerOn, VRef, mclk, powerDownMode);
    inout [5:0] ictrl;
    output done;
    input [5:0] control;
    input resetCap;
    input powerOn;
    input VRef;
    input mclk;
    input powerDownMode;

    reg done;

always @(negedge resetCap)
        if (control == 6'b0)
           begin
           #40
           done = 1;
           end
        else
           begin
           # ((control + 1) * 40)
           done = 1;
           end

always @(posedge resetCap)
        #40 done = 0;

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5Sync/u5Sync.v"
// derived from u5Sync cell schematic dated 8/18/93
module u5Sync (q, clk_b, s_b, vref, Vbiasn);
output q;
input Vbiasn, clk_b, s_b, vref;

supply1 vddA;
supply0 gndA;

tranif0 #(8) P83(n5, vddA, clk_b);
tranif0 P100(n5, vddA, s_b);
tranif0 P4(hnl_0, vddA, hnl_1);
tranif0 P23(hnl_2, vddA, n3);
tranif0 P17(hnl_3, vddA, hnl_1);
tranif0 P20(n4, hnl_3, clkL_b);
tranif0 P10(n1, hnl_4, clkL);
tranif0 P3(n1, hnl_0, clkL_b);
tranif0 P18(n4, hnl_2, clkL);
tranif0 P12(hnl_4, vddA, n2);
not #(1) U122(q, hnl_5);
// make edge verilog-able
not #(0) U102(clkL_b, clkL);
not #(1) U91(hnl_6, hnl_7);
not #(1) U90(hnl_7, n5);
not #(1) U92(clkL, hnl_6);
not #(1) U8(n3, n2);
not #(1) U22(hnl_1, n4);
not #(1) U35(hnl_5, hnl_1);
nand #(1) U7(n2, s_b, n1);
tranif1 N115(hnl_8, gndA, s_b);
tranif1 #(8) N71(n5, hnl_8, clk_b);
tranif1 N24(n4, hnl_9, clkL_b);
tranif1 N21(n4, hnl_10, clkL);
tranif1 N16(hnl_9, gndA, n3);
tranif1 N9(hnl_11, gndA, n2);
tranif1 N2(n1, hnl_12, clkL);
tranif1 N13(n1, hnl_11, clkL_b);
tranif1 N26(hnl_10, gndA, hnl_1);
tranif1 N1(hnl_12, gndA, hnl_1);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffSync/ffSync.v"
primitive ffSync (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D_B:state: output/nextState
          n      1 : ? :   0;
          n      0 : ? :   1;
        // ignore positive edge of clock
          p      ? : ? :   -;
        // ignore data changes on steady clock
          ?      * : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5DLL/u5DLL.v"
// Verilog netlist of
//"/home/earth/usr2/u5/rev1.0/chip/pr4.0/u5DLL"

// HDL file -
// simple latch for u5PhaCmp functionality
primitive latClk (Q, EN, D);
    output Q; reg Q;
    input EN;
    input D;

table
//     EN    D:state:   output/next state
        0   ? :  ?  :     - ; // no change

        1   0 :  ?  :     0 ; // transparent data
        1   1 :  ?  :     1 ; // transparent data
        1   x :  ?  :     x ; // latch data

        x   0 :  1  :     1 ; // reducing pessimism
        x   1 :  0  :     0 ; // reducing pessimism
        p   ? :  ?  :     - ;

endtable
endprimitive

// HDL file - 
// /home/earth/usr2/u5/rev1.0/chip/pr4.0/u5ClkAmp/u5ClkAmp.v"
module u5ClkAmp (clkout, clkout_b, dccrfb_b, vref, pwrDn, dccrfb, clkin, Vbiasn);
    output clkout;
    output clkout_b;
    input dccrfb_b;
    input vref;
    input pwrDn;
    input dccrfb;
    input clkin;
    input Vbiasn;
latClk #(0) mg1(clkout_b, ~pwrDn, clkin);
not #(0) (clkout, clkout_b);

endmodule


// End HDL models


module u5TstCkD (tstclk_b, tstclk);
output tstclk_b;
input tstclk;
supply1 vdd;
supply0 gnd;
not #(0) U4(tstclk_b, hnl_0);
not #(0) U3(hnl_0, hnl_1);
not #(0) U1(hnl_1, tstclk);
endmodule

module u5TstCkA (tstclk, bypass_b, rxclk);
output tstclk;
input bypass_b, rxclk;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

not (weak0,weak1) #(1) U43(hnl_3, hnl_2);
nor #(0) U37(hnl_4, bypass_b, hnl_2);
not #(0) U36(tstclk, hnl_4);
not #(1) U35(hnl_5, bypass_b);
not #(1) U39(hnl_2, hnl_3);
tranif0 P32(hnl_6, vddA, rxclk);
tranif0 P34(hnl_3, hnl_6, bypass_b);
tranif1 N44(hnl_7, gndA, rxclk);
tranif1 N38(hnl_3, hnl_7, hnl_5);
endmodule

module u5TstClk (Vbiasn, slow, tstclk_b, DLLByPassMode_b, ckin, pwrDn, rxclk);
output Vbiasn, slow, tstclk_b;
input DLLByPassMode_b, ckin, pwrDn, rxclk;
supply1 vdd;
supply0 gnd;
u5TstCkD TstCkD(tstclk_b, hnl_8);
u5TstCkA TstCkA(hnl_8, DLLByPassMode_b, rxclk);
assign slow=0;
assign Vbiasn=0;
endmodule

module u5CkBufR (mclk, rclk_b, bypass_b, pwrDn, rckdrv, runclk_b, testCkL_b);
output mclk, rclk_b;
input bypass_b, pwrDn, rckdrv, runclk_b, testCkL_b;
supply1 vdd;
supply0 gnd;
cxfr U1020(m6, run_b, hnl_9, hnl_10);
cxfr U1028(m6, hnl_9, run_b, hnl_11);
cxfr U1003(m1, en_b, hnl_12, hnl_10);
cxfr U1036(m1, hnl_12, en_b, hnl_13);
nand #(1) U1004(run_b, hnl_14, bypass_b);
nand #(1) U1033(en_b, hnl_15, bypass_b);
not #(0) U1052(r6, m3);
not #(0) U1051(r5, m2);
not #(0) U1049(m5, m4);
not #(0) U1029(m4, m3);
not #(0) U1042(m3, m2);
not #(0) U1018(m2, m1);
// same as old model timing
not #(5) U1048(rclk_b, m9);
not #(0) U1047(m9, m8);
not #(0) U1015(m8, m7);
not #(0) U1011(m7, m6);
not #(0) U1046(hnl_9, run_b);
// same as old model timing
not #(6) U1050(mclk, m5);
not #(0) U1034(hnl_11, rckdrv);
not #(0) U1039(hnl_13, rckdrv);
not #(0) U1035(hnl_14, runclk_b);
not #(0) U1040(hnl_10, hnl_16);
not #(0) U1037(hnl_16, testCkL_b);
not #(0) U1043(hnl_15, pwrDn);
not #(1) U1008(hnl_12, en_b);
endmodule

module u5RDLL (mclk, rclk_b, rxclkL, Vbiasn, bypass_b, pwrDn, runclk_b, rxclk, testCkL_b, turboDLL_b, vref);
output mclk, rclk_b, rxclkL;
input Vbiasn, bypass_b, pwrDn, runclk_b, rxclk, testCkL_b, turboDLL_b, vref;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

u5CkBufR CkBufR(mclk, rclk_b, bypass_b, pwrDn, rxclk, runclk_b, testCkL_b);
u5ClkAmp RClkAmp(hnl_40, hnl_41, 1'b0, vref, pwrDn, 1'b0, rxclk, Vbiasn);
not #(0) U64(rxclkL, hnl_42);
not #(0) U63(hnl_42, hnl_43);
not #(0) U62(hnl_43, hnl_41);
not #(1) U65(rtp1, hnl_40);
not #(1) U47(turbo, turboDLL_b);
endmodule

module u5CkBufT (mtclk, tclk_b, tclkfb_b, bypass_b, pwrDn, runtclk, tckdrv, testCkL_b);
output mtclk, tclk_b, tclkfb_b;
input bypass_b, pwrDn, runtclk, tckdrv, testCkL_b;
supply1 vdd;
supply0 gnd;
nand #(1) U1145(hnl_44, gnd, vdd);
nand #(1) U1143(hnl_45, vdd, vdd);
nand #(1) U1139(run_b, bypass_b, runtclk);
nand #(1) U1055(en_b, hnl_46, bypass_b);
not #(0) U1022(m2, m1);
not #(0) U1147(hnl_47, en_b);
not #(0) U1115(hnl_48, hnl_49);
not #(0) U1146(t6, m3);
not #(1) U1134(tclk_b, m9);
not #(1) U1133(m9, m8);
not #(1) U1091(m8, m7);
not #(1) U1049(m7, m6);
// delay to match old model
not #(5) U1136(mtclk, m5);
not #(0) U1135(m5, m4);
not #(0) U1088(m4, m3);
not #(0) U1079(t5, m2);
not #(0) U1031(hnl_50, tckdrv);
not #(0) U1127(tclkfb_b, hnl_51);
not #(0) U1126(hnl_52, hnl_53);
not #(0) U1122(hnl_53, mtclk);
not #(0) U1123(hnl_54, mtclk);
not #(0) U1129(hnl_55, hnl_56);
not #(0) U1121(hnl_56, hnl_54);
not #(0) U1014(hnl_57, tckdrv);
not #(0) U1140(hnl_46, pwrDn);
not #(0) U1137(hnl_58, run_b);
not #(0) U1007(m3, m2);
not #(0) U1167(AR123, testCkL_b);
not #(0) U1118(hnl_49, AR123);
cxfr U1124(hnl_51, hnl_52, hnl_55, hnl_44);
cxfr U1125(hnl_51, hnl_55, hnl_52, hnl_45);
cxfr U1105(m6, run_b, hnl_58, hnl_48);
cxfr U1071(m6, hnl_58, run_b, hnl_57);
cxfr U1062(m1, en_b, hnl_47, hnl_48);
cxfr U1039(m1, hnl_47, en_b, hnl_50);
endmodule

module u5TDLL (mtclk, tclk_b, txclkL, Vbiasn, bypass_b, pwrDn, runtclk, testCkL_b, turboDLL_b, txclk, vref);
output mtclk, tclk_b, txclkL;
input Vbiasn, bypass_b, pwrDn, runtclk, testCkL_b, turboDLL_b, txclk, vref;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

not #(0) U69(txclkL, hnl_84);
not #(0) U68(hnl_84, hnl_85);
not #(1) U67(t1, hnl_82);
not #(0) U66(hnl_85, hnl_83);
not #(1) U47(turbo, turboDLL_b);
u5CkBufT U9(mtclk, tclk_b, clkfb, bypass_b, pwrDn, runtclk, ~txclk, testCkL_b);
u5ClkAmp TClkAmp(hnl_82, hnl_83, 1'b0, vref, pwrDn, 1'b0, txclk, Vbiasn);

endmodule

module u5DLL (rclk_b, mtclk, tclk_b, mclk, Vbiasn, rxclkL, txclkL, slow, runclk_b, runtclk, RxClk, TxClk, VRef, powerDownMode, turboDLL_b, DLLByPassMode_b);
output Vbiasn, mclk, mtclk, rclk_b, rxclkL, slow, tclk_b, txclkL;
input DLLByPassMode_b, RxClk, TxClk, VRef, powerDownMode, runclk_b, runtclk, turboDLL_b;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

u5TstClk TstClk(Vbiasn, slow, tstclk_b, DLLByPassMode_b, rxclkL, powerDownMode, RxClk);
u5RDLL RDLL(mclk, rclk_b, rxclkL, Vbiasn, DLLByPassMode_b, powerDownMode, runclk_b, RxClk, tstclk_b, turboDLL_b, VRef);
u5TDLL TDLL(mtclk, tclk_b, txclkL, Vbiasn, DLLByPassMode_b, powerDownMode, runtclk, tstclk_b, turboDLL_b, TxClk, VRef);
endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5InLat1/u5InLat1.v"
module u5InLat1 (Q_b, EN, D, ENB);
    output Q_b;
    input EN;
    input D;
    input ENB;

  latBarB I0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5InLat2/u5InLat2.v"
module u5InLat2 (toLat4, pd, EN, D_b, ENB);
    output toLat4;
    output pd;
    input EN;
    input D_b;
    input ENB;

  wire   D, Q_b;
  assign D      = ~D_b;
  assign toLat4 = ~Q_b;
  assign pd     = ~Q_b;
  latBarB I0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5InLat3/u5InLat3.v"
module u5InLat3 (dataIn, toLat4, EN, D, ENB);
    output dataIn;
    output toLat4;
    input EN;
    input D;
    input ENB;

  wire   Q_b;
  assign dataIn = ~Q_b;
  assign toLat4 = ~Q_b;
  latBarB I0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5InLat4/u5InLat4.v"
module u5InLat4 (WD, D, EN, ENB);
    output WD; 
    input D;
    input EN;
    input ENB;

  wire   Q;
  assign WD = Q;

  latB I0 (Q, D, EN);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5pd2Lat/u5pd2Lat.v"
module u5pd2Lat (pd, EN, D_b, ENB);
    output pd;
    input EN;
    input D_b;
    input ENB;

  wire   D, Q_b;
  assign D      = ~D_b;
  assign pd     = ~Q_b;
  latBarB latBarB0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5InClk/u5InClk.v"
module u5InClk (InClk, InClkB, rclk);
    output InClk;
    output InClkB;
    input rclk;

supply1 vdd;
supply0 gnd;
not I5(outd, outc);
not #(1) I6(InClk, outa);
not #(1) U1(InClkB, outd);
not #(1) U4(outc, rclk);
not #(1) U3(outa, rclk);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5OutClk/u5OutClk.v"
module u5OutClk (tclkl, tclklB, tclk);
    output tclkl;
    output tclklB;
    input tclk;

supply1 vdd;
supply0 gnd;
not #(1) I6(tclkl, outa);
not I5(outd, outc);
not #(1) U3(outa, tclk);
not #(1) U1(tclklB, outd);
not #(1) U4(outc, tclk);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5SioMux/u5SioMux.v"
primitive u5SioMux (Y_B, C, B, A, SelC, SelA, SelB);
    output Y_B; reg Y_B;
    input C;
    input B;
    input A;
    input SelC;
    input SelA;
    input SelB;

table
//      C B A   SelC SelA SelB : state : Y_B/next state
        1 ? ?   1    0    0    :   ?   :   0 ;
        0 ? ?   1    0    0    :   ?   :   1 ;
        ? 1 ?   0    0    1    :   ?   :   0 ;
        ? 0 ?   0    0    1    :   ?   :   1 ;
        ? ? 1   0    1    0    :   ?   :   0 ;
        ? ? 0   0    1    0    :   ?   :   1 ;
        ? ? ?   0    0    0    :   ?   :   - ; //no change
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5SoDrv/u5SoDrv.v"
// a simple model of u5SoDrv. The charge pump oscillator is ignored.
module u5SoDrv (oscen, pad, InB, osc, PDenable);
    output oscen; reg oscen;
    output pad;
    input InB;
    input osc;
    input PDenable;

	supply1 vdd;
	supply0 gnd;

//	pullup (strong1)(oscen);

	nor #(1) U61(n5, n1, n3);
	nor #(1) U60(n4, n1, InB);
	tranif1 N59(pad, gnd, n5);
	tranif1 N58(vdd, pad, n4);
	not #(1) U79(n3, InB);
	not #(1) U62(n1, PDenable);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5OscMJ/u5OscMJ.v"
module u5OscMJ (osc, oscen);
    output osc; reg osc;
    input oscen;

	initial
	begin
	    osc = 1;
	end

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5OIRcvr/u5OIRcvr.v"
module u5OIRcvr (QB, Q, pwrdn, DB, CLK, D);
    output QB;
    output Q;
    input pwrdn;
    input DB;
    input CLK;
    input D;

	not #(0) I1300(CLK_b, CLK);
        ffSB #(1) I1301(QB, CLK_b, DB, pwrdn);
        not #(0) I1302(Q, QB);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5EIRcvr/u5EIRcvr.v"
module u5EIRcvr (Q, QB, pwrdn, D, DB, CLK);
    output Q;
    output QB;
    input pwrdn;
    input D;
    input DB;
    input CLK;

        ffSB #(1) I1200(QB, CLK, DB, pwrdn);
        not #(0) I1201(Q, QB);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5BEsnif/u5BEsnif.v"
module u5BEsnif (Out_b, VRef, In_b);
    output Out_b; reg Out_b;
    input VRef;
    input In_b;

always @ (In_b) begin
        Out_b = In_b;
    end

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5TstIn/u5TstIn.v"
module u5TstIn (SuperBE_b, BusEnable, powerDownMode);
    output SuperBE_b;
    input BusEnable;
    input powerDownMode;

    reg SuperBE_b;

initial begin
        SuperBE_b = 1;
        end

endmodule

// HDL file - 
// /home/earth/usr2/u5/rev1.0/cad/schema/P4res/P4res.v"
module P4res (PLUS, MINUS);
    inout PLUS;
    inout MINUS;

    tran (PLUS, MINUS);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5MemC/u5MemC.v"
// u5MemC.v - behavioural model for the U5 core
//
// Copyright 1992, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
// 
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
// 
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

// Revision 1.21  1993/11/04  18:51:52  harlan
//

`ifdef NICE_PIN_ORDER
module u5MemC(
              WDL8,			 // write data
              WDL7,			 // write data
	      WDL6,			 // write data
	      WDL5,			 // write data
	      WDL4,			 // write data
	      WDL3,			 // write data
	      WDL2,			 // write data
	      WDL1,			 // write data
	      WDL0,			 // write data
              RDL8,			 // read data
              RDL7,			 // read data
	      RDL6,			 // read data
	      RDL5,			 // read data
	      RDL4,			 // read data
	      RDL3,			 // read data
	      RDL2,			 // read data
	      RDL1,			 // read data
	      RDL0,			 // read data
      	      WE,			 // write enable
    	      CAS,			 // column address strobe
    	      WRITE,			 // write, controls direction of RWD
    	      BSEL,			 // bank select
    	      REQ,			 // request, powers on CAS circuitry
    	      ADR,			 // row/column address
    	      RASB,			 // row address strobe, asserted low
    	      RSTR,			 // restore
    	      PON,			 // power on
    	      VREG,			 // voltage regulator reference
    	      WML,			 // write mask load
    	      WPBT,			 // write-per-bit
    	      MPBT,			 // mask-per-bit
    	      PDMD,			 // power down mode
    	      VCMNA,			 // test func: for VDD minimum test
	      VRST,			 // test func: Vinternal = Vexternal
	      ROLLC,			 // test func: roll call mode
	      SDST,			 // test func: subdetect stop
	      RCRED,			 // test func: roll call redundancy
	      HVST,			 // test func: half Vcc generator
	      BIMDI,			 // test func: burn in mode
	      AGEING,			 // test func: accelerate ageing pin
	      AGEGND);			 // test func: accelerate ageing pin
  
`else
module u5MemC( PON, VREG, RCRED, RDL0, RDL1, RDL2, RDL7, RDL4, RDL3, RDL5, RDL8, RDL6, 
BIMDI, WE, WML, REQ, WRITE, CAS, BSEL, ADR, RSTR, RASB, MPBT, WPBT, PDMD, HVST, AGEGND, 
AGEING, VRST, SDST, ROLLC, VCMNA, WDL3, WDL8, WDL5, WDL1, WDL6, WDL2, WDL4, WDL7, WDL0);
`endif
  
inout         WDL8;			 // write data
inout         WDL7;			 // write data
inout	      WDL6;			 // write data
inout	      WDL5;			 // write data
inout	      WDL4;			 // write data
inout	      WDL3;			 // write data
inout	      WDL2;			 // write data
inout	      WDL1;			 // write data
inout	      WDL0;			 // write data
inout         RDL8;			 // read data
inout         RDL7;			 // read data
inout	      RDL6;			 // read data
inout	      RDL5;			 // read data
inout	      RDL4;			 // read data
inout	      RDL3;			 // read data
inout	      RDL2;			 // read data
inout	      RDL1;			 // read data
inout	      RDL0;			 // read data
inout         WE;			 // write enable
inout         CAS;			 // column address strobe
inout         WRITE;			 // write, controls direction of RWD
inout         BSEL;			 // bank select
inout         REQ;			 // request, powers on CAS circuitry
inout         ADR;			 // row/column address
inout         RASB;			 // row address strobe, asserted low
inout         RSTR;			 // restore
inout         PON;			 // power on
inout         VREG;			 // voltage regulator reference
inout         WML;			 // write mask load
inout         WPBT;			 // write-per-bit
inout         MPBT;			 // mask-per-bit
inout         PDMD;			 // power down mode
inout         VCMNA;			 // test func: for VDD minimum test
inout         VRST;			 // test func: Vinternal = Vexternal
inout         ROLLC;			 // test func: roll call mode
inout         SDST;			 // test func: subdetect stop
inout         RCRED;			 // test func: roll call redundancy
inout         HVST;			 // test func: half Vcc generator
inout         BIMDI;			 // test func: burn in mode
inout         AGEING;			 // test func: accelerate ageing pin
inout         AGEGND;			 // test func: accelerate ageing pin

wire [7:0]    WDL8;			 // write data
wire [7:0]    WDL7;			 // write data
wire [7:0]    WDL6;			 // write data
wire [7:0]    WDL5;			 // write data
wire [7:0]    WDL4;			 // write data
wire [7:0]    WDL3;			 // write data
wire [7:0]    WDL2;			 // write data
wire [7:0]    WDL1;			 // write data
wire [7:0]    WDL0;			 // write data
wire [7:0]    RDL8;			 // read data
wire [7:0]    RDL7;			 // read data
wire [7:0]    RDL6;			 // read data
wire [7:0]    RDL5;			 // read data
wire [7:0]    RDL4;			 // read data
wire [7:0]    RDL3;			 // read data
wire [7:0]    RDL2;			 // read data
wire [7:0]    RDL1;			 // read data
wire [7:0]    RDL0;			 // read data
wire [7:0]    WE;			 // write enable
wire          CAS;			 // column address strobe
wire          WRITE;			 // write, controls direction of RWD
wire          BSEL;			 // bank select
wire          REQ;			 // request, powers on CAS circuitry
wire [8:0]    ADR;			 // row/column address
wire          RASB;			 // row address strobe, asserted low
wire          RSTR;			 // restore
wire          PON;			 // power on
wire          VREG;			 // voltage regulator reference
wire          WML;			 // write mask load
wire          WPBT;			 // write-per-bit
wire          MPBT;			 // mask-per-bit
wire          PDMD;			 // power down mode
wire          VCMNA;			 // test func: for VDD minimum test
wire          VRST;			 // test func: Vinternal = Vexternal
wire          ROLLC;			 // test func: roll call mode
wire          SDST;			 // test func: subdetect stop
wire          RCRED;			 // test func: roll call redundancy
wire          HVST;			 // test func: half Vcc generator
wire          BIMDI;			 // test func: burn in mode
wire          AGEING;			 // test func: accelerate ageing pin
wire          AGEGND;			 // test func: accelerate ageing pin

// declarations for semaphores used by timing checks
reg noisy_sense_if_defined;

// size parameters
parameter byte = 9;			 // number of bits per byte
parameter oct = 8;			 // column access done in groups of 8
parameter col_addr_bits = 8;		 // number of column address bits
parameter num_columns = 1<<col_addr_bits; // number of columns
parameter row_addr_bits = 9;		 // number of row address bits
parameter num_rows = 1<<row_addr_bits;	 // number of rows
parameter block_addr_bits = 1;		 // number of block address bits
parameter num_blocks = 1<<block_addr_bits; // number of banks

// short form to read all the WDL lines
wire [((oct*byte)-1):0] WDL = {WDL8, WDL7, WDL6, WDL5, WDL4,
			       WDL3, WDL2, WDL1, WDL0};

// timing parameters *** NB, must correspond to specify block ***
parameter ns = 10;			 // verilog ticks per nanosecond
parameter us = 10000;			 // verilog ticks per microsecond
parameter ctl_min_delta = -3;		 // time spec adjustment, verilog ticks
parameter ctl_max_delta = +3;		 // time spec adjustment, verilog ticks
parameter out_min_delta = +3;		 // time spec adjustment, verilog ticks
parameter out_max_delta = -3;		 // time spec adjustment, verilog ticks

// timing parameters for specify block
specify
  specparam ns_sp = 10;
  specparam us_sp = 10000;
  specparam ctl_min_delta_sp = -3;
  specparam ctl_max_delta_sp = +3;
  specparam out_min_delta_sp = +3;
  specparam out_max_delta_sp = -3;
endspecify

// timing parameters - column *** NB, must correspond to specify block ***
					 // not interface spec, but operative
parameter tASC =  ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tASC_sp =  (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tBH =   ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tBH_sp =   (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

					 // not interface spec, but operative
parameter tBS =   ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tBS_sp =   (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCAH =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tCAH_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCAS =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tCAS_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tCMD =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tCMD_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCMS =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tCMS_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCP =   ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tCP_sp =   (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tCSA =   ((ctl_max_delta + 2*ns) > 0) ? ctl_max_delta + 2*ns : 0;
specify
  specparam tCSA_sp =  (((ctl_max_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_max_delta_sp + 2*ns_sp : 0);
endspecify

parameter tDAC =  ((out_max_delta + 12*ns) > 0) ? out_max_delta + 12*ns : 0;
specify
  specparam tDAC_sp =  (((out_max_delta_sp + 12*ns_sp) > 0) ?
      	      	      	  out_max_delta_sp + 12*ns_sp : 0);
endspecify

parameter tDH =   ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tDH_sp =   (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tDOH =  ((out_min_delta + 4*ns) > 0) ? out_min_delta + 4*ns : 0;
specify
  specparam tDOH_sp =  (((out_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  out_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tDOHW = ((out_min_delta + 0*ns) > 0) ? out_min_delta + 0*ns : 0;
specify
  specparam tDOHW_sp = (((out_min_delta_sp + 0*ns_sp) > 0) ?
      	      	      	  out_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tDS =   ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tDS_sp =   (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tMDH =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tMDH_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tMDS =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tMDS_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tMPH =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tMPH_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tMPS =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tMPS_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tPC =   ((ctl_min_delta + 16*ns) > 0) ? ctl_min_delta + 16*ns : 0;
specify
  specparam tPC_sp =   (((ctl_min_delta_sp + 16*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 16*ns_sp : 0);
endspecify

parameter tRCD =  ((ctl_min_delta + 48*ns) > 0) ? ctl_min_delta + 48*ns : 0;
specify
  specparam tRCD_sp =  (((ctl_min_delta_sp + 48*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 48*ns_sp : 0);
endspecify

parameter tRQH =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tRQH_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

`ifdef RQL8
  parameter tRQL =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
  specify
    specparam tRQL_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
			    ctl_min_delta_sp + 8*ns_sp : 0);
  endspecify
`else
  `define RQL4
  `ifdef RQL4
    parameter tRQL =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
    specify
      specparam tRQL_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
			      ctl_min_delta_sp + 4*ns_sp : 0);
    endspecify
  `else
    initial
      begin
        $display("%m ERROR: Must define \"RQL4\" or \"RQL8\" for tRQLmin");
	while (1) $stop;
      end
    parameter tRQL = 1000;
    specify
      specparam  tRQL_sp = 1000;
    endspecify
  `endif
`endif

parameter tRQS =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRQS_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRSA =   ((ctl_max_delta + 2*ns) > 0) ? ctl_max_delta + 2*ns : 0;
specify
  specparam tRSA_sp =  (((ctl_max_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_max_delta_sp + 2*ns_sp : 0);
endspecify

parameter tRSB =   ((ctl_max_delta + 2*ns) > 0) ? ctl_max_delta + 2*ns : 0;
specify
  specparam tRSB_sp =  (((ctl_max_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_max_delta_sp + 2*ns_sp : 0);
endspecify

parameter tWEH =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tWEH_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tWES =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tWES_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tWH =   ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tWH_sp =   (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tWML =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tWML_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tWPH =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tWPH_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tWPS =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tWPS_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tWS =   ((ctl_min_delta + 10*ns) > 0) ? ctl_min_delta + 10*ns : 0;
specify
  specparam tWS_sp =   (((ctl_min_delta_sp + 10*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 10*ns_sp : 0);

endspecify

// column timing checks
specify
  $setup(ADR, posedge CAS, tASC_sp);
  $hold(negedge CAS, BSEL, tBH_sp); 
  $setup(BSEL, posedge CAS, tBS_sp);
  $hold(posedge CAS, ADR, tCAH_sp);
  $width(posedge CAS, tCAS_sp);
  $hold(negedge CAS, WML, tCMD_sp);
  $setup(WML, posedge CAS, tCMS_sp);
  $width(negedge CAS, tCP_sp);
  // no check required for response spec tDAC
  $hold(negedge CAS &&& (WRITE == 1), WDL, tDH_sp);
  // no check required for response spec tDOH
  // no check required for response spec tDOHW
  $setup(WDL, posedge CAS &&& (WRITE == 1), tDS_sp);
  $hold(negedge WML, WDL, tMDH_sp);
  $setup(WDL, posedge WML, tMDS_sp);
  $hold(negedge CAS, MPBT, tMPH_sp);
  $setup(MPBT, posedge CAS, tMPS_sp);
  $period(posedge CAS, tPC_sp);
  $setup(RASB, posedge CAS, tRCD_sp);
  $hold(negedge CAS, REQ, tRQH_sp);
  $width(negedge REQ, tRQL_sp);
  $setup(REQ, negedge CAS, tRQS_sp);
  $hold(posedge CAS &&& WRITE, WE, tWEH_sp);
  $setup(WE, posedge CAS &&& WRITE, tWES_sp);
  $hold(negedge CAS, WRITE, tWH_sp);
  $width(posedge WML, tWML_sp);
  $hold(negedge CAS, WPBT, tWPH_sp);
  $setup(WPBT, posedge CAS, tWPS_sp);
  $setup(WRITE, posedge CAS, tWS_sp);
endspecify

// timing parameters - row
parameter tASR1 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tASR1_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tASR2 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tASR2_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tBSR1 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tBSR1_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tBSR2 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tBSR2_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tCFR =  ((ctl_min_delta + 24*ns) > 0) ? ctl_min_delta + 24*ns : 0;
specify
  specparam tCFR_sp =  (((ctl_min_delta_sp + 24*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 24*ns_sp : 0);
endspecify

parameter tPDH =  ((ctl_min_delta + 32*ns) > 0) ? ctl_min_delta + 32*ns : 0;
specify
  specparam tPDH_sp =  (((ctl_min_delta_sp + 32*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 32*ns_sp : 0);
endspecify

parameter tPDS =  ((ctl_min_delta + 64*ns) > 0) ? ctl_min_delta + 64*ns : 0;
specify
  specparam tPDS_sp =  (((ctl_min_delta_sp + 64*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 64*ns_sp : 0);
endspecify

parameter tPRAS = ((ctl_min_delta + 200*ns) > 0) ? ctl_min_delta + 200*ns : 0;
specify
  specparam tPRAS_sp = (((ctl_min_delta_sp + 200*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 200*ns_sp : 0);
endspecify

parameter tPRC =  ((ctl_min_delta + 400*ns) > 0) ? ctl_min_delta + 400*ns : 0;
specify
  specparam tPRC_sp =  (((ctl_min_delta_sp + 400*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 400*ns_sp : 0);
endspecify

parameter tPRP =  ((ctl_min_delta + 200*ns) > 0) ? ctl_min_delta + 200*ns : 0;
specify
  specparam tPRP_sp =  (((ctl_min_delta_sp + 200*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 200*ns_sp : 0);
endspecify

parameter tPVD =  ((out_max_delta + 15*us) > 0) ? ctl_min_delta + 15*us : 0;
specify
  specparam tPVD_sp =  (((out_max_delta_sp + 15000*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 15000*ns_sp : 0);
endspecify

parameter tPVH =  ((out_max_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tPVH_sp =  (((out_max_delta_sp + 0*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tRAH1 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRAH1_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRAH2 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRAH2_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRAS =  ((ctl_min_delta + 112*ns) > 0) ? ctl_min_delta + 112*ns : 0;
specify
  specparam tRAS_sp =  (((ctl_min_delta_sp + 112*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 112*ns_sp : 0);
endspecify

parameter tRBH1 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRBH1_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRBH2 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRBH2_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRC =   ((ctl_min_delta + 140*ns) > 0) ? ctl_min_delta + 140*ns : 0;
specify
  specparam tRC_sp =   (((ctl_min_delta_sp + 140*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 140*ns_sp : 0);
endspecify

parameter tRP =   ((ctl_min_delta + 28*ns) > 0) ? ctl_min_delta + 28*ns : 0;
specify
  specparam tRP_sp =   (((ctl_min_delta_sp + 28*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 28*ns_sp : 0);
endspecify

parameter tRPR =  ((ctl_min_delta + 28*ns) > 0) ? ctl_min_delta + 28*ns : 0;
specify
  specparam tRPR_sp =  (((ctl_min_delta_sp + 28*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 28*ns_sp : 0);
endspecify

parameter tRRD =  ((ctl_min_delta + 106*ns) > 0) ? ctl_min_delta + 106*ns : 0;
specify
  specparam tRRD_sp =  (((ctl_min_delta_sp + 106*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 106*ns_sp : 0);
endspecify

parameter tRSH =  ((ctl_min_delta + 16*ns) > 0) ? ctl_min_delta + 16*ns : 0;
specify
  specparam tRSH_sp =  (((ctl_min_delta_sp + 16*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 16*ns_sp : 0);
endspecify

parameter tRSR =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRSR_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRTH =  ((ctl_min_delta + 26*ns) > 0) ? ctl_min_delta + 26*ns : 0;
specify
  specparam tRTH_sp =  (((ctl_min_delta_sp + 26*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 26*ns_sp : 0);
endspecify

parameter tRTL =  ((ctl_min_delta + 20*ns) > 0) ? ctl_min_delta + 20*ns : 0;
specify
  specparam tRTL_sp =  (((ctl_min_delta_sp + 20*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 20*ns_sp : 0);
endspecify

parameter tRTO =  ((ctl_min_delta + 26*ns) > 0) ? ctl_min_delta + 26*ns : 0;
specify
  specparam tRTO_sp =  (((ctl_min_delta_sp + 26*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 26*ns_sp : 0);
endspecify

parameter tRTR =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tRTR_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tRTS =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRTS_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tQHP =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tQHP_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tQSP =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tQSP_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 0*ns_sp : 0);
endspecify


// row timing checks
specify
  $setup(ADR, negedge RASB, tASR1_sp);
  $setup(ADR, posedge RSTR &&& (RASB == 0), tASR2_sp);
  $setup(BSEL, posedge RASB &&& (RSTR == 0), tBSR1_sp);
  $setup(BSEL, posedge RSTR &&& (RASB == 0), tBSR2_sp);
  $hold(negedge CAS &&& (RSTR == 0), posedge RSTR, tCFR_sp);
  $hold(posedge RASB, PDMD,  tPDH_sp, noisy_sense_if_defined);
  $setup(PDMD, negedge RASB, tPDS_sp, noisy_sense_if_defined);
  $width(negedge RASB &&& (PDMD == 1), tPRAS_sp);
  $period(posedge RASB &&& (PDMD == 1), tPRC_sp);
  $width(posedge RASB &&& (PDMD == 1), tPRP_sp);
  // no check required for response spec  tPVD
  // no check required for response spec  tPVH
  $hold(negedge RASB, ADR, tRAH1_sp);
  $hold(posedge RSTR &&& (RASB == 0), ADR, tRAH2_sp);
  $width(negedge RASB, tRAS_sp);
  $hold(posedge RASB &&& (RSTR == 0), BSEL, tRBH1_sp);
  $hold(posedge RSTR &&& (RASB == 0), BSEL, tRBH2_sp);
  $period(posedge RASB, tRC_sp);
  $width(posedge RASB, tRP_sp);
  $width(posedge RASB &&& (RSTR == 1), tRPR_sp);
  $hold(negedge RASB, RSTR, tRRD_sp);
  $hold(negedge CAS, RASB, tRSH_sp);
  $hold(posedge RASB, RSTR, tRSR_sp);
  $width(posedge RSTR, tRTH_sp);
  $width(negedge RSTR &&& (~RASB), tRTL_sp);
  $hold(posedge RSTR &&& (RASB == 0), RASB, tRTO_sp);
  $hold(negedge RSTR, RASB, tRTR_sp);
  $hold(posedge RSTR &&& (RASB == 1), RASB, tRTS_sp);
  $setup(REQ, posedge PDMD, tQHP_sp);
  $hold (negedge PDMD, REQ, tQSP_sp);
endspecify


// timing parameters - other
parameter tPON = ctl_min_delta + 80*ns;

//////////////////////////////////////////////////////////////////////////////

// memory array
reg [(oct*byte-1):0] core [0:((num_blocks*num_rows*num_columns)-1)];

// cache lines, formed by the sense amplifiers
reg [(oct*byte-1):0] cache [0:((num_blocks*(num_columns))-1)];

// latch for write-per-bit and mask-per-bit
wire [((oct*byte)-1):0] write_mask;

// logic 0
supply0 Gnd;

// logic 1
supply1 Vdd;

//////////////////////////////////////////////////////////////////////////////

// CAS read
wire [((oct*byte)-1):0] rdl_drive;	 // derivative signal
wire [((oct*byte)-1):0] sa_read;
wire [(col_addr_bits-1):0] cr_col_addr;
wire read_prech;
reg  cr_rdcy_control;
wire [(col_addr_bits):0] cr_rdcy_BSEL_ADR;
wire [(col_addr_bits):0] cr_rdcy_select;
wire [(col_addr_bits):0] cr_rdcy_latched;
wire cr_rdcy_prech;
wire cr_rdcy_prech0;
reg  cr1REQ;
reg  cr_latch_addr;
reg  crCAS;				 // signals with timing uncertainties
wire crWRITE;
wire crREQ;
wire crBSEL;
reg  cr_control;
wire cr_control0;
wire cr_control1;
wire [((oct*byte)-1):0] cr_cache;
wire read_prech0;
reg  [(col_addr_bits-1):0] crADR;
wire [(col_addr_bits-1):0] cr0ADR;

`ifdef DEBUGCORE
  always @rdl_drive
    begin
      $display("%0d %m: update RDL: crBSEL=%b, cr_col_addr=%b", 
               $stime, crBSEL, cr_col_addr);
      $display("  %b", rdl_drive);
    end
`endif
      
`ifdef INFOCORE
  always @(posedge cr_control)
    if (cr_control === 1)
      $display("%0d %m: CAS Read of block=%h address=%h", 
               $stime, crBSEL, cr_col_addr);
`endif

always @(posedge cr_control)
  if ({crBSEL, cr_col_addr} !== cr_rdcy_latched)
    $display("%0d %m: WARNING, Timing violation of tRSA, tRSB, or tCSA.", 
             $stime);

assign #tDOHW rdl_drive = 
      	     WRITE ? {oct*byte{1'bz}}
	           : {RDL8, RDL7, RDL6, RDL5, RDL4, RDL3, RDL2, RDL1, RDL0};

assign {RDL8, RDL7, RDL6, RDL5, RDL4, RDL3, RDL2, RDL1, RDL0} =
           cr_control ? crREQ ? ({crBSEL, cr_col_addr} === cr_rdcy_latched) ?
	                         cr_cache : {oct*byte{1'bx}}
                              : {oct*byte{1'bx}}
                      : rdl_drive;

					 // cas read control
always @(cr_control1 or cr_control0) cr_control = cr_control1 & cr_control0;
assign #0    cr_control1 = cr_control0;        // with uncertain high period
assign #tCAS cr_control1 = cr_control0;
assign cr_control0 = (crCAS & ~crWRITE & ((read_prech === 1) ? 1 : 'bx));

					 // cas read data
assign #0    cr_cache = cache[{crBSEL, cr_col_addr}];
assign #tCAS cr_cache = cache[{crBSEL, cr_col_addr}];

assign cr_col_addr = cr_latch_addr ? cr_col_addr : crADR; // address latch

assign cr_rdcy_latched = crCAS ? cr_rdcy_latched : cr_rdcy_select;

assign read_prech = crCAS ? read_prech	 // precharge equalizes diff amp
                          : read_prech0;
assign #0   read_prech0 = crWRITE | ~crCAS;
assign #tCP read_prech0 = crWRITE | ~crCAS;


  //effective end of cas read
  //parameter end_cr = max(tRQH, tWH, tBH);
parameter end_cr1 = (tWH  > tBH)     ? tWH  : tBH;
parameter end_cr  = (tRQH > end_cr1) ? tRQH : end_cr1;

always @CAS  crCAS <= #end_cr CAS;	 // align reference pulse

initial check_equal(end_cr - ctl_min_delta, tDAC - tCAS,
                    "max(tRQH, tWH, tBH)", "tDAC-tCAS");

assign #(end_cr - tRQH) crREQ = REQ;	 // early
assign #(end_cr + tRQS) crREQ = REQ;	 // late

assign #(end_cr - tWH)  crWRITE = WRITE; // early
assign #(end_cr + tWS)  crWRITE = WRITE; // late

assign #(end_cr - tBH)  crBSEL = BSEL;	 // early
assign #(end_cr + tBS)  crBSEL = BSEL;	 // late

always @cr0ADR  crADR <= #((end_cr > tCAH) ? end_cr - tCAH : 0) cr0ADR; // align
assign #0             cr0ADR = ADR;	           // early
assign #(tCAH + tASC) cr0ADR = ADR;	           // late

always @CAS cr_latch_addr <= #((tCAH > end_cr) ? tCAH : end_cr) CAS;

					 // redundancy control
always @(REQ or CAS)    cr_rdcy_control <= #(end_cr + tCSA) REQ & ~CAS;
assign #end_cr          cr_rdcy_BSEL_ADR = {BSEL, ADR[(col_addr_bits-1):0]};
assign cr_rdcy_select = cr_rdcy_control ? cr_rdcy_select : cr_rdcy_BSEL_ADR;
assign cr_rdcy_select = cr_rdcy_prech ? cr_rdcy_BSEL_ADR : 'bx;

assign cr_rdcy_prech = (cr1REQ & ~crCAS) ? cr_rdcy_prech : cr_rdcy_prech0;
assign #0    cr_rdcy_prech0 = ~cr1REQ | crCAS;
assign #tRQL cr_rdcy_prech0 = ~cr1REQ | crCAS;

always @REQ  cr1REQ <= #end_cr REQ;

initial check_ge(tCAS, tRQL, "tCAS", "tRQL");
initial check_equal(tCSA, tRSA, "tCSA", "tRSA");
initial check_equal(tCSA, tRSB, "tCSA", "tRSB");

// CAS write, including WPBT and MPBT
wire [((oct*byte)-1):0] sa_drive;	 // derivative signals
wire [((oct*byte)-1):0] sa_data;
wire [((oct*byte)-1):0] sa_enable;
wire [((oct*byte)-1):0] bit_enable;
wire [(oct-1):0] byte_enable;
wire [(col_addr_bits-1):0] cw_col_addr;
wire [((oct*byte)-1):0] wm_drive;
reg  cw_rdcy_control;
wire [(col_addr_bits):0] cw_rdcy_BSEL_ADR;
wire [(col_addr_bits):0] cw_rdcy_select;
wire [(col_addr_bits):0] cw_rdcy_latched;
wire [(col_addr_bits):0] cw_eff_addr;
wire cw_rdcy_prech;
wire cw_rdcy_prech0;
reg  cw1REQ;
reg  cwCAS;				 // signals with timing uncertainties
reg  cw_control;
wire cw_control0;
wire cw0CAS;
wire cwREQ;
wire cwWRITE;
wire [((oct*byte)-1):0] cwWDL;
wire cwBSEL;
wire cwWPBT;
wire cwMPBT;
reg  [(oct-1):0] cwWE;
wire [(oct-1):0]cw0WE;
reg  wmWML;
wire [((oct*byte)-1):0] wmWDL;
reg  [(col_addr_bits-1):0] cwADR;
wire [(col_addr_bits-1):0] cw0ADR;
reg [(col_addr_bits):0] i_col;	 // index for column addresses + 1 bit

					 // update addressed portion of cache
always @(sa_drive or cw_eff_addr or sa_enable or posedge cwCAS)
  if (|sa_enable & cwCAS)
    begin
      if (check_x_bits(cw_eff_addr))
      	begin
      	  for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	    cache[i_col] = {oct*byte{1'bx}};
	  $display("%0d %m: WARNING All cache <- X (workaround Verilog bug)",
	           $stime);
	end
      else
        cache[cw_eff_addr] = sa_drive;
      if ({cwBSEL, cw_col_addr} !== cw_rdcy_latched)
        $display("%0d %m: WARNING Timing violation of tRSA, tRSB, tCSA: Write",
                 $stime);
      `ifdef INFOCORE
      	if (cw_control === 1)
	  $display("%0d %m: CAS Write of block=%h address=%h, byte_enable=%h",
                   $stime, cwBSEL, cw_col_addr, byte_enable);
      `endif
      `ifdef DEBUGCORE
        $display("%0d %m: updated cache: cwBSEL=%b, cw_col_addr=%b", 
                 $stime, cwBSEL, cw_col_addr);
        $display("  %b", sa_drive);
      `endif
    end

					 // cas write control
always @(cw_control0 or cwCAS) cw_control = cw_control0 & cwCAS;
assign #0    cw_control0 = cwCAS;	 // with uncertain high period
assign #tCAS cw_control0 = cwCAS;

assign sa_drive = (cw_control & ((cwREQ === 1) ? 1 : 'bx))
                                ? (sa_enable & sa_data)
                                  | (~sa_enable & cache[cw_eff_addr])
				  | ((sa_data ~^ cache[cw_eff_addr])
				     & sa_data & cache[cw_eff_addr])
			        : cache[cw_eff_addr];

assign sa_data =   sa_enable & (cwMPBT ? write_mask : cwWDL);

assign sa_enable =   bit_enable & {byte{byte_enable}};

assign byte_enable = cwCAS ? {oct{cwWRITE}} & byte_enable
                           : {oct{cwWRITE}} & cwWE;

assign bit_enable = cwWPBT ? (cwMPBT ? cwWDL 
				     : write_mask)
                           : {oct*byte{1'b1}};
			   
assign cw_eff_addr = ({cwBSEL, cw_col_addr} === cw_rdcy_latched)
                     ? {cwBSEL, cw_col_addr}
		     : 'bx;

assign cw_col_addr = cwCAS ? cw_col_addr : cwADR;

assign cw_rdcy_latched = cwCAS ? cw_rdcy_latched : cw_rdcy_select;

  //effective end of cas write
  //parameter end_cw = max(tRQH, tWH, tDH, tBH, tWPH, tMPH, tCMD, tWEH, tCAH);
parameter end_cw7 = (tWEH > tCAH)    ? tWEH : tCAH;
parameter end_cw6 = (tCMD > end_cw7) ? tCMD : end_cw7;
parameter end_cw5 = (tMPH > end_cw6) ? tMPH : end_cw6;
parameter end_cw4 = (tWPH > end_cw5) ? tWPH : end_cw5;
parameter end_cw3 = (tBH  > end_cw4) ? tBH  : end_cw4;
parameter end_cw2 = (tDH  > end_cw3) ? tDH  : end_cw3;
parameter end_cw1 = (tWH  > end_cw2) ? tWH  : end_cw2;
parameter end_cw  = (tRQH > end_cw1) ? tRQH : end_cw1;

always @CAS  cwCAS <= #end_cw CAS;	 // align reference pulse

assign #(end_cw - tRQH) cwREQ = REQ;	 // early
assign #(end_cw + tRQS) cwREQ = REQ;	 // late

assign #(end_cw - tWH)  cwWRITE = WRITE; // early
assign #(end_cw + tWS)  cwWRITE = WRITE; // late

assign #(end_cw - tDH)  cwWDL = WDL;	 // early
assign #(end_cw + tDS)  cwWDL = WDL;	 // late

assign #(end_cw - tBH)  cwBSEL = BSEL;	 // early
assign #(end_cw + tBS)  cwBSEL = BSEL;	 // late

assign #(end_cw - tWPH) cwWPBT = WPBT;	 // early
assign #(end_cw + tWPS) cwWPBT = WPBT;	 // late

assign #(end_cw - tMPH) cwMPBT = MPBT;	 // early
assign #(end_cw + tMPS) cwMPBT = MPBT;	 // late

always @cw0WE   cwWE <= #(end_cw - tWEH) cw0WE;	 // align
assign #0             cw0WE = WE;		 // early
assign #(tWEH + tWES) cw0WE = WE;		 // late

always @cw0ADR  cwADR <= #(end_cw - tCAH) cw0ADR;// align
assign #0             cw0ADR = ADR;	         // early
assign #(tCAH + tASC) cw0ADR = ADR;              // late

					 // redundancy control
always @(REQ or CAS)    cw_rdcy_control <= #(end_cw + tCSA) REQ & ~CAS;
assign #end_cw          cw_rdcy_BSEL_ADR = {BSEL, ADR[(col_addr_bits-1):0]};
assign cw_rdcy_select = cw_rdcy_control ? cw_rdcy_select : cw_rdcy_BSEL_ADR;
assign cw_rdcy_select = cw_rdcy_prech ? cw_rdcy_BSEL_ADR : 'bx;

assign cw_rdcy_prech = (cw1REQ & ~cwCAS) ? cw_rdcy_prech : cw_rdcy_prech0;
assign #0    cw_rdcy_prech0 = ~cw1REQ | cwCAS;
assign #tRQL cw_rdcy_prech0 = ~cw1REQ | cwCAS;

always @REQ  cw1REQ <= #end_cw REQ;


// latching the write mask

assign #0    write_mask = wm_drive;	 // mark time to properly latch
assign #tWML write_mask = wm_drive;

assign wm_drive = wmWML ? wmWDL : write_mask;	// latch action

  //effective end of write mask
  //parameter end_wm = max(tCMS, tMDH, 0, 0, 0, 0, 0, 0, 0);
parameter end_wm = (tCMS > tMDH) ? tCMS : tMDH;

always @WML  wmWML <= #end_wm WML;	 // align reference pulse

assign #(end_wm - tMDH) wmWDL = WDL;	 // early
assign #(end_wm + tMDS) wmWDL = WDL;	 // late

initial check_equal(tWML, tCMS, "tWML", "tCMS");


//////////////////////////////////////////////////////////////////////////////

// row read
reg [(oct*byte-1):0] core_row_temp [0:(num_columns-1)]; // scratch reg for core
reg [(block_addr_bits):0] i_blk;	 // index for block addresses + 1 bit
wire ras_prech;				 // latch bit for row precharged
wire RSTR1;				 // internal RSTR, from pin unless PDMD
reg  rrRASB;				 // delayed reference pulses
reg  rrRSTR1;
reg  [(row_addr_bits-1):0] rr_row_addr;	 // address for row read
reg  rr_block;				 // block for row read
wire rr_control;			 // signals with timing uncertainty
wire rr_control0;
wire rr_control1;
wire rr_control2;
wire [(row_addr_bits-1):0] rrw_row_addr; // address for row read and write
wire rrw_block;				 // block for row read and write
wire [(row_addr_bits-1):0] rrwADR;	 // address timing uncertainty
wire rrwBSEL;				 // block timing uncertainty
reg  rrwRASB;				 // address/block ref signals
reg  rrwRSTR1;
wire rrw_ras_rstr;			 // derived signal for address/block
reg  [(row_addr_bits+1):0] debug_ras;	 // debug: flag, block and addr at read

// add this after debug_ras in u5MemC

wire [71:0] harlan;
// monitor bank 1 row 1b6 column 0 in core
assign harlan = core[{1'b1,9'b110110110,8'b0}];
wire [71:0] harlan2;
// monitors bank 1 column 0 in cacheline
assign harlan2 = cache[{1'b1,8'b0}];

always @(posedge rr_control)
  begin
    if (rr_control === 1'bx)
      begin
	for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	  begin
	    core_row_temp[i_col] = 
	             core[{rr_block, rr_row_addr, i_col[(col_addr_bits-1):0]}];
	    core[{rr_block, rr_row_addr, i_col[(col_addr_bits-1):0]}] = 
	             {oct*byte{1'bx}};
	    cache[{rr_block, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
	  end
	debug_ras = {1'bx, rr_block, rr_row_addr};
	`ifdef DEBUGCORE
	  $display("%0d %m:  start  read core block=%b, addr=%b",
		   $stime, rr_block, rr_row_addr);
	`endif
      end
    else
      begin
	if (noisy_sense_if_defined === 1'bx)
	  begin
	    for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	      cache[{rr_block, i_col[(col_addr_bits-1):0]}] <= 
	                                          #end_cr core_row_temp[i_col];
	    debug_ras <= #end_cr {1'b0, rr_block, rr_row_addr};
	    `ifdef DEBUGCORE
	      $display("%0d %m: finish read core block=%b, addr=%b",
		       $stime, rr_block, rr_row_addr);
	    `endif
            `ifdef INFOCORE
              $display("%0d %m: RAS Read of block=%h address=%h", 
		       $stime, rr_block, rr_row_addr);
            `endif
	  end
	else
	  begin
	    noisy_sense_if_defined = 'bx;
	    `ifdef DEBUGCORE
	      $display("%0d %m: finish read core block=%b, addr=%b: noise->X",
		       $stime, rr_block, rr_row_addr);
	    `endif
	  end
      end
  end

always @(posedge ras_prech)		 // precharging wipes the sense amps
  begin
    for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
      cache[{rr_block, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
    `ifdef DEBUGCORE
      $display("%0d %m:  precharge clearing cache, block=%b", 
               $stime, rr_block);
    `endif
  end


					 //effective end of row read
					 //parameter end_rr = max(tRAH1,tRBH1);
parameter end_rr  = (tRAH1 > tRBH1) ? tRAH1 : tRBH1;

					 // row read control
assign rr_control = rr_control2 & rr_control0;
assign #0    rr_control2 = rr_control0;  // with uncertain read period
assign #tRP  rr_control2 = rr_control0;
assign #(tRCD - end_rr - tRP) rr_control2 = rr_control1;
assign #tRP                   rr_control1 = rr_control0;
assign rr_control0 = (~rrRASB & ((ras_prech === 1) ? 1 : 'bx));

always @RASB rrRASB <= #end_rr RASB;	 // align reference pulses
always @RSTR1 rrRSTR1 <= #end_rr RSTR1;

always @rrw_row_addr rr_row_addr <= #(end_rr - tRAH1) rrw_row_addr; // rd addr

always @rrw_block    rr_block    <= #(end_rr - tRAH1) rrw_block; // read block

initial check_ge(end_rr, tRAH1, "end_rr", "tRAH1");

// row precharge
wire prechRASB;				 // signals with timing uncertainty
wire sa_isolate;

assign ras_prech = (rrRSTR1 & ~rrRASB)
                              ? ras_prech : prechRASB; // precharge sense amps
assign #0            prechRASB = rrRASB;	       // early effect
assign #tRP          prechRASB = sa_isolate & rrRASB;  // late effect
assign #(tRPR - tRP) sa_isolate = ~(rrRSTR1 & ~rrRASB); // add'l delay factor


// row restore
wire rw_rstr;				 // derivative restore signal
wire rstr_prech;			 // latch bit for restore recovery
reg  rwRSTR1;				 // delayed reference pulse
reg  [(row_addr_bits-1):0] rw_row_addr;	 // address for row read
reg  rw_block;				 // block for row read
wire rw_control;			 // signals with timing uncertainty
wire rw_control0;
wire rw_control1;
wire rw_control2;
reg  rwRASB;
wire rw0RASB;
reg  extendRASB;
reg  [(row_addr_bits+1):0] debug_rstr;	 // debug: flag, block and addr: write
integer i_core;				 // index for wiping out the core

always @(posedge rw_control)
  begin
    if (rw_control === 1'bx)
      begin
	for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	  core[{rw_block, rw_row_addr, i_col[(col_addr_bits-1):0]}] = 
	                                                      {oct*byte{1'bx}};
	debug_rstr = {1'bx, rw_block, rw_row_addr};
      	if (check_x_bits({rw_block, rw_row_addr}))
      	  begin
	    for (i_core = 0; i_core < (num_blocks*num_rows*num_columns);
	         i_core = i_core + 1)
	      core[i_core] = 72'bx; //{oct*byte{1'bx}};
	    $display("%0d %m: WARNING All core <- X (workaround Verilog bug)",
	             $stime);
	  end
	`ifdef DEBUGCORE
	  $display("%0d %m: start  write core block=%b, addr=%b",
		   $stime, rw_block, rw_row_addr);
	`endif
      end
    else
      begin
      	if (check_x_bits({rw_block, rw_row_addr}))
	  $display("%0d %m: WARNING Core left as X (workaround Verilog bug)",
	            $stime);
	else
	  begin
  	    for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	      core[{rw_block, rw_row_addr, i_col[(col_addr_bits-1):0]}] = 
	                         cache[{rw_block, i_col[(col_addr_bits-1):0]}];
	    debug_rstr = {1'b0, rw_block, rw_row_addr};
	  end
	`ifdef DEBUGCORE
	  $display("%0d %m: finish write core block=%b, addr=%b",
		   $stime, rw_block, rw_row_addr);
	`endif
        `ifdef INFOCORE
          $display("%0d %m: RAS Write of block=%h address=%h", 
		   $stime, rw_block, rw_row_addr);
        `endif
      end
  end
      
					 // row write control
assign rw_control = rw_control2 & rw_control0;
assign #0    rw_control2 = rw_control0;  // with uncertain write period
assign #tRTL rw_control2 = rw_control0;
assign #(tRTO - tRTL) rw_control2 = rw_control1;
assign #tRTL          rw_control1 = rw_control0;
assign rw_control0 = (rw_rstr & ((rstr_prech === 1) ? 1 : 'bx));

					 //effective end of row write
					 //parameter end_rw = max(tRAH2,tRBH2);
parameter end_rw  = (tRAH2 > tRBH2) ? tRAH2 : tRBH2;
//parameter end_rw = tRTO;		 // effective end of row write

always @RSTR1 rwRSTR1 <= #end_rw RSTR1;	 // align reference pulse

always @rw0RASB rwRASB <= #end_rw rw0RASB;
assign #0       rw0RASB = RASB;
assign #tRSR    rw0RASB = RASB;

assign rw_rstr = rwRSTR1 & ~extendRASB;	 // combinational logic for restore

always @(posedge RASB) extendRASB <= #end_rw RASB;
always @(negedge RASB) extendRASB <= #(end_rw + tRRD - tRTO) RASB;

initial check_equal(tRTO, tRTH, "tRTO", "tRTH");

always @rrw_row_addr rw_row_addr <= #(end_rw - tRAH1) rrw_row_addr; // rd addr

always @rrw_block    rw_block    <= #(end_rw - tRAH1) rrw_block; // read block

initial check_ge(end_rw, tRAH1, "end_rw", "tRAH1");

// restore recovery
wire rstr_prech0;			 // signals with timing uncertainty
wire rstr_prech1;

assign rstr_prech = rstr_prech0 ? rstr_prech1 : rstr_prech;

assign #0    rstr_prech1 = rstr_prech0; // early effect
assign #tRTL rstr_prech1 = rstr_prech0; // late effect
assign rstr_prech0 = ~rwRSTR1 | extendRASB;


// row read and write address and block
assign rrw_row_addr = (rrwRSTR1 & ~rrwRASB)
                               ? rrw_row_addr : rrwADR; // row read addr latch

assign rrw_block    = (rrwRASB | rrwRSTR1 | rrw_ras_rstr) 
                               ? rrw_block : rrwBSEL; // row read block

always @RASB rrwRASB <= #tRAH1 RASB;	 // align reference signals
always @RSTR1 rrwRSTR1 <= #tRAH1 RSTR1;

assign #0               rrwADR = ADR;	 // early
assign #(tASR1 + tRAH1) rrwADR = ADR;	 // late

assign #0               rrwBSEL = BSEL;	 // early
assign #(tBSR1 + tRBH1) rrwBSEL = BSEL;	 // late

assign #(tRTR - tBSR1) rrw_ras_rstr = ~rrwRASB & rrwRSTR1; // delayed ctl pair

initial check_equal(tRAH1, tRAH2, "tRAH1", "tRAH2");
initial check_equal(tRAH1, tRBH1, "tRAH1", "tRBH1");
initial check_equal(tRAH1, tRBH2, "tRAH1", "tRBH2");
initial check_equal(tASR1, tASR2, "tASR1", "tASR2");
initial check_equal(tBSR1, tBSR2, "tBSR1", "tBSR2");


// power down mode
wire internal_rstr;			 // defines RSTR1 during PDMD
reg  stretchRASB;			 // time altered signals
reg  dly_stretchRASB;

					 // select external or internal restore
assign RSTR1 = PDMD ? internal_rstr : RSTR;

assign internal_rstr = stretchRASB | dly_stretchRASB;

always @(posedge RASB) stretchRASB <= #tRSR RASB;
always @(negedge RASB) stretchRASB <= #tRCD RASB;

always @(stretchRASB or PDMD) 
                       dly_stretchRASB <= #(tRRD - tRCD) stretchRASB | ~PDMD;

always @(posedge PDMD)			 // entering PDMD affects all caches
  begin
    for (i_blk = 0; i_blk < num_blocks; i_blk = i_blk +1)
      for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
        cache[{i_blk, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
    `ifdef DEBUGCORE
      $display("%0d %m:  entering powerdown, clearing all caches", $stime);
    `endif
  end

always @(negedge (rw_control & PDMD))	 // caches precharge after PDMD restore
  #0 begin
       for (i_blk = 0; i_blk < num_blocks; i_blk = i_blk +1)
         for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
           cache[{i_blk, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
       `ifdef DEBUGCORE
         $display("%0d %m: end internal restore, clearing all caches", $stime);
       `endif
     end

// derivative parameter checks
initial check_ge(tCFR, end_cw, "tCFR", "internal:end_cw");
initial check_ge(tRSH, end_cw, "tRSH", "internal:end_cw");

//////////////////////////////////////////////////////////////////////////////

// power on
reg drvPON;
assign PON = drvPON;
initial
  fork
    #1        drvPON = Gnd;
    `ifdef XPONCORE
      #(tPON/2) drvPON = 1'bx;
    `endif
    #tPON     drvPON = Vdd;
  join

// voltage regulator reference
reg drvVREG;
assign VREG = drvVREG;
always @(posedge PON or negedge PDMD) drvVREG <= #tPVD PON & ~PDMD;
always @(negedge PON or posedge PDMD) drvVREG <= #tPVH 'bx;

// tie off test signals
assign BIMDI = Gnd;
assign RCRED = Gnd;


//////////////////////////////////////////////////////////////////////////////

// Functions

function [31:0] max;			 // returns maximum of parameter values
  input v0, v1, v2, v3, v4, v5, v6, v7, v8;
  integer v0, v1, v2, v3, v4, v5, v6, v7, v8;
  begin
    max = v0;
    if (v1 > max) max = v1;
    if (v2 > max) max = v2;
    if (v3 > max) max = v3;
    if (v4 > max) max = v4;
    if (v5 > max) max = v5;
    if (v6 > max) max = v6;
    if (v7 > max) max = v7;
    if (v8 > max) max = v8;
  end
endfunction


// Tasks

task check_equal;			 // checks for equal values, else stops
  input value1;
  input value2;
  input string1;
  input string2;
  integer value1;
  integer value2;
  reg [0:(32*8)-1] string1;
  reg [0:(132*8)-1] string2;
  begin
    if (value1 !== value2)
      begin
        $display("%0d %m ERROR: values not equal. %0s=%0d, %0s=%0d.",
                 $stime, string1, value1, string2, value2);
        #0 $stop;
      end
  end
endtask

task check_ge;			 // checks for ge values, else stops
  input value1;
  input value2;
  input string1;
  input string2;
  integer value1;
  integer value2;
  reg [0:(32*8)-1] string1;
  reg [0:(32*8)-1] string2;
  begin
    if (!(value1 >= value2))
      begin
        $display("%0d %m ERROR: values not >=. %0s=%0d, %0s=%0d.",
                 $stime, string1, value1, string2, value2);
        #0 $stop;
      end
  end
endtask

// check_x_bits - checks for any x bits
function [0:0] check_x_bits;
  input value;
  reg [31:0] value;
  begin
   check_x_bits = ((| (value & ~value)) === 1'bx) ? 1 : 0;
  end
endfunction

// not yet handled
// . init RASes
// . bit rot
// . effect of tRSH


endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latSA/latSA.v"
primitive latSA (Q, D, EN, S);
output Q; reg Q;
input  D,EN,S;

table
//	D  EN   S  :state:	output/next state
        ?   0   0  : ? :        - ; // no change
        ?   0   1  : ? :        1 ; // set output
        1   1   1  : ? :        1 ; // set output
        0   1   1  : ? :        x ; // x if conflict

        0   1   0  : ? :        0 ; // latch data
        1   1   0  : ? :        1 ; // latch data
        x   1   0  : ? :        x ; // latch data

        0   x   0  : 0 :        0 ; // reducing pessimism
        1   x   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latNBarA/latNBarA.v"
primitive latNBarA (Q, D_B, EN_B);
output Q; reg Q;
input  D_B,EN_B;

table
//	D_B  EN_B :state:	output/next state
        ?     1   : ? : - ; // no change

        0     0   : ? : 1 ; // latch data
        1     0   : ? : 0 ; // latch data
        x     0   : ? : x ; // latch data

        0     x   : 1 : 1 ; // reducing pessimism
        1     x   : 0 : 0 ; // reducing pessimism
        ?     n   : ? : - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ltxBarSB/ltxBarSB.v"
module ltxBarSB (Q, EN, D_B, S);
output Q;
input  D_B,EN,S;

  latBarSB #(1) latBarSB0 (Q, D_B, EN, S);

endmodule


// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ltxSB/ltxSB.v"
primitive ltxSB (Q, D, EN, S);
output Q; reg Q;
input  D,EN,S;

table
//      D  EN   S  :state:      output/next state
        ?   0   0  : ? :        - ; // no change
        ?   0   1  : ? :        1 ; // set output
        1   1   1  : ? :        1 ; // set output
        0   1   1  : ? :        x ; // x if conflict

        0   1   0  : ? :        0 ; // latch data
        1   1   0  : ? :        1 ; // latch data
        x   1   0  : ? :        x ; // latch data

        0   x   0  : 0 :        0 ; // reducing pessimism
        1   x   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffSB/ffSB.v"
primitive ffSB (Q, CLK, D, S);
    output Q; reg Q;
    input CLK;
    input D;
    input S;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D  S  :state: output/nextState
        n       0  0  : ? :   0;
        n       1  ?  : ? :   1;
        // ignore positive edge of clock
        p       ?  ?  : ? :   -;
        // ignore data changes on steady clock
        ?       *  ?  : ? :   -;
        // set output to 1
        ?       ?  1  : ? :   1;
        ?       ?  *  : 1 :   -;
 
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffRC/ffRC.v"
primitive ffRC (Q, CLK, R_B, D);
    output Q; reg Q;
    input CLK;
    input R_B, D;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge R_B D   :state: output/nextState
        n       1   0   : ? :   0;
        n       1   1   : ? :   1;
        // ignore positive edge of clock
        p       ?   ?   : ? :   -;
        // ignore data changes on steady clock
        ?       1   *   : ? :   -;
        // set output to 1
        ?       0   ?   : ? :   0;
        ?       *   ?   : ? :   0;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBarD/ffBarD.v"
primitive ffBarD (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes
//      neg logic output

//      CLKedge D :state: output/nextState
        n       0 : ? :   1;
        n       1 : ? :   0;
        // ignore positive edge of clock
        p       ? : ? :   -;
        // ignore data changes on steady clock
        ?       * : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/DAff/DAff.v"
module DAff (Q_B, CLK, DAdata, D_B, DA_B);
    output Q_B;
    input CLK;
    input DAdata;
    input D_B;
    input DA_B;
    supply1 vdd;
    supply0 gnd;

    buf #(1) I1000(hnl_1000, DAdata);
    buf #(1) I1001(hnl_1001, D_B);
    buf #(1) I1002(hnl_1002, d_bs1);
    nand nandd(outd, outc, DA_B);
    nand nandb(lclk, outa, DA_B);
    not (weak0,weak1) #(1) U68(q_bs2, x);
    cxfr U76(q_bs2, hnl_222, DA_B, hnl_1000);
    cxfr U70(q_bs2, lclkb, lclk, hnl_1002);
    cxfr U64(ds1, lclk, lclkb, hnl_1001);
    not #(1) I77(hnl_222, DA_B);
    not #(1) I63(x, q_bs2);
    not #(1) I62(Q_B, q_bs2);
    not inc(outc, CLK);
    not ina(outa, CLK);
    not ine(lclkb, outd);
    not #(1) U65(d_bs1, ds1);
    not (weak0,weak1) #(1) I59(ds1, d_bs1);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latBarSB/latBarSB.v"
primitive latBarSB (Q, D_B, EN, S);
output Q; reg Q;
input  D_B,EN,S;

table
//	D_B  EN   S  :state:	output/next state
        ?     0   0  : ? :      - ; // no change
        ?     0   1  : ? :      1 ; // set output
        0     1   1  : ? :      1 ; // set output
        1     1   1  : ? :      x ; // conflict

        0     1   0  : ? :      1 ; // latch data
        1     1   0  : ? :      0 ; // latch data
        x     1   0  : ? :      x ; // latch data

        0     x   0  : 1 :      1 ; // reducing pessimism
        1     x   0  : 0 :      0 ; // reducing pessimism
        ?     p   ?  : ? :      - ;
        ?     0   ?  : 1 :      - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBNcD/ffBNcD.v"
primitive ffBNcD (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes
//      neg logic output

//      CLKedge D :state: output/nextState
        n       0 : ? :   1;
        n       1 : ? :   0;
        // ignore positive edge of clock
        p       ? : ? :   -;
        // ignore data changes on steady clock
        ?       * : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffD/ffD.v"
primitive ffD (Q, D, CLK);
    output Q; reg Q;
    input CLK;
    input D;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      D  CLKedge  :state: output/nextState
        0    n      : ? :   0;
        1    n      : ? :   1;
        // ignore positive edge of clock
        ?    p      : ? :   -;
        // ignore data changes on steady clock
        *    ?      : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/countupx/countupx.v"
module countupx (cout_b, q_b, cin_b, ldCount, ldData, reset_b, data_b, cnt, autoData_b);
    output cout_b;
    output q_b;
    input cin_b;
    input ldCount;
    input ldData;
    input reset_b;
    input data_b;
    input cnt;
    input autoData_b;

supply1 vdd;
supply0 gnd;
not (weak0,weak1) #(1) I174(n5, hnl_347);
not (weak0,weak1) #(1) I7(n3, n4);
buf #(1) I3232(n44, n4);
tranif0 I9(n5, vdd, reset_b);
nor #(1) I12(n7, cin_b, n8);
not #(1) I169(hnl_347, n5);
not #(1) I10(q_b, n5);
not #(1) I4(n2, n1);
cxfr I1(n9, n12, ldCount, q_b);
cxfr I17(n1, cin_b, n11, n6);
cxfr I16(n1, n11, cin_b, n8);
cxfr U176(n5, ldData, hnl_348, hnl_349);
cxfr U175(n3, hnl_350, cnt, n2);
cxfr I2(n9, ldCount, n12, autoData_b);
cxfr I8(n5, cnt, hnl_350, n44);
not #(1) I6(n4, n3);
not #(1) I20(hnl_350, cnt);
not #(1) U177(hnl_348, ldData);
not #(1) I3(n12, ldCount);
not #(1) I14(n6, n9);
not #(1) I15(n8, n6);
not #(1) I18(n11, cin_b);
not #(1) I13(cout_b, n7);
not #(1) U168(hnl_349, data_b);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latSB/latSB.v"
primitive latSB (Q, D, EN, S);
output Q; reg Q;
input  D,EN,S;

table
//	D  EN   S  :state:	output/next state
        ?   0   0  : ? :        - ; // no change
        ?   0   1  : ? :        1 ; // set output
        1   1   1  : ? :        1 ; // set output
        0   1   1  : ? :        x ; // x if conflict

        0   1   0  : ? :        0 ; // latch data
        1   1   0  : ? :        1 ; // latch data
        x   1   0  : ? :        x ; // latch data

        0   x   0  : 0 :        0 ; // reducing pessimism
        1   x   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/hitSel/hitSel.v"
primitive mux211 (Y_B, A, B, SEL, EN);
output Y_B; reg Y_B;
input A, B, SEL, EN;

table
//  A B SEL EN : state : Y_B/next_state
    0 ?  0  1  :  ?    : 1;     // select from A
    1 ?  0  1  :  ?    : 0;     // select from A
    ? 0  1  1  :  ?    : 1;     // select from B
    ? 1  1  1  :  ?    : 0;     // select from B
    0 0  ?  1  :  ?    : 1;     // reduce pessimism
    1 1  ?  1  :  ?    : 0;     // reduce pessimism
    ? ?  ?  0  :  ?    : -;     // no change
endtable

endprimitive

module hitSel (packetRASaddr_b, partialId_b, pd2, pd1, sel, writeA0123);
    output packetRASaddr_b;
    output partialId_b;
    input pd2;
    input pd1;
    input sel;
    input writeA0123;

  mux211 #(1) mux0 (partialId_b,     pd2, pd1, sel, writeA0123);
  mux211 #(1) mux1 (packetRASaddr_b, pd1, pd2, sel, writeA0123);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/mux21s/mux21s.v"
// Description of an mux21s
primitive mux21s(Y, A, B, SelB, SelB_B);
output Y;
input A, B, SelB, SelB_B;

table
//	A  B  SelB SelB_B: Y
	?  1  1    0     : 1;
	?  0  1    0     : 0;
	1  ?  0    1     : 1;
	0  ?  0    1     : 0;
	0  0  ?    ?     : 0;
	1  1  ?    ?     : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latRB/latRB.v"
primitive latRB (Q, D, EN, R_B);
output Q; reg Q;
input  D,EN,R_B;

table
//	D  EN  R_B :state:	output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        0   1   0  : ? :        0 ; // clear output
        1   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        0 ; // latch data
        1   1   1  : ? :        1 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 0 :        0 ; // reducing pessimism
        1   x   1  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/xnandpc2/xnandpc2.v"
module xnandpc2 (Y, A, PC, B);
    inout Y;
    input A;
    input PC;
    input B;

supply1 vdd;
supply0 gnd;
tranif0 P1(Y, vdd, PC);
not #(1) U15(A_b, A1);
not #(1) U12(B_b, B);
buf I1010(A1, A);
cxfr U11(xnorAB, B_b, B, A_b);
cxfr U10(xnorAB, B, B_b, A1);
tranif1 N4(hnl_336, gnd, xnorAB);
tranif1 N8(Y, hnl_336, PC);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latRA/latRA.v"
primitive latRA (Q, D, EN, R_B);
output Q; reg Q;
input  D,EN,R_B;

table
//	D  EN  R_B :state:	output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        0   1   0  : ? :        0 ; // clear output
        1   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        0 ; // latch data
        1   1   1  : ? :        1 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 0 :        0 ; // reducing pessimism
        1   x   1  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/countup/countup.v"
module countup (cout_b, q_b, cnt_b, cin_b, ldCount, data);
    output cout_b;
    output q_b;
    input cnt_b;
    input cin_b;
    input ldCount;
    input data;

	supply1 vdd;
	supply0 gnd;
	not (weak0,weak1) #(1) I5013(n5, hnl_96);
	nor #(1) I5007(n7, cin_b, q_b);
	not (weak0,weak1) #(1) I7(n3, n4);
	buf (buf_data, data);
	tranif1 I5005(buf_data, n5, ldCount);
	tranif1 I5000(n3, hnl_97, cnt_b);
	not #(1) I5004(q_b, n5);
	not #(1) I5067(hnl_96, n5);
	cxfr I5012(n2, cin_b, n8, n1);
	cxfr I5010(n2, n8, cin_b, n6);
	buf (buf_n4, n4);
	cxfr I5003(n5, n9, cnt_b, buf_n4);
	not #(1) I5011(n8, cin_b);
	not #(1) I5009(n6, n1);
	not #(1) I5008(cout_b, n7);
	not #(1) I5006(n1, q_b);
	not #(1) I5002(n4, n3);
	not #(1) I5001(n9, cnt_b);
	not #(1) U5066(hnl_97, n2);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/countdn/countdn.v"
module countdn (cout_b, q_b, cnt_b, cin_b, ldCount, data);
    output cout_b;
    output q_b;
    input cnt_b;
    input cin_b;
    input ldCount;
    input data;

	supply1 vdd;
	supply0 gnd;
	not (weak0,weak1) #(1) I7000(n3, n4);
	not (weak0,weak1) #(1) I7001(n5, hnl_96);
	buf I7002(buf_data, data);
	tranif1 I7003(buf_data, n5, ldCount);
	tranif1 I7004(n3, hnl_97, cnt_b);
	nor #(1) I7005(n7, cin_b, n1);
	not #(1) I7006(hnl_96, n5);
	not #(1) I7007(q_b, n5);
	buf I7022(buf_n4, n4);
	cxfr I7008(n5, n9, cnt_b, buf_n4);
	cxfr I7009(n2, cin_b, n8, n1);
	cxfr I7010(n2, n8, cin_b, n6);
	not #(1) I7011(n9, cnt_b);
	not #(1) I7012(n4, n3);
	not #(1) I7013(n1, q_b);
	not #(1) I7014(n6, n1);
	not #(1) I7015(n8, cin_b);
	not #(1) I7016(cout_b, n7);
	not #(1) U7017(hnl_97, n2);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBNcRA/ffBNcRA.v"
primitive ffBNcRA (Q, CLK, D_B, R_B);
    output Q; reg Q;
    input CLK;
    input D_B;
    input R_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D_B R_B  :state: output/nextState
        n        0  1    : ? :   1;
        n        1  ?    : ? :   0;
        // ignore positive edge of clock
        p        ?  ?    : ? :   -;
        // ignore data changes on steady clock
        ?        *  1    : ? :   -;
        // set output to 0
        ?        ?  0    : ? :   0;
        ?        ?  *    : 0 :   -;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ltxBarB/ltxBarB.v"
module ltxBarB (Q, EN, D_B);
    output Q;
    input EN;
    input D_B;

        latBNcA #(2) latBNcA0(Q, EN, D_B);

endmodule


// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latSRB/latSRB.v"
primitive latSRB (Q, D, EN, R_B, S);
    output Q; reg Q;
    input D;
    input EN;
    input R_B;
    input S;

table
//      D  EN  R_B  S  :state:      output/next state
        ?   0   1   0  : ? :        - ; // no change
        ?   0   0   0  : ? :        0 ; // clear output
        0   1   0   0  : ? :        0 ; // clear output
        1   1   0   0  : ? :        x ; // conflict

        ?   0   1   1  : ? :        1 ; // set output
        0   1   1   1  : ? :        1 ; // set output
        1   1   1   1  : ? :        x ; // conflict
        ?   ?   0   1  : ? :        x ; // conflict

        0   1   1   0  : ? :        0 ; // latch data
        1   1   1   0  : ? :        1 ; // latch data
        x   1   1   0  : ? :        x ; // latch data

        0   x   1   0  : 0 :        0 ; // reducing pessimism
        1   x   1   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?   ?  : ? :        - ;
        ?   0   ?   0  : 0 :        - ; // reducing pessimism
        ?   0   1   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/aoi211A/aoi211A.v"
// Description of an AND-OR-INVERT gate
// y = not ((A1 & A2) | B | C)
primitive aoi211A(Y, A1, A2, B, C);
output Y;
input A1, A2, B, C;

table
//	A1 A2 B  C : Y
	1  1  ?  ? : 0;
	?  ?  1  ? : 0;
	?  ?  ?  1 : 0;
	0  ?  0  0 : 1;
	?  0  0  0 : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latWA/latWA.v"
module latWA (A, Y);
    inout A;
    output Y;

  not #1(Y, A);
  not (weak1, weak0) (A, Y);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffQBB/ffQBB.v"
module ffQBB (Q, QB, D, CLK);
    output Q;
    output QB;
    input D;
    input CLK;

        supply1 vdd;
        supply0 gnd;
        ffA I1100(Q, D, CLK);
        not I1101(QB, Q);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffQBC/ffQBC.v"
module ffQBC (Q, QB, D, CLK);
    output Q;
    output QB;
    input D;
    input CLK;

        supply1 vdd;
        supply0 gnd;
        ffA I1100(Q, D, CLK);
        not I1101(QB, Q);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBarA/ffBarA.v"
primitive ffBarA (Q, CLK, D_B);
output Q; reg Q;
input  CLK, D_B;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes
//	neg logic output

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   1;
	n 	1 : ? :   0;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latEnbSB/latEnbSB.v"
primitive latEnbSB (Q, D, S, ENB);
output Q; reg Q;
input  D,S,ENB;

table
//	D   S  ENB  :state:	output/next state
        ?   0   1   : ? :        - ; // no change
        ?   1   1   : ? :        1 ; // set output
        1   1   0   : ? :        1 ; // set output
        0   1   0   : ? :        x ; // x if conflict

        0   0   0   : ? :        0 ; // latch data
        1   0   0   : ? :        1 ; // latch data
        x   0   0   : ? :        x ; // latch data

        0   0   x   : 0 :        0 ; // reducing pessimism
        1   0   x   : 1 :        1 ; // reducing pessimism
        ?   ?   p   : ? :        - ;
        ?   ?   1   : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/u5CMPV/u5CMPV.v"
module u5CMPV (CMPF, CMPV, Vext, VRef, VREG);
    output CMPF;
    input CMPV;
    input Vext;
    input VRef;
    input VREG;

supply1 vdd;
supply0 gnd;
not #(1) U137(hnl_151, hnl_152);
tranif0 P134(hnl_153, vdd, hnl_154);
tranif0 N133(hnl_154, vdd, hnl_154);
tranif1 N132(hnl_153, hnl_157, VREG);
tranif1 N131(hnl_154, hnl_157, VRef);
tranif1 N130(hnl_157, gnd, hnl_151);
not #(1) U141(CMPF, hnl_153);
not #(1) U136(hnl_152, CMPV);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latBNcA/latBNcA.v"
primitive latBNcA (Q, EN, D_B);
    output Q; reg Q;
    input EN;
    input D_B;

table
//     EN  D_B:state:   output/next state
        0   ? :  ?  :     - ; // no change

        1   0 :  ?  :     1 ; // transparent data
        1   1 :  ?  :     0 ; // transparent data
        1   x :  ?  :     x ; // latch data
 
        x   0 :  1  :     1 ; // reducing pessimism
        x   1 :  0  :     0 ; // reducing pessimism
        p   ? :  ?  :     - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latBarB/latBarB.v"
module latBarB (Q, EN, D_B);
    output Q;
    input EN;
    input D_B;

	latBNcA #(2) latBNcA0(Q, EN, D_B);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latB/latB.v"
module latB (Q, D, EN);
    output Q;
    input D;
    input EN;

	latBNcA #(2) latBNcA0(Q_b, EN, D);
	not not0(Q, Q_b);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBarC/ffBarC.v"
primitive ffBarC (Q_B, CLK, D);
output Q_B; reg Q_B;
input  CLK, D;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes
//	neg logic output

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   1;
	n 	1 : ? :   0;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBarB/ffBarB.v"
primitive ffBarB (Q, CLK, D_B);
output Q; reg Q;
input  CLK, D_B;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes
//	neg logic output

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   1;
	n 	1 : ? :   0;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffRA/ffRA.v"
primitive ffRA (Q, CLK, R_B, D);
    output Q; reg Q;
    input CLK;
    input R_B;
    input D;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge R_B D   :state: output/nextState
        n       ?   0   : ? :   0;
        n       1   1   : ? :   1;
        // ignore positive edge of clock
        p       ?   ?   : ? :   -;
        // ignore data changes on steady clock
        ?       1   *   : ? :   -;
        // set output to 0
        ?       0   ?   : ? :   0;
        ?       *   ?   : 0 :   -;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/srff/srff.v"
primitive srff (Q, S_B, R_B);
    output Q;reg Q;
    input S_B;
    input R_B;

table
//  S_B R_B : state : output/next state
     1   1  :  ?    :    -    ;
     1   0  :  ?    :    0    ;
     0   1  :  ?    :    1    ;
     0   0  :  ?    :    1    ;
     0   x  :  ?    :    1    ;
     1   x  :  0    :    -    ;
     x   1  :  1    :    -    ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/mux31/mux31.v"
// Description of an mux31
primitive mux31(Y_B, A, B, C, SelA, SelB, SelC);
output Y_B;reg Y_B;
input A, B, C, SelA, SelB, SelC;

table
//	A B C   SelA SelB SelC : state : Y_B/next state
	1 ? ?   1    0    0    :   ?   :   0 ;
	0 ? ?   1    0    0    :   ?   :   1 ;
	? 1 ?   0    1    0    :   ?   :   0 ;
	? 0 ?   0    1    0    :   ?   :   1 ;
	? ? 1   0    0    1    :   ?   :   0 ;
	? ? 0   0    0    1    :   ?   :   1 ;
	? ? ?   0    0    0    :   ?   :   - ; //no change
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/oai21A/oai21A.v"
// Description of an OR-AND-INVERT gate
// y = not ((A1 | A2) & B)
primitive oai21A(Y, A1, A2, B);
output Y;
input A1, A2, B;

table
//	A1 A2 B	: Y
	1  ?  1 : 0;
	?  1  1 : 0;
	0  0  ? : 1;
	?  ?  0 : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffA/ffA.v"
primitive ffA (Q, D, CLK);
    output Q; reg Q;
    input D;
    input CLK;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      D  CLKedge :state: output/nextState
        0    n     : ? :   0;
        1    n     : ? :   1;
        // ignore positive edge of clock
        ?    p     : ? :   -;
        // ignore data changes on steady clock
        *    ?     : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffB/ffB.v"
primitive ffB (Q, CLK, D);
output Q; reg Q;
input  CLK, D;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   0;
	n 	1 : ? :   1;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// Description of new_mux41.  A four to one mux
// with 2 select lines.  One line have to be
// selected all the time.
primitive new_mux41 (Y_B, A, B, C, D, Sel1, Sel0);
output Y_B;reg Y_B;
input A,B,C,D,Sel1,Sel0;

table
//      A  B  C  D Sel1 Sel0 : state: Y_B/next state
        0  ?  ?  ?  0    0   :   ?  :    1;     // sel 00
        1  ?  ?  ?  0    0   :   ?  :    0;

        ?  0  ?  ?  0    1   :   ?  :    1;     // sel 01
        ?  1  ?  ?  0    1   :   ?  :    0;

        ?  ?  0  ?  1    0   :   ?  :    1;     // sel 10
        ?  ?  1  ?  1    0   :   ?  :    0;

        ?  ?  ?  0  1    1   :   ?  :    1;     // sel 11
        ?  ?  ?  1  1    1   :   ?  :    0;

        0  0  ?  ?  0    ?   :   ?  :    1;     // sel 0x
        1  1  ?  ?  0    ?   :   ?  :    0;

        ?  ?  0  0  1    ?   :   ?  :    1;     // sel 1x
        ?  ?  1  1  1    ?   :   ?  :    0;

        0  ?  0  ?  ?    0   :   ?  :    1;     // sel x0
        1  ?  1  ?  ?    0   :   ?  :    0;

        ?  0  ?  0  ?    1   :   ?  :    1;     // sel x1
        ?  1  ?  1  ?    1   :   ?  :    0;

        0  0  0  0  ?    ?   :   ?  :    1;     // sel xx
        1  1  1  1  ?    ?   :   ?  :    0;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/mux41/mux41.v"
// Description of an mux41
primitive mux41 (Y_B, A, B, C, D, SelA, SelB, SelC, SelD);
output Y_B;reg Y_B;
input A,B,C,D,SelA,SelB,SelC,SelD;

table
//	A  B  C  D SelA SelB SelC SelD : state: Y_B/next state
        1  ?  ?  ?  1    0    0    0   :   ?  :    0;
        0  ?  ?  ?  1    0    0    0   :   ?  :    1;
        ?  1  ?  ?  0    1    0    0   :   ?  :    0;
        ?  0  ?  ?  0    1    0    0   :   ?  :    1;
        ?  ?  1  ?  0    0    1    0   :   ?  :    0;
        ?  ?  0  ?  0    0    1    0   :   ?  :    1;
        ?  ?  ?  1  0    0    0    1   :   ?  :    0;
        ?  ?  ?  0  0    0    0    1   :   ?  :    1;
        ?  ?  ?  ?  0    0    0    0   :   ?  :    -; // no change
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBNcA/ffBNcA.v"
primitive ffBNcA (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//         CLKedge  D_B :state: output/nextState
             n      0   : ? :   1;
             n      1   : ? :   0;
        // ignore positive edge of clock
             p      ?   : ? :   -;
        // ignore data changes on steady clock
             ?      *   : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latBEnbA/latBEnbA.v"
primitive latBEnbA (Q, D_B, ENB);
    output Q; reg Q;
    input D_B;
    input ENB;

table
//     D_B ENB:state:   output/next state
        ?   1 :  ?  :     - ; // no change

        0   0 :  ?  :     1 ; // transparent data
        1   0 :  ?  :     0 ; // transparent data
        x   0 :  ?  :     x ; // latch data

        0   x :  1  :     1 ; // reducing pessimism
        1   x :  0  :     0 ; // reducing pessimism
        ?   n :  ?  :     - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/latBarA/latBarA.v"
module latBarA (Q, EN, D_B);
    output Q;
    input EN;
    input D_B;

	latBNcA #(2) latBNcA0(Q, EN, D_B);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/mux21/mux21.v"
// Description of an mux21
primitive mux21(Y, A, B, SelB);
output Y;
input A, B, SelB;

table
//	A  B  SelB : Y
        ?  1  1    : 1;
        ?  0  1    : 0;
        1  ?  0    : 1;
        0  ?  0    : 0;
        0  0  ?    : 0;
        1  1  ?    : 1;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffNcA/ffNcA.v"
primitive ffNcA (Q, D, CLK);
    output Q; reg Q;
    input D;
    input CLK;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      D  CLKedge :state: output/nextState
        0    n     : ? :   0;
        1    n     : ? :   1;
        // ignore positive edge of clock
        ?    p     : ? :   -;
        // ignore data changes on steady clock
        *    ?     : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffC/ffC.v"
primitive ffC (Q, CLK, D);
output Q; reg Q;
input  CLK, D;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   0;
	n 	1 : ? :   1;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/aoi21A/aoi21A.v"
// Description of an AND-OR-INVERT gate
// y = not ((A1 & A2) | B)
primitive aoi21A(Y, A1, A2, B);
output Y;
input A1, A2, B;

table
//	A1 A2 B	: Y
	1  1  ? : 0;
	?  ?  1 : 0;
	0  ?  0 : 1;
	?  0  0 : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ltxRB/ltxRB.v"
primitive ltxRB (Q, D, EN, R_B);
output Q; reg Q;
input  D,EN,R_B;

table
//      D  EN  R_B :state:      output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        0   1   0  : ? :        0 ; // clear output
        1   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        0 ; // latch data
        1   1   1  : ? :        1 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 0 :        0 ; // reducing pessimism
        1   x   1  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revC.0/chip/ffBarRA/ffBarRA.v"
primitive ffBarRA (Q, CLK, D_B, R_B);
    output Q; reg Q;
    input CLK;
    input D_B;
    input R_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D_B R_B  :state: output/nextState
        n        0  1    : ? :   1;
        n        1  ?    : ? :   0;
        // ignore positive edge of clock
        p        ?  ?    : ? :   -;
        // ignore data changes on steady clock
        ?        *  1    : ? :   -;
        // set output to 0
        ?        ?  0    : ? :   0;
        ?        ?  *    : 0 :   -;

endtable

endprimitive


// End HDL models


module lvtncap (MINUS, PLUS);
inout MINUS, PLUS;
supply1 vdd;
supply0 gnd;
endmodule

module u5BENSad (NSAdr_7_, NSAdr_6_, NSAdr_5_, NSAdr_4_, NSAdr_3_, NSAdr_2_, NSAdr_1_, NSAdr_0_, BEevenD, BEoddD, loadNSAdr, rclk, writeOp_b);
output NSAdr_7_, NSAdr_6_, NSAdr_5_, NSAdr_4_, NSAdr_3_, NSAdr_2_, NSAdr_1_, NSAdr_0_;
input BEevenD, BEoddD, loadNSAdr, rclk, writeOp_b;
supply1 vdd;
supply0 gnd;
ffBarRA F94BO(hnl_0, gnd, gnd, vdd);
ltxRB F94BN(hnl_1, gnd, gnd, vdd);
aoi21A #(1) F94BM(hnl_2, gnd, gnd, gnd);
ffC #(1) F94BL(hnl_3, gnd, gnd);
nand #(0) F94BI(hnl_4, gnd, gnd, gnd, gnd);
nor #(1) F94BK(hnl_5, gnd, gnd);
nor #(1) F94BJ(hnl_6, gnd, gnd);
nand #(1) F94BH(hnl_7, gnd, gnd);
nand #(1) F94BG(hnl_8, gnd, gnd);
not #(1) F94BF(hnl_9, gnd);
not #(1) F94BE(hnl_10, gnd);
ffNcA I160(hnl_11, BEoddD, rclk);
ffNcA I159(hnl_12, hnl_11, rclk);
ffNcA I158(hnl_13, hnl_12, rclk);
ffNcA I155(hnl_14, hnl_15, rclk);
ffNcA I154(hnl_15, hnl_16, rclk);
ffNcA I153(hnl_16, BEevenD, rclk);
mux21 #(1) I152(hnl_17, hnl_14, BEevenD, writeOp_b);
mux21 #(1) I146(hnl_18, hnl_13, BEoddD, writeOp_b);
latBarA I140(pre3, rclk, hnl_19);
latBarA I139(pre1, rclk, hnl_20);
latBarA I137(pre5, rclk, hnl_21);
latBarA I135(pre7, rclk, hnl_18);
latBarA I134(pre0, rclk, hnl_22);
latBarA I126(pre6, rclk, hnl_17);
latBarA I124(pre4, rclk, hnl_23);
latBarA I121(pre2, rclk, hnl_24);
latBEnbA I141(hnl_20, pre3, rclk);
latBEnbA I138(hnl_19, pre5, rclk);
latBEnbA I136(hnl_21, pre7, rclk);
latBEnbA I122(hnl_24, pre4, rclk);
latBEnbA I123(hnl_23, pre6, rclk);
latBEnbA I120(hnl_22, pre2, rclk);
ffBNcA I119(hnl_25, loadNSAdr, pre7);
ffBNcA I118(hnl_26, loadNSAdr, pre5);
ffBNcA I117(hnl_27, loadNSAdr, pre3);
ffBNcA I116(hnl_28, loadNSAdr, pre1);
ffBNcA I115(hnl_29, loadNSAdr, pre6);
ffBNcA I114(hnl_30, loadNSAdr, pre4);
ffBNcA I113(hnl_31, loadNSAdr, pre2);
ffBNcA I112(hnl_32, loadNSAdr, pre0);
not #(1) I110(NSAdr_3_, hnl_27);
not #(1) I109(NSAdr_5_, hnl_26);
not #(1) I86(NSAdr_7_, hnl_25);
not #(1) I85(NSAdr_6_, hnl_29);
not #(1) I84(NSAdr_1_, hnl_28);
not #(1) I80(NSAdr_2_, hnl_31);
not #(1) I77(NSAdr_0_, hnl_32);
not #(1) I74(NSAdr_4_, hnl_30);
endmodule

module invEEbuf (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) I17(hnl_33, hnl_34);
not #(1) U9(Y, hnl_33);
not #(1) U16(hnl_34, A);
endmodule

module u5OpDeco (MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, writeMaskedNSOp_b, writeOp_b, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, op_3_, op_0_,
op_b_2_, op_b_1_, rclk);
output MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, writeMaskedNSOp_b, writeOp_b;
input DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, op_3_, op_0_, op_b_2_, op_b_1_, rclk;
supply1 vdd;
supply0 gnd;
not #(1) U345(writeOp_b, hnl_35);
not #(1) U254(op_1_, op_b_1_);
nor #(1) I333(abortOperation_b, illegalOpCode, initAbort);
aoi21A #(1) U332(colD, op_b_2_, op_b_3_, op_1_);
nor #(1) U331(colC, op_1_, hnl_36, hnl_37);
nor #(1) U340(hnl_38, op_b_1_, op_2_);
nor #(1) U330(hnl_36, op_2_, op_3_);
nor #(1) U329(hnl_37, op_b_2_, op_b_3_);
nor #(1) U328(selD, OpX_b_1_, OpX_b_0_);
nor #(1) U327(selC, OpX_b_1_, OpX_0_);
nor #(1) U326(selB, OpX_1_, OpX_b_0_);
nor #(1) U325(selA, OpX_1_, OpX_0_);

////////////////////////////////////////////////////////////////////////////////

// hack

//mux41 #(1) I320(illegalOpCode, colA, op_b_1_, colC, colD, selA, selB, selC, selD);

new_mux41 #(1) I320(illegalOpCode, colA, op_b_1_, colC, colD, OpX_1_, OpX_0_);

////////////////////////////////////////////////////////////////////////////////

ffB #(1) I310(REQinhibiten, rclk, hnl_39);
not #(1) U305(WPBNP, hnl_40);
ffA I344(hnl_41, OpX_1_, rclk);
ffA I304(hnl_42, hnl_43, rclk);
ffA I303(hnl_44, hnl_45, rclk);
invEEbuf U300(MPBT, hnl_46);
invEEbuf U299(WPBT, hnl_47);
nor #(1) U342(colA, hnl_38, hnl_48);
nor #(1) U292(initAbort, hnl_49, deviceEnableMode);
nor #(1) U289(hnl_45, hnl_41, OpX_0_);
nor #(1) U343(hnl_48, op_b_3_, op_b_1_, op_0_);
nor #(1) U281(hnl_50, op_b_3_, op_b_2_, op_1_);
not #(1) U256(writeMaskedNSOp_b, hnl_50);
mux21 #(1) I347(hnl_51, op_b_0_, op_b_2_, op_b_1_);
mux21 #(1) I219(hnl_46, hnl_52, hnl_42, DAmode_b);
mux21 #(1) I212(hnl_47, hnl_53, hnl_44, DAmode_b);
nand #(1) U346(hnl_35, hnl_51, op_b_3_);
nand #(1) I243(NSOp, hnl_54, hnl_55);
nand #(1) U317(hnl_39, hnl_56, writeMaskedNSOp_b);
oai21A U291(hnl_49, regWrite_b, SInRaw_b, bcastWrite_b);
nand #(1) U319(hnl_54, op_b_2_, OpX_0_);
nand #(1) U275(hnl_55, op_3_, op_b_1_);
nand #(1) U313(hnl_56, op_3_, WPBNP);
nand #(1) U285(hnl_43, hnl_41, OpX_0_);
nand #(1) U284(hnl_40, colC, selC);
nand #(1) U271(regWrite_b, op_1_, op_0_);
nand #(1) U270(bcastWrite_b, op_3_, op_1_);
not #(1) U349(op_b_0_, op_0_);
not #(1) U236(hnl_52, TestMPBT);
not #(1) U224(hnl_53, TestWPBT);
not #(1) U320(op_2_, op_b_2_);
not #(1) U253(op_b_3_, op_3_);
not #(1) U233(OpX_b_1_, OpX_1_);
not #(1) U232(OpX_b_0_, OpX_0_);
endmodule

module u5CdlyCt (startCycle_b, CASenable, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_, writeOp_b);
output startCycle_b;
input CASenable, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_, writeOp_b;
supply1 vdd;
supply0 gnd;
nor #(1) U568(hnl_57, Q2, Q1, Q0_b);
ffC #(1) I488(preCycState4, rclk, writeA45);
mux21 #(1) I582(hnl_58, delayStart_b, preCycState4, delay0);
mux21 #(1) I579(hnl_59, hnl_57, preCycState4, delay1);
mux21 #(1) I489(hnl_58, delayStart_b, preCycState4, delay0);
nor #(1) U576(hnl_60, reset, hnl_61);
nand #(0) U572(hnl_62, readDelay_2_, readDelay_1_, readDelay_0_, writeOp_b);
nand #(0) U571(hnl_63, writeDelay_b_2_, writeDelay_b_1_, writeDelay_0_, writeOp);
nand #(0) U570(hnl_64, readDelay_b_2_, readDelay_b_1_, readDelay_b_0_, writeOp_b);
nand #(0) U569(hnl_65, writeDelay_b_2_, writeDelay_1_, writeDelay_b_0_, writeOp);
not #(1) U581(preCycState4_b, preCycState4);
not #(1) U529(writeOp, writeOp_b);
nand #(1) U566(hnl_66, hnl_67, hnl_68, hnl_69);
ffBarRA I557(Q0, rclk, hnl_70, hnl_60);
ffBarRA I556(Q1, rclk, hnl_71, hnl_60);
ffBarRA I554(Q2, rclk, hnl_72, hnl_60);
aoi21A #(1) U538(hnl_73, writeDelay_b_1_, writeDelay_b_0_, writeDelay_b_2_);
nand #(1) U574(delay0, hnl_63, hnl_62);
nand #(1) U573(delay1, hnl_65, hnl_64);
nand #(1) I551(hnl_74, hnl_75, hnl_76);
nand #(1) I550(hnl_77, hnl_78, hnl_75);
nand #(1) U546(hnl_79, hnl_80, hnl_81);
nand #(1) U541(hnl_82, hnl_69, hnl_83);
nand #(1) U535(Y2, hnl_84, hnl_85);
nand #(1) U565(hnl_67, writeDelay_b_1_, writeDelay_b_0_);
nand #(1) U564(hnl_68, writeDelay_2_, writeDelay_b_0_);
nand #(1) U548(hnl_76, readDelay_b_1_, readDelay_0_);
nand #(1) U545(hnl_75, readDelay_b_2_, readDelay_1_);
nand #(1) U544(hnl_78, readDelay_2_, readDelay_b_0_);
nand #(1) U543(hnl_81, readDelay_2_, readDelay_b_1_);
nand #(1) U540(hnl_83, writeDelay_1_, writeDelay_0_);
nand #(1) U539(hnl_69, writeDelay_2_, writeDelay_b_1_);
nand #(1) U533(hnl_84, Q1, Q0_b);
nor #(1) U575(hnl_61, CASenable, preCycState5_b);
nor #(1) U528(loadRead, preCycState4_b, writeOp);
nor #(1) U527(loadWrite, preCycState4_b, writeOp_b);
nand #(1) U542(hnl_80, readDelay_b_2_, readDelay_1_, readDelay_0_);
nand #(1) U534(hnl_85, Q2, Q1_b, Q0);
ffB #(1) I492(delayStart_b, rclk, hnl_59);
ffB #(1) I443(preCycState5, rclk, preCycState4);
mux31 #(1) I507(hnl_72, Y2, hnl_73, hnl_79, preCycState4_b, loadWrite, loadRead);
mux31 #(1) I509(hnl_70, Q1, hnl_82, hnl_74, preCycState4_b, loadWrite, loadRead);
mux31 #(1) I508(hnl_71, Q2, hnl_66, hnl_77, preCycState4_b, loadWrite, loadRead);
not #(1) U486(startCycle_b, hnl_58);
not #(1) U580(preCycState5_b, preCycState5);
not #(1) U559(Q0_b, Q0);
not #(1) U558(Q1_b, Q1);
not #(1) U525(writeDelay_b_2_, writeDelay_2_);
not #(1) U524(writeDelay_b_1_, writeDelay_1_);
not #(1) U523(readDelay_b_2_, readDelay_2_);
not #(1) U522(readDelay_b_1_, readDelay_1_);
not #(1) U461(readDelay_b_0_, readDelay_0_);
not #(1) U387(writeDelay_b_0_, writeDelay_0_);
endmodule

module u5CDOpCk (MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, regOp, startCycle_b, writeMaskedNSOp_b, writeOp_b, CASenable, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT,
deviceEnableMode, opcode_3_, opcode_0_, opcode_b_2_, opcode_b_1_, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_);
output MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, regOp, startCycle_b, writeMaskedNSOp_b, writeOp_b;
input CASenable, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, opcode_3_, opcode_0_, opcode_b_2_, opcode_b_1_, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset,
writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_;
supply1 vdd;
supply0 gnd;
u5OpDeco OpDeco(MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, writeMaskedNSOp_b, writeOp_b, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, opcode_3_, opcode_0_,
opcode_b_2_, opcode_b_1_, rclk);
u5CdlyCt CdlyCt(startCycle_b, CASenable, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_, writeOp_b);
not #(1) I291(regOp, opcode_b_1_);
endmodule

module u5RdTclk (rdPipeBusy_b, readOpD, tclkDisable_b, CASenable, CASstate3, ackWinOver, busyError_b, earlyDone, rclk, readOp, readOpD2, reset_b);
output rdPipeBusy_b, readOpD, tclkDisable_b;
input CASenable, CASstate3, ackWinOver, busyError_b, earlyDone, rclk, readOp, readOpD2, reset_b;
supply1 vdd;
supply0 gnd;
latBarA I40(trueReadOp, ackWinOver, hnl_86);
not #(1) U32(rdPipeBusy_b, haltCount_b);
srff I31(haltCount_b, hnl_87, stopCounterP_b);
ffRA I30(stopCounterP_b, rclk, reset_b, hnl_88);
ffBarB #(1) I34(tclkDisable_b, rclk, hnl_89);
ffBarB #(1) I29(RdTCk3, rclk, RdTCk2);
ffA I37(readOpD, readOp, rclk);
ffA I27(RdTck1, hnl_90, rclk);
ffA I26(RdTCk2, RdTck1, rclk);
oai21A U15(hnl_89, hnl_91, trueReadOp, stopCounterP_b);
nand #(1) U41(hnl_86, busyError_b, CASenable, readOp);
nand #(1) U35(hnl_87, CASstate3, earlyDone, readOpD2);
nand #(1) U218(hnl_88, RdTCk3, RdTCk2, RdTck1);
nand #(1) U214(hnl_90, hnl_92, haltCount_b);
not #(1) U6(hnl_91, ackWinOver);
xor #(1) U220(hnl_92, RdTCk3, RdTCk2);
endmodule

module u5XS (rdPipeBusy_b, tclkDisable_b, CASenable, CASstate3_buf, ackWinOver, busyError_b, earlyDone, rclk, reset, writeOp_b);
output rdPipeBusy_b, tclkDisable_b;
input CASenable, CASstate3_buf, ackWinOver, busyError_b, earlyDone, rclk, reset, writeOp_b;
supply1 vdd;
supply0 gnd;
nor #(1) U28(hnl_93, hnl_94, hnl_94);
nor #(1) U25(readOpD2, hnl_95, hnl_95);
nand #(1) U8(hnl_95, hnl_93, hnl_93);
nand #(1) U17(hnl_94, readOpD, readOpD);
not #(1) U3(reset_b, reset);
u5RdTclk RdTclk(rdPipeBusy_b, readOpD, tclkDisable_b, CASenable, CASstate3_buf, ackWinOver, busyError_b, earlyDone, rclk, writeOp_b, readOpD2, reset_b);
endmodule

module invEE (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) U9(Y, A);
endmodule

module u5GoFish (Out_T, In_R, mtclk, rclk, skip);
output Out_T;
input In_R, mtclk, rclk, skip;
supply1 vdd;
supply0 gnd;
mux21 #(1) I43(mg4, n03, n13, skip);
not #(1) I52(Out_T, mg6);
not #(1) U46(mg3, mg2);
not #(1) U54(hnl_96, gnd);
not #(1) U53(hnl_97, gnd);
not #(1) U55(hnl_98, gnd);
not #(1) I31(mg5, mg4);
not #(1) U44(mg1, mtclk);
ffA I25(n03, n01, txdly);
ffA I51(mg6, mg5, mtclk);
ffA I28(n01, In_R, rclk);
ffA I34(n13, n11, txdly);
latB I36(n11, In_R, rclk);
not #(5) U47(txdly, mg3);
not #(1) U45(mg2, mg1);
endmodule

module u5BSNack (BCOeven_b, BCOodd_b, RASaddrEnable, sytload_b, BusCtrlEn_b, LoadShiftRegister_b, ackLatch, bcastWrite, idHitA, idHitB, latchAbort_b, mtclk, nack, rclk, reset, skip, writeA45);
output BCOeven_b, BCOodd_b, RASaddrEnable, sytload_b;
input BusCtrlEn_b, LoadShiftRegister_b, ackLatch, bcastWrite, idHitA, idHitB, latchAbort_b, mtclk, nack, rclk, reset, skip, writeA45;
supply1 vdd;
supply0 gnd;
ffBarC #(1) I634(hnl_99, rclk, writeA45);
aoi21A #(1) U612(idBcw, idHitA, idHitB, bcastWrite);
not #(1) U626(T12, hnl_100);
invEE U635(RASaddrEnable, hnl_99);
invEE U625(sytload_b, hnl_101);
not #(1) U624(hnl_101, hnl_102);
u5GoFish BDsync(hnl_102, LoadShiftRegister_b, mtclk, rclk, skip);
u5GoFish BCsync(hnl_100, BusCtrlEn_b, mtclk, rclk, skip);
latBarB I620(T13, mtclk, hnl_100);
nand #(1) U606(BCOodd_b, T13, nk);
nand #(1) U607(BCOeven_b, T12, ok);
nor #(1) U615(okp, idNbcw, go_b, nack);
nor #(1) U613(nkp, nack_b, go_b, idBcw);
nand #(1) U608(idNbcw, idHitA, idHitB, bcastWrite_b);
nand #(1) U605(go_b, latchAbort_b, reset_b);
latBNcA I580(nk, ackLatch, hnl_103);
latBNcA I579(ok, ackLatch, hnl_104);
not #(1) U633(bcastWrite_b, bcastWrite);
not #(1) U614(nack_b, nack);
not #(1) U611(reset_b, reset);
not #(1) U581(hnl_103, nkp);
not #(1) U578(hnl_104, okp);
endmodule

module nandpc2 (Y, A, PC);
inout Y;
input A, PC;
supply1 vdd;
supply0 gnd;
tranif0 P1(Y, vdd, PC);
tranif1 N1(Y, hnl_105, A);
tranif1 N2(hnl_105, gnd, PC);
endmodule

module u5RshCtl (AUXRASreq, AUXorPDcycle, A_1_, PDreq2, RASrfshRetD, RefreshReturn_b, close0Req_b, close1Req_b, closeCycle, closeCycle_b, doAUXcycle, driveRfshAddr_b, endCycleD_buf, restoreBank0,
restoreBank1, PD64after, PreScx_b, RASAUXRet_b, RASidle_b, clearPDreq2, close0Pending_b, close0Selected, close1Pending_b, close1Selected, decXferCnt_b, enableRefreshMode, evalRfshCount,
explicitRestore, idle, incRfshRow_b, packetBSELx, powerDownReq_b, rclk, reFetchCycle, reset, rfshEqualsZero, setRR_b, writeA45, writeA0123x);
output AUXRASreq, AUXorPDcycle, A_1_, PDreq2, RASrfshRetD, RefreshReturn_b, close0Req_b, close1Req_b, closeCycle, closeCycle_b, doAUXcycle, driveRfshAddr_b, endCycleD_buf, restoreBank0, restoreBank1;
input PD64after, PreScx_b, RASAUXRet_b, RASidle_b, clearPDreq2, close0Pending_b, close0Selected, close1Pending_b, close1Selected, decXferCnt_b, enableRefreshMode, evalRfshCount, explicitRestore,
idle, incRfshRow_b, packetBSELx, powerDownReq_b, rclk, reFetchCycle, reset, rfshEqualsZero, setRR_b, writeA45, writeA0123x;
supply1 vdd;
supply0 gnd;
latEnbSB I508(hnl_106, setRR_b, hnl_107, decXferCnt_b);
latEnbSB I431(hnl_108, powerDownReq_b, hnl_109, decXferCnt_b);
nand #(1) U501(AUXorPDcycle, doAUXcycle_b, hnl_110, PDreq2_b);
nor #(1) U493(hnl_111, idle_b, writeA0123x, writeA45);
ffBarA #(1) I497(hnl_112, rclk, hnl_113);
ffBarC #(1) I486(close1Req_b, rclk, PDClose);
ffBarC #(1) I485(close0Req_b, rclk, PDClose);
nand #(1) U428(hnl_114, refreshCycle_b, PDreq2_b);
not #(1) U429(driveRfshAddr_b, hnl_114);
not #(1) U434(hnl_109, resetPD_b);
mux21 #(1) I500(preRB0, hnl_115, packetBSELx, explicitRestore);
mux21 #(1) I499(preRB1, hnl_116, hnl_117, explicitRestore);
mux21 #(1) I411(preRB1, hnl_116, hnl_117, explicitRestore);
mux21 #(1) I405(preRB0, hnl_115, packetBSELx, explicitRestore);
not #(1) U410(hnl_117, packetBSELx);
ffQBC I401(rfshSelected_b, rfshSelected, hnl_118, rclk);
ffB #(1) I479(PDreq2_b, rclk, hnl_119);
ffB #(1) I387(hnl_120, rclk, PD64after);
ffB #(1) I384(AUXRASreq, rclk, hnl_121);
not #(1) U365(RASrfshRetD, hnl_122);
nor #(1) I399(doAUXcycleLocal, A_0_, A_1_);
nor #(1) I346(endCycle_b, hnl_123, reset);
ffBarRA I335(powerDownReqD, rclk, hnl_108, resetPD_b);
not #(1) I448(endCycleD_buf, endCycleD_b);
not #(1) U322(doAUXcycle, doAUXcycle_b);
nor #(1) U314(cyclePending_b, rfshSelected, close0Selected, close1Selected);
nor #(1) U498(hnl_113, hnl_124, RASidle_b);
nor #(1) I352(hnl_123, hnl_50, A_0_);
nor #(1) U416(hnl_125, hnl_122, reFetchCycle);
nor #(1) U305(PDClose, hnl_108, powerDownReqD);
ffBarB #(1) I419(RASAUXRetD, rclk, RASAUXRet_b);
oai21A U487(hnl_126, hnl_111, hnl_127, A_b_1_);
oai21A U279(hnl_128, hnl_112, writeA0123x, A_0_);
oai21A U281(hnl_50, reFetchCycle, rfshSelected_b, RASAUXRetD);
nand #(1) I421(hnl_129, endCycle_b, endCycleD_b, hnl_130);
nand #(1) U377(hnl_121, hnl_131, startAUX_b, startPDRAScyc_b);
nand #(1) U276(hnl_132, endCycle_b, hnl_128, A_b_1_);
ffQBB I495(hnl_124, hnl_127, hnl_126, rclk);
ffQBB I403(endCycleD_b, endCycleD, endCycle_b, rclk);
ffQBB I396(closeCycle_b, closeCycle, hnl_133, rclk);
ffQBB I275(A_0_, A_b_0_, hnl_132, rclk);
ffQBB I273(A_1_, A_b_1_, hnl_129, rclk);
nand #(1) U511(hnl_107, reset_b, incRfshRow_b);
nand #(1) U469(hnl_134, reset_b, powerDownReq_b);
nand #(1) U333(hnl_135, hnl_106, hnl_136);
nand #(1) U414(hnl_115, close0Selected, doAUXcycle);
nand #(1) U415(hnl_116, close1Selected, doAUXcycle);
nand #(1) U460(RefreshReturn_b, endCycleD, rfshSelected);
nand #(1) U417(hnl_122, rfshSelected, RASAUXRetD);
nand #(1) U292(doAUXcycle_b, A_b_1_, A_b_0_);
not #(1) U362(PDreq2, PDreq2_b);
not #(1) U229(restoreBank0, preRB0);
not #(1) U230(restoreBank1, preRB1);
aoi21A #(1) U245(hnl_137, endCycleD, rfshSelected, hnl_134);
ffBarA #(1) I400(hnl_138, rclk, doAUXcycleLocal);
ffBarA #(1) I382(hnl_139, rclk, hnl_120);
ffBarA #(1) I332(rfshReq_b, rclk, hnl_135);
latWA U225(rfshEqualsZero, hnl_140);
nor #(1) U502(hnl_110, close0Selected, close1Selected);
nor #(1) U357(resetPD_b, clearPDreq2, reset);
nand #(1) U481(hnl_141, rfshSelected, A_b_1_, A_b_0_);
nand #(1) U480(hnl_133, refreshCycle_b, doAUXcycle, hnl_119);
nand #(1) U445(hnl_118, rfshPending, close1Pending_b, close0Pending_b);
nand #(1) U309(setPDmode_b, close1Selected, endCycleD, powerDownReqD);
nand #(1) U242(hnl_136, rfshEqualsZero, PreScx_b, enableRefreshMode);
nand #(1) U397(startAUX_b, doAUXcycleLocal, hnl_138);
nand #(1) U383(startPDRAScyc_b, hnl_120, hnl_139);
nand #(1) U366(hnl_131, hnl_125, doAUXcycleLocal);
nand #(1) U278(hnl_130, cyclePending_b, A_1_);
not #(1) U494(idle_b, idle);
not #(1) U478(hnl_119, hnl_142);
not #(1) U467(reset_b, reset);
nandpc2 U83(rfshEqualsZero, reset, evalRfshCount);
srff I342(refreshCycle_b, endCycleD_b, hnl_141);
srff I310(hnl_142, setPDmode_b, resetPD_b);
srff I244(rfshPending, rfshReq_b, hnl_137);
endmodule

module slDly (out, in_b);
output out;
input in_b;
supply1 vdd;
supply0 gnd;
not #(100) U54(out, hnl_143);
not #(1) U46(hnl_144, hnl_86);
not #(1) U43(hnl_145, hnl_146);
not #(1) U41(hnl_86, in_b);
not #(1) U39(hnl_146, hnl_147);
not #(1) U38(hnl_143, hnl_145);
not #(1) U36(hnl_148, hnl_144);
not #(1) U33(hnl_149, hnl_148);
not #(1) U31(hnl_147, hnl_149);
endmodule

module u5Rasb (RASB, RASpending, RASpending_b, clearPDreq2, drivePacketRASaddr, incRfshRow_b, powerDownMode, reFetchCycle, reFetchCycle_b, updateRowAddr, AUXRASreq, BIMDI, DAmode_b, PDreq2, RASkill,
RASprecharge, RASrfshRetD, RASstate4, RS_0_, SInRaw_b, TestRASB, clearRASpending_b, doAUXcycle, endPowerDown_b, explicitRestore, idHitRowMiss, latchAbort, rclk, reset, rfshCout_1_, setPD, standby,
writeA0123x);
output RASB, RASpending, RASpending_b, clearPDreq2, drivePacketRASaddr, incRfshRow_b, powerDownMode, reFetchCycle, reFetchCycle_b, updateRowAddr;
input AUXRASreq, BIMDI, DAmode_b, PDreq2, RASkill, RASprecharge, RASrfshRetD, RASstate4, RS_0_, SInRaw_b, TestRASB, clearRASpending_b, doAUXcycle, endPowerDown_b, explicitRestore, idHitRowMiss,
latchAbort, rclk, reset, rfshCout_1_, setPD, standby, writeA0123x;
supply1 vdd;
supply0 gnd;
aoi211A #(1) I825(hnl_150, RASstate4, idHitRowMiss, AUXRASreq, RASpending);
aoi211A #(1) I823(hnl_151, idHitRowMiss, RASstate4, RASleading, RASaddrEn);
not #(1) U625(RASB, hnl_152);
nor #(1) I816(RASaddrInh_b, hnl_153, explicitRestore);
invEE U815(drivePacketRASaddr, hnl_154);
ffRA I811(RASaddrEn, rclk, RASaddrInh_b, hnl_155);
not #(1) U810(hnl_154, RASaddrEn);
nor #(1) U800(hnl_156, hnl_150, latchAbort, hnl_157);
aoi21A #(1) U783(hnl_158, updateKill_b, setPD_b, hnl_159);
nand #(1) U786(hnl_160, RASleading, RASkill_b, updateKill_b);
ffB #(1) I775(RASp1, rclk, hnl_161);
ffB #(1) I774(RASp2, rclk, RASp1);
ffB #(1) I770(reFetchCycle_b, rclk, hnl_162);
not #(1) I753(reFetchCycle, reFetchCycle_b);
ffBarB #(1) I784(updateKill_b, rclk, hnl_158);
ffBarB #(1) I737(clearPDreq2, rclk, hnl_163);
nand #(1) U817(hnl_153, DAmode_b, RASkill_b, reset_b);
nand #(1) U771(hnl_162, hnl_164, reset_b, doAUXcycle);
nand #(1) U699(hnl_165, RASp1, RASp2, RASp3);
srff I805(hnl_166, endPowerDown_b, setPD_b);
srff I724(powerDownMode_b, endPowerDown_b, hnl_167);
slDly I714(delayedRASB_b, RASB);
not #(1) U711(incRfshRow_b, hnl_168);
nand #(1) I710(hnl_168, hnl_169, burstRfshInc_b);
nand #(1) U788(hnl_159, RS_0_, reset_b);
nand #(1) U592(hnl_170, hnl_171, DAmode_b);
ffA I767(burstRfshInc_b, hnl_172, rclk);
ffA I700(RASp3, RASp2, rclk);
ffQBC I697(RASpending, RASpending_b, hnl_156, rclk);
nor #(1) I693(RASleading, RASp2, hnl_173);
not #(1) U732(powerDownMode, powerDownMode_b);
not #(1) U681(updateRowAddr, hnl_160);
nand #(1) U698(hnl_174, hnl_165, forceRAS_b);
nor #(1) U812(hnl_155, hnl_151, doAUXcycle, writeA0123x);
nor #(1) U633(hnl_175, hnl_171, SInRaw_b);
nor #(1) U703(hnl_161, RASprecharge, hnl_170);
nor #(1) U647(forceRAS_b, hnl_176, hnl_175);
not #(1) U821(hnl_177, hnl_178);
not #(1) U820(hnl_152, hnl_177);
not #(1) U819(hnl_178, hnl_179);
not #(1) U818(hnl_179, hnl_174);
not #(1) U799(RASkill_b, RASkill);
not #(1) U806(hnl_180, hnl_166);
not #(1) U801(hnl_157, clearRASpending_b);
not #(1) U769(doAUXcycle_b, doAUXcycle);
not #(1) U730(hnl_181, BIMDI);
not #(1) U726(setPD_b, setPD);
not #(1) U657(reset_b, reset);
not #(1) U628(hnl_176, TestRASB);
not #(1) U600(hnl_171, PDreq2);
nand #(1) U807(hnl_167, hnl_180, standby);
nand #(1) U772(hnl_164, hnl_182, reFetchCycle_b);
nand #(1) U766(hnl_172, RASrfshRetD, reFetchCycle_b);
nand #(1) U746(hnl_182, RASrfshRetD, rfshCout_1_);
nand #(1) U738(hnl_163, RASprecharge, PDreq2);
nand #(1) U733(hnl_169, delayedRASB_b, PDrfshEn);
nand #(1) U731(PDrfshEn, powerDownMode_b, hnl_181);
nand #(1) U692(hnl_173, RASp1, doAUXcycle_b);
endmodule

module u5AkWDly (BusCtrlEn_b, ackClear, ackLatch, ackWinOver, ackWinOverD, inhLoadLast_b, ackDelay_1_, ackDelay_0_, ackWinDelay_2_, ackWinDelay_1_, ackWinDelay_0_, eval, loadDelay, rclk, reset);
output BusCtrlEn_b, ackClear, ackLatch, ackWinOver, ackWinOverD, inhLoadLast_b;
input ackDelay_1_, ackDelay_0_, ackWinDelay_2_, ackWinDelay_1_, ackWinDelay_0_, eval, loadDelay, rclk, reset;
supply1 vdd;
supply0 gnd;
ffBarB #(1) I115(inhLoadLast_b, rclk, hnl_183);
mux21 #(1) I98(hnl_184, hnl_185, hnl_186, code0567);
oai21A U83(hnl_183, hnl_187, inhLoadLast_b, eval);
nor #(1) U6_3_(ackWsel_3_, ackWselect_b_0_, ackWselect_b_1_);
nor #(1) U6_2_(ackWsel_2_, ackWselect_0_, ackWselect_b_1_);
nor #(1) U6_1_(ackWsel_1_, ackWselect_b_0_, ackWselect_1_);
nor #(1) U6_0_(ackWsel_0_, ackWselect_0_, ackWselect_1_);
nand #(1) U89(hnl_188, ackWselect_b_0_, ackWselect_b_1_, ackWselect_b_2_);
oai21A U88(hnl_189, ackWselect_1_, ackWselect_0_, ackWselect_2_);
nand #(1) U78(ackLatch, hnl_190, hnl_191, reset_b);
latB I59_1_(ackSelect_1_, ackDelay_1_, loadDelay);
latB I59_0_(ackSelect_0_, ackDelay_0_, loadDelay);
latB I58_2_(ackWselect_2_, ackWinDelay_2_, loadDelay);
latB I58_1_(ackWselect_1_, ackWinDelay_1_, loadDelay);
latB I58_0_(ackWselect_0_, ackWinDelay_0_, loadDelay);
nand #(1) U20(code0567, hnl_189, hnl_188);
not #(1) U97(BusCtrlEn_b, hnl_192);
not #(1) U73_1_(ackSelect_b_1_, ackSelect_1_);
not #(1) U73_0_(ackSelect_b_0_, ackSelect_0_);
not #(1) U72_2_(ackWselect_b_2_, ackWselect_2_);
not #(1) U72_1_(ackWselect_b_1_, ackWselect_1_);
not #(1) U72_0_(ackWselect_b_0_, ackWselect_0_);
ffB #(1) I99(ackWinOverD, rclk, ackWinOver);
ffB #(1) I92(ackClear, rclk, hnl_184);
ffB #(1) I96(ackWinOver, rclk, ackClear);
ffB #(1) I71(hnl_193, rclk, hnl_190);
ffB #(1) I70(hnl_190, rclk, hnl_191);
ffB #(1) I69(hnl_191, rclk, evalD);
ffB #(1) I68(evalD, rclk, eval);
mux41 #(1) I48(hnl_192, hnl_193, hnl_190, hnl_191, evalD, ackSel_2_, ackSel_1_, ackSel_0_, ackSel_3_);
mux41 #(1) I39(hnl_185, hnl_194, hnl_195, hnl_196, hnl_197, ackWsel_0_, ackWsel_3_, ackWsel_2_, ackWsel_1_);
mux41 #(1) I38(hnl_186, hnl_198, hnl_199, hnl_193, hnl_190, ackWsel_0_, ackWsel_3_, ackWsel_2_, ackWsel_1_);
ffA I33(hnl_198, hnl_199, rclk);
ffA I94(hnl_187, ackWinOver, rclk);
ffA I37(hnl_194, hnl_195, rclk);
ffA I36(hnl_195, hnl_196, rclk);
ffA I35(hnl_196, hnl_197, rclk);
ffA I34(hnl_197, hnl_198, rclk);
ffA I32(hnl_199, hnl_193, rclk);
nor #(1) U50_0_(ackSel_3_, ackSelect_b_0_, ackSelect_b_1_);
nor #(1) U50_1_(ackSel_2_, ackSelect_0_, ackSelect_b_1_);
nor #(1) U50_2_(ackSel_1_, ackSelect_b_0_, ackSelect_1_);
nor #(1) U50_3_(ackSel_0_, ackSelect_0_, ackSelect_1_);
not #(1) U65(reset_b, reset);
endmodule

module mux71x (Y, A, B, C, D, E, F, G, SelA, SelB, SelC, SelD, SelE, SelF, SelG);
output Y;
input A, B, C, D, E, F, G, SelA, SelB, SelC, SelD, SelE, SelF, SelG;
supply1 vdd;
supply0 gnd;
not #(1) U13(hnl_200, hnl_201);
not #(1) U42(Y, hnl_200);
not (weak0,weak1) #(1) I41(hnl_201, hnl_200);
tranif1 N27(hnl_201, B, SelB);
tranif1 N31(hnl_201, F, SelF);
tranif1 U1(hnl_201, A, SelA);
tranif1 N28(hnl_201, C, SelC);
tranif1 N38(hnl_201, G, SelG);
tranif1 N30(hnl_201, E, SelE);
tranif1 N29(hnl_201, D, SelD);
endmodule

module u5NSWErg (NSWE, selectOdd, loadNSWE, pd2, pd3, rclk, unloadNSWE);
output NSWE, selectOdd;
input loadNSWE, pd2, pd3, rclk, unloadNSWE;
supply1 vdd;
supply0 gnd;
oai21A U106(hnl_202, hnl_203, loadNSWE, rclk);
ffBarB #(1) I103(hnl_203, rclk, hnl_204);
nor #(1) U101(hnl_204, unloadNSWE, loadNSWE);
not #(1) U95(slowGatedNSWEclk, hnl_205);
nand #(1) U93(hnl_206, vdd, vdd, hnl_207);
not #(1) U91(gatedNSWEclk, hnl_207);
not #(1) U86(clkSelectEven, hnl_202);
not #(1) U107(hnl_208, hnl_209);
not #(1) U98(hnl_210, loadNSWE);
not #(1) U94(hnl_205, hnl_206);
nand #(1) U84(hnl_207, selectOdd, rclk, hnl_203);
ffA I90(hnl_211, pd3, slowGatedNSWEclk);
ffA I89(hnl_212, pd2, slowGatedNSWEclk);
ffB #(1) I99(NSWE, rclk, hnl_208);
ffNcA I104(selectOdd, hnl_213, clkSelectEven);
ffNcA I71(hnl_193, hnl_211, slowGatedNSWEclk);
ffNcA I70(hnl_190, hnl_193, slowGatedNSWEclk);
ffNcA I69(oddNSWE_b, hnl_190, gatedNSWEclk);
ffNcA I68(evenNSWE_b, hnl_214, gatedNSWEclk);
ffNcA I67(hnl_214, hnl_215, slowGatedNSWEclk);
ffNcA I66(hnl_215, hnl_212, slowGatedNSWEclk);
nand #(1) U105(hnl_213, hnl_210, selectOdd);
mux21 #(1) I43(hnl_209, evenNSWE_b, oddNSWE_b, selectOdd);
endmodule

module nandpd2 (Y, A, B);
inout Y;
input A, B;
supply1 vdd;
supply0 gnd;
tranif1 N2(hnl_105, gnd, B);
tranif1 N1(Y, hnl_105, A);
endmodule

module u5DARbit (DAR, loadDAR, reset_b, setDAR, testBD);
output DAR;
input loadDAR, reset_b, setDAR, testBD;
supply1 vdd;
supply0 gnd;
not #(1) U36(DAR, hnl_216);
not #(1) U35(hnl_87, hnl_217);
not #(1) U34(hnl_218, loadDAR);
not #(1) U33(hnl_149, testBD);
mux21 #(1) I32(hnl_217, hnl_216, hnl_149, setDAR);
ffBNcRA I28(hnl_216, hnl_218, hnl_87, reset_b);
endmodule

module u5id (debug_1_, debug_0_, dataZA2, dataZA3, idhit, A2_b, A3_b, dataInA2, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID);
output debug_1_, debug_0_;
inout dataZA2, dataZA3, idhit;
input A2_b, A3_b, dataInA2, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID;
supply1 vdd;
supply0 gnd;
latRA #(1) I53(debug_1_, dataInA3, writeDeviceID, reset_b);
latRA #(1) I21(debug_0_, dataInA2, writeDeviceID, reset_b);
xnandpc2 U51(idhit, debug_1_, evalId, A3_b);
xnandpc2 U50(idhit, debug_0_, evalId, A2_b);
nandpd2 U48(dataZA3, debug_1_, readDeviceId);
nandpd2 U42(dataZA2, debug_0_, readDeviceId);
endmodule

module u5Rhit (bank0RowAddr, bank1RowAddr, dataZbank0, dataZbank1, rowHitLeft, rowHitRight, BSEL, evalRowHit, packetRowAddr, packetRowAddr_b, readR_10_, reset_b, updateRowAddr);
output bank0RowAddr, bank1RowAddr;
inout dataZbank0, dataZbank1, rowHitLeft, rowHitRight;
input BSEL, evalRowHit, packetRowAddr, packetRowAddr_b, readR_10_, reset_b, updateRowAddr;
supply1 vdd;
supply0 gnd;
latRB #(1) I55(bank1RowAddr, n2, updateRowAddr, reset_b);
latRB #(1) I54(bank0RowAddr, n1, updateRowAddr, reset_b);
not #(1) U50(hnl_219, BSEL);
xnandpc2 U42(rowHitRight, bank1RowAddr, evalRowHit, packetRowAddr_b);
xnandpc2 U41(rowHitLeft, bank0RowAddr, evalRowHit, packetRowAddr_b);
mux21s #(1) I49(n2, bank1RowAddr, packetRowAddr, BSEL, hnl_219);
mux21s #(1) I3(n1, packetRowAddr, bank0RowAddr, BSEL, hnl_219);
nandpd2 U45(dataZbank1, bank1RowAddr, readR_10_);
nandpd2 U44(dataZbank0, bank0RowAddr, readR_10_);
endmodule

module u5RASadr (adrSelReg, n1_b, packetRowaddr_b, dataZ01, dataIn01, pd12, pd23, readR_8_, reset_b, writeA0123, writeR_8_);
output adrSelReg, n1_b, packetRowaddr_b;
inout dataZ01;
input dataIn01, pd12, pd23, readR_8_, reset_b, writeA0123, writeR_8_;
supply1 vdd;
supply0 gnd;
nandpd2 U12(dataZ01, adrSelReg, readR_8_);
latRA #(1) I9(adrSelReg, dataIn01, writeR_8_, reset_b);
hitSel I26(packetRowaddr_b, n1_b, pd23, pd12, adrSelReg, writeA0123);
endmodule

module u5Rfsh1 (RefCount, RefLoad, cout_b, dataZ01, dataZ23, rfshEqualsZero, cin_b, cnt, dataIn01, dataIn23, evalRfshCount, readR_4_, reset, reset_b, writeR_4_);
output RefCount, RefLoad, cout_b;
inout dataZ01, dataZ23, rfshEqualsZero;
input cin_b, cnt, dataIn01, dataIn23, evalRfshCount, readR_4_, reset, reset_b, writeR_4_;
supply1 vdd;
supply0 gnd;
latSB #(1) I59(RefLoad, dataIn23, writeR_4_, reset);
countupx I58(cout_b, RefCount, cin_b, rfshEqualsZero, writeR_4_, reset_b, dataIn01, cnt, RefLoad);
not #(1) U48(hnl_220, RefCount);
nandpd2 U42(dataZ23, RefLoad, readR_4_);
nandpd2 U38(dataZ01, RefCount, readR_4_);
nandpc2 U36(rfshEqualsZero, hnl_220, evalRfshCount);
endmodule

module u5RfshRw (carryOut, rfshRASaddr, dataZ, carryIn, dataIn, incRfshRow_b, readR_5_, writeR_5_);
output carryOut, rfshRASaddr;
inout dataZ;
input carryIn, dataIn, incRfshRow_b, readR_5_, writeR_5_;
supply1 vdd;
supply0 gnd;
not #(1) I51(rfshRASaddr, hnl_221);
countup I47(carryOut, hnl_221, incRfshRow_b, carryIn, writeR_5_, dataIn);
nandpd2 U130(dataZ, rfshRASaddr, readR_5_);
endmodule

module u5CASdy1 (readDelay, writeDelay, dataZ1, dataZ3, dataIn1, dataIn3, readR_2_, reset_b, writeR_2_);
output readDelay, writeDelay;
inout dataZ1, dataZ3;
input dataIn1, dataIn3, readR_2_, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
latRB #(1) hnl_222(readDelay, dataIn1, writeR_2_, reset_b);
latRB #(1) hnl_223(writeDelay, dataIn3, writeR_2_, reset_b);
nandpd2 U1076(dataZ1, readDelay, readR_2_);
nandpd2 U1077(dataZ3, writeDelay, readR_2_);
endmodule

module pdnull (Y, A);
inout Y;
input A;
supply1 vdd;
supply0 gnd;
tranif1 N1(Y, gnd, gnd);
endmodule

module nandpd1 (Y, A);
inout Y;
input A;
supply1 vdd;
supply0 gnd;
tranif1 N1(Y, gnd, A);
endmodule

module u5MscR4 (ackDelay, ackWinDelay, dataZ0, dataZ1, dataZ2, dataZ3, autoSkip, dataIn0, dataIn2, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_2_);
output ackDelay, ackWinDelay;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input autoSkip, dataIn0, dataIn2, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
pdnull U157(dataZ1, readR_9_);
pdnull U156(dataZ0, readR_9_);
latRB #(1) I132(ackDelay, dataIn2, writeR_2_, reset_b);
latRB #(1) I127(ackWinDelay, dataIn0, writeR_2_, reset_b);
nandpd1 U140(dataZ3, readR_0_);
nandpd1 U139(dataZ0, readR_0_);
nandpd1 U125(dataZ1, readR_0_);
nandpd2 U158(dataZ0, autoSkip, readR_3_);
nandpd2 U133(dataZ2, ackDelay, readR_2_);
nandpd2 U128(dataZ0, ackWinDelay, readR_2_);
endmodule

module u5bit4 (ADR_3_, CASctCy45, Count_2_, DAR_3_, NSWE_4_, RAScountLSB_b, RfshCntCary45, RfshRwCy45, XferCntBorw45, ackDelay_1_, ackWinDelay_1_, partialId_b_2_, pd2_4_, readDelay_1_, skip,
writeDelay_1_, xcnt_b_0_, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, idHitB, rfshEqualsZero, rowHitLeftB, rowHitRightB, CASctCy34, DAmode_b, DLLByPassMode_b, NSAdr_3_, RASaddrEnable, RASldCount,
RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary34, RfshRwCy34, autoSkip, autoSkipEn, dataIn0_4_, dataIn1_4_, dataIn2_4_, dataIn3_4_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr,
driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_1_, pd0_4_, pd1_4_, pd2_5_, pd3_4_, rclk, readR_10_, readR_9_, readR_8_,
readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, skipBit, testBD_5_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x,
writeR_8_, writeR_6_, writeR_5_, writeR_4_, writeR_2_, writeR_1_);
output ADR_3_, CASctCy45, Count_2_, DAR_3_, NSWE_4_, RAScountLSB_b, RfshCntCary45, RfshRwCy45, XferCntBorw45, ackDelay_1_, ackWinDelay_1_, partialId_b_2_, pd2_4_, readDelay_1_, skip, writeDelay_1_,
xcnt_b_0_;
inout dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, idHitB, rfshEqualsZero, rowHitLeftB, rowHitRightB;
input CASctCy34, DAmode_b, DLLByPassMode_b, NSAdr_3_, RASaddrEnable, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary34, RfshRwCy34, autoSkip, autoSkipEn, dataIn0_4_, dataIn1_4_,
dataIn2_4_, dataIn3_4_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL,
partialId_b_1_, pd0_4_, pd1_4_, pd2_5_, pd3_4_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR,
skipBit, testBD_5_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_6_, writeR_5_, writeR_4_, writeR_2_, writeR_1_;
supply1 vdd;
supply0 gnd;
nand #(1) U588(hnl_224, hnl_225, DLLByPassMode_b);
latSRB rowExpRest0(rowExpRest_0_, dataIn3_4_, writeR_6_, vdd, reset);
latSRB rowImpRest0(rowImpRest_0_, dataIn2_4_, writeR_6_, vdd, reset);
latSRB rowAcc0(rowAcc_0_, dataIn1_4_, writeR_6_, reset_b, gnd);
latSRB rowPre0(rowPre_0_, dataIn0_4_, writeR_6_, reset_b, gnd);
ltxBarB Count2(Count_b_2_, writeA45, pd2_4_);
ltxBarB Addr31(Addr_31_, writeA0123, pd3_4_);
latBNcA I582(packetRowAddr_3_, RASaddrEnable, packetRowAddr_b_3_);
mux71x AdrMUX3(ADR_3_, ColAdr_3_, NSAdr_3_, packetRowAddr_3_, rfshRowAddr_3_, bank0RowAddr_3_, bank1RowAddr_3_, testBD_5_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_226, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg4(NSWE_4_, selectEven_4_, loadNSWE, pd2_4_, pd3_4_, rclk, unloadNSWE);
not #(1) I576(DAmode, DAmode_b);
nor #(1) I572(hnl_226, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U569(skip, hnl_224);
mux21 #(1) I567(hnl_225, skipBit, autoSkip, autoSkipEn);
not #(1) U562(RAScountLSB_b, RAScountLSB);
not #(1) U561(Count_2_, Count_b_2_);
mux41 #(1) I560(cnt0, rowPre_0_, rowAcc_0_, rowImpRest_0_, rowExpRest_0_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
latBarA RASct0(RAScountLSB, RASldCount, cnt0);
nandpd2 U559(dataZ3_4_, rowExpRest_0_, readR_6_);
nandpd2 U551(dataZ0_4_, rowPre_0_, readR_6_);
nandpd2 U541(dataZ1_4_, rowAcc_0_, readR_6_);
nandpd2 U539(dataZ2_4_, rowImpRest_0_, readR_6_);
u5DARbit DARbit3(DAR_3_, loadDAR, DAmode, setDAR, testBD_5_);
countdn Count3(XferCntBorw45, xcnt_b_0_, decXferCnt_b, gnd, writeA45, pd3_4_);
countup Col_3_(CASctCy45, net1444, incColAdr_b, CASctCy34, writeA0123x, pd0_4_);
u5id Id22_31(id_31_, id_22_, dataZ0_4_, dataZ2_4_, idHitB, partialId_b_1_, Addr_31_, dataIn0_4_, dataIn2_4_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_3_(bank0RowAddr_3_, bank1RowAddr_3_, dataZ0_4_, dataZ2_4_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_3_, packetRowAddr_b_3_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr3(adrSelReg_3_, partialId_b_2_, packetRowAddr_b_3_, dataZ0_4_, dataIn0_4_, pd1_4_, pd2_5_, readR_8_, reset_b, writeA0123, writeR_8_);
u5Rfsh1 RefCnt4(RefCount_4_, RefLoad_4_, RfshCntCary45, dataZ0_4_, dataZ2_4_, rfshEqualsZero, RfshCntCary34, incRfshInterval, dataIn0_4_, dataIn2_4_, evalRfshCount, readR_4_, reset, reset_b,
writeR_4_);
u5RfshRw RfshRw3(RfshRwCy45, rfshRowAddr_3_, dataZ0_4_, RfshRwCy34, dataIn0_4_, incRfshRow_b, readR_5_, writeR_5_);
u5CASdy1 CASdy1(readDelay_1_, writeDelay_1_, dataZ1_4_, dataZ3_4_, dataIn1_4_, dataIn3_4_, readR_2_, reset_b, writeR_2_);
u5MscR4 MscR4(ackDelay_1_, ackWinDelay_1_, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, autoSkip, dataIn0_4_, dataIn2_4_, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_2_);
not #(1) U498(ColAdr_3_, net1444);
not #(1) U493(reset_b, reset);
endmodule

module spdt1 (s1, s2);
inout s1;
input s2;
supply1 vdd;
supply0 gnd;
endmodule

module u5CAScyc (CAS, CASstate1_b, CASstate3_buf, CASwrite, LoadShiftRegister_b, WML, WRITE, decXferCnt_b, earlyREQinhibit, firstCycWE_b, incColAdr_b, loadLast, loadNSAdr, preloadNSWE, selRegData,
startNSAdr_b, trueCASstate1_b, unloadNSWE, writeD0123, writeD4567, writeSenseAmpPipe, CASenable, DAWD0123, DAWD4567, DAmode_b, NSOp, REQinhibiten, TestCAS, TestRASB, TestWML, TestWRITE, WPBNP,
abortOperation_b, earlyDone, inhLoadLast_b, localREQ, rclk, regOp, reset, standby, startCycle_b, virtuallyDone, writeA45, writeMaskedNSOp_b, writeOp_b);
output CAS, CASstate1_b, CASstate3_buf, CASwrite, LoadShiftRegister_b, WML, WRITE, decXferCnt_b, earlyREQinhibit, firstCycWE_b, incColAdr_b, loadLast, loadNSAdr, preloadNSWE, selRegData,
startNSAdr_b, trueCASstate1_b, unloadNSWE, writeD0123, writeD4567, writeSenseAmpPipe;
input CASenable, DAWD0123, DAWD4567, DAmode_b, NSOp, REQinhibiten, TestCAS, TestRASB, TestWML, TestWRITE, WPBNP, abortOperation_b, earlyDone, inhLoadLast_b, localREQ, rclk, regOp, reset, standby,
startCycle_b, virtuallyDone, writeA45, writeMaskedNSOp_b, writeOp_b;
supply1 vdd;
supply0 gnd;
latRB #(1) I691(latchedSelReg, regOp, firstCycle, hnl_227);
ffD I856(decXferCnt_b, trueCASstate1_b, rclk);
nand #(0) U853(hnl_228, CASenable, hnl_229, hnl_230, REQinhibiten);
ffBNcD I844(preloadNSWE, rclk, hnl_231);
ffC #(1) I850(loadLast, rclk, preLoadLast);
ffC #(1) I842(hnl_232, rclk, hnl_233);
latBarB I835(hnl_234, rclk, hnl_235);
ffBarA #(1) I831(hnl_236, rclk, hnl_237);
aoi21A #(1) U832(hnl_237, WPBNP_b, loadMask, firstCycleD);
aoi21A #(1) U830(hnl_238, hnl_239, WPBNP, hnl_236);
ffBarB #(1) I807(preinhibitCount, rclk, hnl_238);
ffBarB #(1) I816(hnl_240, rclk, preLoadNSaddr);
not #(1) I817(CASstate3_buf, CASstate3_b);
nand #(1) I809(hnl_229, firstCycle_b, CASstate2);
invEE U860(writeD0123, writeD0123_b);
invEE U841(incColAdr_b, hnl_232);
invEE U797(writeD4567, hnl_234);
latBarSB #(1) I790(hnl_241, preWriteSenseAmpPipe_b, rclk, hnl_242);
oai21A U734(preCASstate1, CASenable_b, hnl_243, hnl_244);
not #(1) U595(writeMaskedNSOp, writeMaskedNSOp_b);
not #(1) U695(writeOp, writeOp_b);
not #(1) U702(LoadShiftRegister_b, preLoadSR);
not #(1) U752(unloadNSWE, hnl_245);
latB I854(preCASwrite_b, hnl_246, rclk);
spdt1 I686(CASstate2_b, CASstate1_b);
spdt1 I684(CASstate3, CASstate2);
ffBarA #(1) I829(hnl_239, rclk, NScnt_0_);
ffBarA #(1) I784(preFirstCycWE, rclk, inhibitFirstWriteCycle_b);
ffBarA #(1) I683(hnl_247, rclk, preWriteSenseAmpPipe_b);
ffBarC #(1) I776(CASstate4, rclk, CASstate3_b);
ffQBC I529(firstCycle_b, firstCycle, earlyFC_b, rclk);
ffQBC I716(CASstate2_b, CASstate2, hnl_248, rclk);
ffQBC I655(CASstate1, CASstate1_b, preCASstate1, rclk);
ffBarB #(1) I705(firstWPBNPcycle_b, rclk, hnl_249);
nor #(1) U768(hnl_233, preIncColAdr_b, WPBNPinh);
nor #(1) U737(hnl_250, hnl_251, CASstate1);
nor #(1) U731(hnl_252, hnl_253, hnl_254);
nor #(1) U638(resetNScnt_b, resetCnt, firstCycle);
invEEbuf U722(writeSenseAmpPipe, hnl_255);
invEEbuf U643(selRegData, hnl_256);
invEEbuf U637(WML, WML_b);
invEEbuf U636(CAS, CAS_b);
ffBNcA I653(resetCnt, CASstate2_b, cnt8_b);
ffBNcA I624(hnl_257, CASstate0or4_b, hnl_258);
aoi21A #(1) U864(earlyFC_b, firstCycle, CASstate2_b, writeA45);
aoi21A #(1) U847(hnl_259, startCycle_b, CASstate4_b, inhLoadLast);
aoi21A #(1) U729(hnl_253, WPBNP_b, writeMaskedNSOp_b, inhibitCount_b);
aoi21A #(1) U760(loadNSWEmask, firstCycle_b, loadMask_b, writeMaskedNSOp_b);
ffA I756(maskedNSHoldOff, loadNSWEmask, rclk);
nor #(1) U524(preLoadSR, CASstate2_b, DAmode, writeOp);
nor #(1) U780(hnl_260, writeOp_b, regOp, DAmode);
nor #(1) U767(hnl_261, earlyDone, NSOp, CASstate2_b);
nor #(1) U669(DAinhibit, hnl_262, TestRASB, DAmode_b);
nor #(1) U603(maskedNSclkEn, CASstate3_b, writeMaskedNSOp_b, maskedNSHoldOff);
nor #(1) U567(hnl_258, NScnt_2_, NScnt_1_, NScnt_0_);
oai21A U696(hnl_249, hnl_161, firstWPBNPcycle_b, hnl_263);
not #(1) U852(earlyREQinhibit, hnl_228);
not #(1) U753(hnl_245, maskedNSclkEn);
not #(1) U746(CASstate0or4, CASstate0or4_b);
not #(1) U700(hnl_263, writeA45);
not #(1) U693(regOp_b, regOp);
not #(1) U660(WPBNP_b, WPBNP);
not #(1) U521(reset_b, reset);
nor #(1) I791(hnl_255, hnl_241, hnl_247);
nor #(1) I745(CASstate0or4_b, CASstate0, CASstate4);
nor #(1) I701(firstCycWE_b, preFirstCycWE, hnl_264);
ffQBB I834(loadMask_b, loadMask, preloadMask_b, rclk);
ffQBB I808(inhibitCount, inhibitCount_b, preinhibitCount, rclk);
ffQBB I765(firstCycleD_b, firstCycleD, firstCycle_b, rclk);
ffQBB I739(CASstate0_b, CASstate0, startCycle_b, rclk);
ffQBB I495(CASstate3, CASstate3_b, CASstate2, rclk);
ffBNcRA I486(NScnt_2_, NScnt_1_, NScnt_2_, resetNScnt_b);
ffBNcRA I485(NScnt_1_, NScnt_0_, NScnt_1_, resetNScnt_b);
ffBNcRA I484(NScnt_0_, CASstate0or4_b, NScnt_0_, resetNScnt_b);
not #(1) I662(loadNSAdr, hnl_240);
not #(1) U471(WRITE, write_b);
mux21 #(1) I838(preLoadLast, hnl_259, hnl_265, writeOp);
mux21 #(1) I824(hnl_254, hnl_266, regOp, firstCycleD_b);
mux21 #(1) I810(hnl_230, preinhibitCount, inhibitCount, writeMaskedNSOp);
mux21 #(1) I743(hnl_267, CASstate0_b, startCycle_b, writeOp_b);
mux21 #(1) I740(hnl_243, CASstate0_b, startCycle_b, writeOp_b);
nand #(1) U815(hnl_248, CASstate1, reset_b, abortOperation_b);
nand #(1) U774(hnl_268, CASstate0or4, writeOp, hnl_269);
nand #(1) U773(hnl_270, writeOp, CASstate2, hnl_269);
nand #(1) U772(preWML_b, CASWMLen, inhibit1stMemWriteCyc_b, WPBNPinh);
nand #(1) U659(cnt8_b, hnl_258, WPBNP_b, hnl_257);
nand #(1) U497(hnl_256, latchedSelReg, hnl_227, DAmode_b);
nand #(1) U826(trueCASstate1_b, inhibitFirstWriteCycle_b, CASstate1, hnl_271);
nand #(1) U738(startNSAdr_b, CASstate1, NSOp, inhibitFirstWriteCycle_b);
nand #(1) U420(preCAS_b, CASWMLen, hnl_252, CASenable);
nor #(1) I771(WPBNPinh, inhibitCount_b, WPBNP_b);
nor #(1) I411(CASwrite, CAS_b, preCASwrite_b);
not #(1) U490(write_b, hnl_272);
nor #(1) U849(hnl_265, inhLoadLast, CASstate1_b);
nor #(1) U837(hnl_242, hnl_273, rclk);
nor #(1) U777(hnl_274, inhibitCount_b, writeMaskedNSOp_b);
nor #(1) U770(preLoadNSaddr, NSOp_b, CASstate1_b);
nor #(1) U706(hnl_264, WPBNP_b, firstWPBNPcycle_b);
nor #(1) U703(hnl_161, firstCycleD, CASstate3_b);
not #(1) U735(hnl_251, hnl_244);
DAff I251(CAS_b, rclk, DAinhibit, preCAS_b, DAmode_b);
DAff I342(WML_b, rclk, TestWML, preWML_b, DAmode_b);
DAff I287(writeD0123_b, rclk, DAWD0123, hnl_268, DAmode_b);
DAff I263(preWriteD4567_b, rclk, DAWD4567, hnl_270, DAmode_b);
nand #(1) U822(hnl_266, regOp_b, writeOp_b);
nand #(1) U788(preWriteSenseAmpPipe_b, writeOp_b, CASstate3);
nand #(1) U775(hnl_269, regOp, inhibitFirstWriteCycle_b);
nand #(1) U720(hnl_246, localREQ, hnl_260);
nand #(1) U690(stopCAS_b, inhibitFirstWriteCycle_b, virtuallyDone);
nand #(1) U689(hnl_244, CASstate4, stopCAS_b);
nand #(1) U645(preIncColAdr_b, hnl_261, inhibit1stMemWriteCyc_b);
not #(1) U867(hnl_227, standby);
not #(1) U848(CASstate4_b, CASstate4);
not #(1) U846(inhLoadLast, inhLoadLast_b);
not #(1) U836(hnl_273, DAinhibit);
not #(1) U827(hnl_271, hnl_274);
not #(1) U823(inhibit1stMemWriteCyc_b, hnl_254);
not #(1) U803(hnl_235, preWriteD4567_b);
not #(1) U781(DAmode, DAmode_b);
not #(1) U736(CASenable_b, CASenable);
not #(1) U670(hnl_262, TestCAS);
not #(1) U563(NSOp_b, NSOp);
not #(1) U496(Wn1, TestWRITE);
nand #(1) U863(hnl_231, preloadMask_b, earlyFC_b);
nand #(1) U733(CASWMLen, hnl_267, hnl_250);
nand #(1) U336(hnl_272, preCASwrite_b, Wn1);
nand #(1) U865(preloadMask_b, resetCnt, writeMaskedNSOp);
nand #(1) U449(inhibitFirstWriteCycle_b, firstCycleD, writeOp);
endmodule

module u5RegDec (framePulseX, readR_10_, readR_9_, readR_8_, readR_7_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_,
writeR_3_, writeR_2_, writeR_1_, ADR_6_, ADR_2_, ADR_1_, ADR_0_, Addr_2_, PDMD, framePulse_b, reset, selRegData, writeD4567);
output framePulseX, readR_10_, readR_9_, readR_8_, readR_7_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_,
writeR_2_, writeR_1_;
input ADR_6_, ADR_2_, ADR_1_, ADR_0_, Addr_2_, PDMD, framePulse_b, reset, selRegData, writeD4567;
supply1 vdd;
supply0 gnd;
nand #(1) U49(framePulseX, framePulse_b, hnl_275);
nand #(1) U44(hnl_276, hnl_277, selRegData);
not #(1) U43_0_(ADRB_1_, ADR_b_1_);
not #(1) U43_1_(ADRB_0_, ADR_b_0_);
not #(1) U52(hnl_275, reset);
not #(1) U45(hnl_277, PDMD);
not #(1) U35(hnl_87, writeD4567);
not #(1) U42(selRegDataB, hnl_276);
not #(1) U36(writeD4567B, hnl_87);
not #(1) U34(Addr_b_2_, Addr_2_);
not #(1) U32_0_(ADR_b_2_, ADR_2_);
not #(1) U32_1_(ADR_b_1_, ADR_1_);
not #(1) U32_2_(ADR_b_0_, ADR_0_);
not #(1) U33_0_(readR_10_, net46_0_);
not #(1) U33_1_(readR_9_, net46_1_);
not #(1) U33_2_(readR_8_, net46_2_);
not #(1) U33_3_(readR_7_, net46_3_);
not #(1) U33_4_(readR_6_, net46_4_);
not #(1) U33_5_(readR_5_, net46_5_);
not #(1) U33_6_(readR_4_, net46_6_);
not #(1) U33_7_(readR_3_, net46_7_);
not #(1) U33_8_(readR_2_, net46_8_);
not #(1) U33_9_(readR_1_, net46_9_);
not #(1) U33_10_(readR_0_, net46_10_);
not #(1) U30_0_(writeR_8_, net45_0_);
not #(1) U30_1_(writeR_7_, net45_1_);
not #(1) U30_2_(writeR_6_, net45_2_);
not #(1) U30_3_(writeR_5_, net45_3_);
not #(1) U30_4_(writeR_4_, net45_4_);
not #(1) U30_5_(writeR_3_, net45_5_);
not #(1) U30_6_(writeR_2_, net45_6_);
not #(1) U30_7_(writeR_1_, net45_7_);
nand #(0) U4_0_(net44_0_, ADR_6_, ADR_b_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_1_(net44_1_, Addr_2_, ADR_b_0_, ADR_b_1_, ADR_2_);
nand #(0) U4_2_(net44_2_, Addr_b_2_, ADR_b_0_, ADR_b_1_, ADR_2_);
nand #(0) U4_3_(net44_3_, Addr_2_, ADRB_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_4_(net44_4_, Addr_b_2_, ADRB_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_5_(net44_5_, Addr_2_, ADR_b_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_6_(net44_6_, Addr_b_2_, ADR_b_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_7_(net44_7_, Addr_2_, ADRB_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_8_(net44_8_, Addr_b_2_, ADRB_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_9_(net44_9_, lsbx, ADR_b_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_10_(net44_10_, lsbx_b, ADR_b_0_, ADR_b_1_, ADR_b_2_);
nor #(1) U27(lsbx, ADR_6_, Addr_b_2_);
nor #(1) U28(lsbx_b, ADR_6_, Addr_2_);
not #(1) U16_0_(sel_10_, net44_0_);
not #(1) U16_1_(sel_9_, net44_1_);
not #(1) U16_2_(sel_8_, net44_2_);
not #(1) U16_3_(sel_7_, net44_3_);
not #(1) U16_4_(sel_6_, net44_4_);
not #(1) U16_5_(sel_5_, net44_5_);
not #(1) U16_6_(sel_4_, net44_6_);
not #(1) U16_7_(sel_3_, net44_7_);
not #(1) U16_8_(sel_2_, net44_8_);
not #(1) U16_9_(sel_1_, net44_9_);
not #(1) U16_10_(sel_0_, net44_10_);
nand #(1) U218_0_(net45_0_, writeD4567B, readR_8_);
nand #(1) U218_1_(net45_1_, writeD4567B, readR_7_);
nand #(1) U218_2_(net45_2_, writeD4567B, readR_6_);
nand #(1) U218_3_(net45_3_, writeD4567B, readR_5_);
nand #(1) U218_4_(net45_4_, writeD4567B, readR_4_);
nand #(1) U218_5_(net45_5_, writeD4567B, readR_3_);
nand #(1) U218_6_(net45_6_, writeD4567B, readR_2_);
nand #(1) U218_7_(net45_7_, writeD4567B, readR_1_);
nand #(1) U8_0_(net46_0_, sel_10_, selRegDataB);
nand #(1) U8_1_(net46_1_, sel_9_, selRegDataB);
nand #(1) U8_2_(net46_2_, sel_8_, selRegDataB);
nand #(1) U8_3_(net46_3_, sel_7_, selRegDataB);
nand #(1) U8_4_(net46_4_, sel_6_, selRegDataB);
nand #(1) U8_5_(net46_5_, sel_5_, selRegDataB);
nand #(1) U8_6_(net46_6_, sel_4_, selRegDataB);
nand #(1) U8_7_(net46_7_, sel_3_, selRegDataB);
nand #(1) U8_8_(net46_8_, sel_2_, selRegDataB);
nand #(1) U8_9_(net46_9_, sel_1_, selRegDataB);
nand #(1) U8_10_(net46_10_, sel_0_, selRegDataB);
endmodule

module u5clkCtl (bcastWrite, runtclk, DLLByPassMode_b, bcastWriteA, bcastWriteB, idHitA, idHitB, latchAbort_b, rclk, reset, tclkDisable_b, writeA0123);
output bcastWrite, runtclk;
input DLLByPassMode_b, bcastWriteA, bcastWriteB, idHitA, idHitB, latchAbort_b, rclk, reset, tclkDisable_b, writeA0123;
supply1 vdd;
supply0 gnd;
not #(1) U129(bcastWrite, hnl_278);
nand #(1) U128(hnl_278, bcastWriteA, bcastWriteB);
nand #(1) U121(hnl_279, latchAbort_b, tclkDisable_b);
ffA I117(hnl_27, writeA0123, rclk);
srff I116(enableTclk_b, hnl_280, hnl_281);
nand #(1) U115(hnl_281, hnl_282, openTclkEnLatch);
nor #(1) U104(forceRuntclk_b, hnl_205, reset);
ffB #(1) I101(openTclkEnLatch, rclk, hnl_27);
nand #(1) I99(runtclk, forceRuntclk_b, enableTclk_b);
not #(1) U113(hnl_282, hnl_283);
not #(1) U94(hnl_205, DLLByPassMode_b);
aoi21A #(1) U114(hnl_280, openTclkEnLatch, hnl_283, hnl_279);
aoi21A #(1) U77(hnl_283, idHitA, idHitB, bcastWrite);
endmodule

module aoi22A (Y, A1, A2, B1, B2);
output Y;
input A1, A2, B1, B2;
supply1 vdd;
supply0 gnd;
tranif0 P4(hnl_284, vdd, B2);
tranif0 P3(hnl_284, vdd, B1);
tranif0 P2(Y, hnl_284, A2);
tranif0 P1(Y, hnl_284, A1);
tranif1 N3(Y, hnl_285, B1);
tranif1 N1(Y, hnl_105, A1);
tranif1 N4(hnl_285, gnd, B2);
tranif1 N2(hnl_105, gnd, A2);
endmodule

module u5HitLog (CASenable, RASkill, RASstate4, idHitRowMiss, idMissReturn_b, latchAbort_b, nack, RASidle_b, abortOperation_b, ackClear, bcastWrite, busyError_b, eval, idHitA, idHitB, packetBSEL,
packetBSELx, powerDownMode, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, updateRowAddr, writeA45, writeA45_b, writeA0123);
output CASenable, RASkill, RASstate4, idHitRowMiss, idMissReturn_b, latchAbort_b, nack;
input RASidle_b, abortOperation_b, ackClear, bcastWrite, busyError_b, eval, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB,
updateRowAddr, writeA45, writeA45_b, writeA0123;
supply1 vdd;
supply0 gnd;
nand #(1) U472(hnl_286, idHitA, idHitB, rowMiss);
nor #(1) U471(hnl_287, writeA45_b, regOp, RASidle_b);
ffC #(1) I470(RASstate4, rclk, hnl_287);
latB I435(packetRowHit_b, rowMiss, writeA45);
aoi22A U469(rowMiss, row0hitA, row0hitB, row1hitA, row1hitB);
ffB #(1) I463(preCycState4, rclk, writeA45);
latSB #(1) I460(latchAbort_b, abortOperation_b, preCycState4, hnl_288);
nand #(1) U458(RASkill, hnl_289, latchAbort_b, nackNoAction_b);
ffA I439(ackClearD, ackClear, rclk);
latBarB I434(packetIdHit, writeA45, idHit_b);
not #(1) U443(hnl_288, hnl_290);
nor #(1) U420(CASenable_b, bcastWrite, hnl_291, hnl_292);
aoi21A #(1) U412(hnl_293, nackNoAction_b, hnl_294, writeA0123);
ffBarA #(1) I413(nackNoAction_b, rclk, hnl_293);
nor #(1) U426(hnl_292, packetRowHit_b, packetIdHit_b);
nor #(1) U425(hnl_291, regOp_b, packetIdHit_b);
nor #(1) U440(hnl_290, writeA0123, ackClearD);
nor #(1) U406(invalidate_b, powerDownMode, reset);
srff I405(row0valid_b, invalidate_b, hnl_295);
srff I404(row1valid_b, invalidate_b, hnl_296);
nand #(1) U476(hnl_297, idHitRowMiss, RASstate4);
nand #(1) U437(idHit_b, idHitA, idHitB);
nand #(1) U408(hnl_295, updateRowAddr, hnl_298);
nand #(1) U407(hnl_296, updateRowAddr, packetBSELx);
not #(1) U473(idHitRowMiss, hnl_286);
not #(1) U379(CASenable, CASenable_b);
latWA U374(idHitA, hnl_299);
latWA U373(idHitB, hnl_300);
latWA U372(row0hitA, hnl_301);
latWA U371(row1hitA, hnl_302);
latWA U370(row1hitB, hnl_303);
latWA U369(row0hitB, hnl_304);
nand #(1) I299(hnl_289, packetIdHit_b, bcastWrite_b);
nand #(1) U457(hnl_294, preCycState4, CASenable_b, hnl_297);
nand #(1) I261(CAS_OK, packetRowHit_b, regOp_b, bcastWrite_b);
nandpc2 U377(row0hitA, packetBSEL, eval);
nandpc2 U375(row1hitA, hnl_305, eval);
nandpc2 U359(row0hitA, row0valid_b, eval);
nandpc2 U352(row1hitA, row1valid_b, eval);
nand #(1) U301(idMissReturn_b, RASkill, ackClear, busyError_b);
not #(1) U450(regOp_b, regOp);
not #(1) U446(bcastWrite_b, bcastWrite);
not #(1) U418(hnl_305, packetBSEL);
not #(1) U350(hnl_298, packetBSELx);
nand #(1) U382(nack, busyError_b, CAS_OK);
not #(1) U422(packetIdHit_b, packetIdHit);
endmodule

module invFF (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) U9(Y, A);
endmodule

module u5PreCyc (REQ, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idle, localREQ, virtuallyDone, writeA45, prewriteA45, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b,
NSOp, PDMD, RASreturn_b, RASstate4, RefreshReturn_b, TestRASB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitRowMiss, idMissReturn_b, rclk, regOp, reset, reset_b, startNSAdr_b,
writeOp_b);
output REQ, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idle, localREQ, virtuallyDone, writeA45, prewriteA45, writeA0123, writeA0123x;
input AUXorPDcycle, AUXpending_b, DAmode_b, NSOp, PDMD, RASreturn_b, RASstate4, RefreshReturn_b, TestRASB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitRowMiss, idMissReturn_b, rclk,
regOp, reset, reset_b, startNSAdr_b, writeOp_b;
supply1 vdd;
supply0 gnd;
ffBarD I606(preevalR, rclk, localframePulse_b);
ffBarD I603(preevalL, rclk, localframePulse_b);
not #(1) U697(frameEnableX_b, frameEnableX);
not #(1) U692(state2x_b, state2x);
not #(1) U691(state2x, writeA0123x_b);
nand #(1) U684(hnl_306, idHitRowMiss, RASstate4);
aoi211A #(1) I681(clearDriveColAdr_b, idHitRowMiss, RASstate4, AUXorPDcycle, hnl_307);
nor #(1) U625(hnl_308, D2, hnl_309);
ffB #(1) I581(virtuallyDone, rclk, earlyDone);
aoi22A U675(hnl_310, hnl_308, writeOpD2_b, earlyDone, hnl_311);
nor #(1) I669(busy_b, hnl_312, hnl_313);
ffBNcD I654(prewriteA45, rclk, state2x);
ffBNcD I534(prewriteA0123, rclk, localframePulse);
ffBNcD I535(writeA0123x_b, rclk, hnl_314);
oai21A U699(hnl_165, frameEnableX_b, frameRaw_b, busyError_b);
oai21A U646(preDriveColAdr, hnl_315, hnl_176, regOp_b);
ffBarRA I642(preDriveNSAdr, rclk, hnl_316, hnl_317);
not #(1) U651(hnl_318, hnl_319);
not #(1) U645(preDriveNSAdr_b, preDriveNSAdr);
not #(1) U634(REQ_b, hnl_320);
nand #(0) U628(hnl_176, reset_b, hnl_306, hnl_310, goIdle_b);
ffRA I672(hnl_321, rclk, reset_b, hnl_165);
ffRA I631(hnl_319, rclk, clearDriveColAdr_b, preDriveColAdr);
not #(1) U649(hnl_307, hnl_316);
invEEbuf U566(REQ, REQ_b);
invFF U604(evalR, preevalR);
invFF U600(evalL, preevalL);
invFF U564(writeA0123, prewriteA0123);
invFF U563(writeA0123x, writeA0123x_b);
nand #(1) I489(hnl_58, idMissReturn_b, RASreturn_b, RefreshReturn_b);
invEE U652(driveColAdr, hnl_318);
invEE I498(writeA45, prewriteA45);
invEE U526(driveNSAdr, preDriveNSAdr_b);
ffQBB I574(D1, hnl_309, virtuallyDone, rclk);
ffQBB I666(hnl_312, idle, idleEarly_b, rclk);
ffQBB I639(goIdle, goIdle_b, hnl_58, rclk);
nand #(1) U693(localframePulse_b, hnl_322, frameEnableX);
nand #(1) U688(hnl_323, frameEnableX, AUXpending_b);
nand #(1) U673(busyError_b, hnl_321, prewriteA45);
DAff I492(hnl_320, rclk, hnl_324, hnl_325, DAmode_b);
ffA I576(D2, D1, rclk);
ffA I598(hnl_326, startNSAdr_b, rclk);
ffA I579(writeOpD2_b, hnl_327, rclk);
ffA I578(hnl_327, writeOp_b, rclk);
mux21 #(1) I477(idleEarly_b, hnl_328, hnl_329, busy_b);
nor #(1) U638(hnl_328, earlyDone, reset, goIdle);
nor #(1) U636(hnl_325, hnl_176, hnl_315, earlyREQinhibit);
oai21A U515(hnl_316, hnl_330, preDriveNSAdr, state2x_b);
not #(1) U445(localREQ, localREQ_b);
nor #(1) U695(localframePulse, frameRaw_b, frameEnableX_b);
nor #(1) U677(hnl_311, writeOpD2_b, virtuallyDone);
nor #(1) U633(earlyREQ, hnl_315, hnl_176);
nor #(1) U517(hnl_330, hnl_326, NSOp_b);
nor #(1) U536(hnl_314, frameRaw_b, hnl_323, idleEarly_b);
nor #(1) U643(hnl_317, localREQ_b, DAmode);
nor #(1) U637(hnl_329, reset, evalL);
nor #(1) U632(hnl_315, state2x, localREQ);
nor #(1) U493(hnl_111, TestRASB, PDMD);
not #(1) U687(hnl_313, AUXpending_b);
not #(1) U694(hnl_322, frameRaw_b);
not #(1) U647(regOp_b, regOp);
not #(1) U644(DAmode, DAmode_b);
not #(1) U640(hnl_324, hnl_111);
not #(1) U511(NSOp_b, NSOp);
ffBarB #(1) I629(localREQ_b, rclk, earlyREQ);
endmodule

module u5PreHit (CASenable, RASkill, RASstate4, REQ, bcastWrite, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idHitRowMiss, idle, latchAbort, latchAbort_b, localREQ, nack, runtclk,
virtuallyDone, writeA45, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b, DLLByPassMode_b, NSOp, PDMD, RASidle_b, RASreturn_b, RefreshReturn_b, TestRASB, abortOperation_b, ackClear,
bcastWriteA, bcastWriteB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB,
startNSAdr_b, tclkDisable_b, updateRowAddr, writeOp_b);
output CASenable, RASkill, RASstate4, REQ, bcastWrite, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idHitRowMiss, idle, latchAbort, latchAbort_b, localREQ, nack, runtclk,
virtuallyDone, writeA45, writeA0123, writeA0123x;
input AUXorPDcycle, AUXpending_b, DAmode_b, DLLByPassMode_b, NSOp, PDMD, RASidle_b, RASreturn_b, RefreshReturn_b, TestRASB, abortOperation_b, ackClear, bcastWriteA, bcastWriteB, earlyDone,
earlyREQinhibit, frameEnableX, frameRaw_b, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, startNSAdr_b, tclkDisable_b,
updateRowAddr, writeOp_b;
supply1 vdd;
supply0 gnd;
ffBarRA F94BZ(hnl_331, gnd, gnd, vdd);
ltxRB F94BY(hnl_332, gnd, gnd, vdd);
aoi21A #(1) F94BX(hnl_333, gnd, gnd, gnd);
ffC #(1) F94BW(hnl_334, gnd, gnd);
nand #(0) F94BT(hnl_335, gnd, gnd, gnd, gnd);
nor #(1) F94BV(hnl_336, gnd, gnd);
nor #(1) F94BU(hnl_337, gnd, gnd);
nand #(1) F94BS(hnl_338, gnd, gnd);
nand #(1) F94BR(hnl_339, gnd, gnd);
not #(1) F94BQ(hnl_340, gnd);
not #(1) F94BP(hnl_341, gnd);
u5clkCtl clkCtl(bcastWrite, runtclk, DLLByPassMode_b, bcastWriteA, bcastWriteB, idHitA, idHitB, latchAbort_b, rclk, reset, tclkDisable_b, writeA0123);
u5HitLog HitLog(CASenable, RASkill, RASstate4, idHitRowMiss, idMissReturn_b, latchAbort_b, nack, RASidle_b, abortOperation_b, ackClear, bcastWrite, busyError_b, evalR, idHitA, idHitB, packetBSEL,
packetBSELx, powerDownMode, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, updateRowAddr, writeA45, writeA45_b, writeA0123);
u5PreCyc PreCyc(REQ, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idle, localREQ, virtuallyDone, writeA45, writeA45_b, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b,
NSOp, PDMD, RASreturn_b, RASstate4, RefreshReturn_b, TestRASB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitRowMiss, idMissReturn_b, rclk, regOp, reset, hnl_342, startNSAdr_b,
writeOp_b);
not #(1) U590(hnl_342, reset);
not #(1) U444(latchAbort, latchAbort_b);
endmodule

module u5RshXS (close0Pending_b, close0Selected, close1Pending_b, close1Selected, close0Req_b, close1Req_b, endCycleD, rclk, reset);
output close0Pending_b, close0Selected, close1Pending_b, close1Selected;
input close0Req_b, close1Req_b, endCycleD, rclk, reset;
supply1 vdd;
supply0 gnd;
ffBarC #(1) I11(close1Selected, rclk, hnl_343);
ffBarC #(1) I10(close0Selected, rclk, close0Pending_b);
not #(1) U443(close0Pending_b, hnl_344);
not #(1) U447(close1Pending_b, close1Pending);
nand #(1) U446(hnl_343, close0Pending_b, close1Pending);
aoi21A #(1) U253(hnl_345, endCycleD, close1Selected, reset);
aoi21A #(1) U250(hnl_346, endCycleD, close0Selected, reset);
srff I252(close1Pending, close1Req_b, hnl_345);
srff I251(hnl_344, close0Req_b, hnl_346);
endmodule

module u5RAScyc (DeviceBusy, RASAUXRet_b, RAScount_b, RASidle_b, RASldCount, RASprecharge, RASreturn_b, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RS_0_, RSTR, clearRASpending_b, close0Pending_b,
close0Selected, close1Pending_b, close1Selected, explicitRestore, localRSTR_b, setPD, DAmode_b, PD64after, PDreq2, RAScountLSB_b, RASoverflow_b, RASpending, RASpending_b, TestRSTR, busy_b,
close0Req_b, close1Req_b, closeCycle, closeCycle_b, doAUXcycle, endCycleD_buf, needRestore, powerDownReq_b, rclk, reFetchCycle_b, reset, turboDLL_b);
output DeviceBusy, RASAUXRet_b, RAScount_b, RASidle_b, RASldCount, RASprecharge, RASreturn_b, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RS_0_, RSTR, clearRASpending_b, close0Pending_b,
close0Selected, close1Pending_b, close1Selected, explicitRestore, localRSTR_b, setPD;
input DAmode_b, PD64after, PDreq2, RAScountLSB_b, RASoverflow_b, RASpending, RASpending_b, TestRSTR, busy_b, close0Req_b, close1Req_b, closeCycle, closeCycle_b, doAUXcycle, endCycleD_buf,
needRestore, powerDownReq_b, rclk, reFetchCycle_b, reset, turboDLL_b;
supply1 vdd;
supply0 gnd;
ffBNcRA I846(hnl_347, RAScount_b, RASoverflow_b, hnl_348);
nand #(1) I827(explicitRestore, reFetchCycle_b, expRestore_b);
ffBarD I451(hnl_349, rclk, hnl_350);
invFF U826(RAScount_b, hnl_349);
ffB #(1) I788(initLoad_b, rclk, hnl_351);
not #(1) U824(RS_0_, preRS_0_);
not #(1) U823(RS_b_0_, preRS_b_0_);
not #(1) U822(RS_b_1_, preRS_b_1_);
not #(1) U821(RS_1_, preRS_1_);
not #(1) U820(RS_b_2_, preRS_b_2_);
not #(1) U819(RS_2_, preRS_2_);
u5RshXS RshXS(close0Pending_b, close0Selected, close1Pending_b, close1Selected, close0Req_b, close1Req_b, endCycleD_buf, rclk, reset);
ffA I631(hnl_319, initLoad_b, rclk);
ffA I808(hnl_352, hnl_319, rclk);
ffBarA #(1) I807(setPDEarly, rclk, hnl_353);
not #(1) U835(RASidle_b, hnl_354);
not #(1) U525(localRSTR_b, hnl_355);
not #(1) U754(needRestore_b, needRestore);
aoi21A #(1) U696(hnl_249, vdd, needRestore_b, hnl_352);
not #(1) U494(RSTR, hnl_356);
not #(1) I645(hnl_355, RSTR_b);
not #(1) U776(hnl_357, turboDLL_b);
ffQBB I545(preRS_2_, preRS_b_2_, hnl_78, rclk);
ffQBB I773(RASn2, hnl_358, RASn3, rclk);
ffC #(1) I763(RASsel_3_, rclk, hnl_156);
ffBarC #(1) I762(RASsel_1_, rclk, RASprecharge_b);
ffBarC #(1) I761(RASsel_2_, rclk, hnl_359);
nand #(1) U784(hnl_351, RASpending, RASpendingD_b);
not #(1) U739(doAUXcycle_b, doAUXcycle);
not #(1) U736(reset_b, reset);
ffRC I734(RASsel_0_, rclk, powerDownReq_b, hnl_360);
ffRC I793(setPD, rclk, reset_b, setPDEarly);
aoi21A #(1) U770(hnl_361, RAScntLSBdel, RAScntZ, hnl_358);
oai21A U730(m13, PD2leading, closeCycle, RS_1_);
nor #(1) U725(hnl_362, RASidleLocal_b, PD2leading);
nor #(1) U755(hnl_354, RS_b_2_, RS_b_1_, RS_b_0_);
nor #(1) U744(RASpowerDown, RS_2_, RS_b_1_, RS_b_0_);
nor #(1) U693(hnl_363, m00, RS_b_2_, RS_b_0_);
ffSB I657(hnl_364, rclk, hnl_171, reset);
not #(1) U658(clearRASpending_b, hnl_364);
not #(1) U679(RASprecharge, RASprecharge_b);
DAff I639(RSTR_b, rclk, TestRSTR, hnl_365, DAmode_b);
aoi22A U600(hnl_171, RS_b_2_, RS_b_0_, RS_2_, RS_0_);
ffQBC I765(RAScntZ_b, RAScntZ, hnl_366, rclk);
ffQBC I499(preRS_0_, preRS_b_0_, hnl_367, rclk);
ffQBC I498(preRS_1_, preRS_b_1_, hnl_368, rclk);
ffBarA #(1) I716(hnl_369, rclk, PDreq2);
not #(1) U576(RASsense, RASsense_b);
ffD I825(RASldCount, hnl_370, rclk);
ffBarB #(1) I792(RASpendingD_b, rclk, RASpending);
ffBarB #(1) I772(RAScntLSBdel, rclk, RAScountLSB_b);
ffBarB #(1) I740(PD2leading, rclk, hnl_371);
nand #(1) I231(hnl_372, RASidleLocal_b, RASn2);
nand #(1) U797(hnl_370, hnl_351, hnl_366);
nand #(1) I721(hnl_373, expRestore_b, reset_b);
nand #(1) U709(m00, needRestore_b, closeCycle_b);
nand #(1) I690(hnl_374, m13, m14);
nand #(1) I571(hnl_375, m11, m12);
nand #(1) I729(hnl_376, m15, reset_b, m16);
nand #(1) U722(hnl_377, m21, m22, m23);
nand #(1) I695(hnl_378, m03, reset_b, m04);
nand #(1) U684(hnl_306, setRSTR_b, RASsense_b, RSTR_b);
nand #(1) U674(hnl_360, RS_0_, hnl_379, hnl_380);
nand #(1) I551(hnl_74, m21, m02, RASprecharge_b);
nand #(1) U831(DeviceBusy, hnl_354, busy_b, hnl_269);
nand #(1) U777(RASidleLocal_b, RS_2_, RS_1_, RS_0_);
nand #(1) U627(expRestore_b, preRS_b_2_, preRS_1_, preRS_0_);
nand #(1) U622(RASholdOff_b, RS_b_2_, RS_1_, RS_b_0_);
nand #(1) U593(RASAUXRet_b, RAScntZ, RASholdOff, doAUXcycle);
nand #(1) U591(RASreturn_b, RAScntZ, doAUXcycle_b, RASsense);
nand #(1) U588(RASsense_b, RS_b_2_, RS_b_1_, RS_0_);
nand #(1) U578(RASprecharge_b, RS_2_, RS_b_1_, RS_0_);
nand #(1) U400(RASn3, hnl_347, RAScount_b, RASn2);
nor #(1) U800(hnl_156, RASidleLocal_b, hnl_381, gnd);
nor #(1) U544(hnl_78, hnl_362, hnl_373, hnl_377);
nor #(1) U429(hnl_368, hnl_375, hnl_374, hnl_376);
nor #(1) U430(hnl_367, hnl_74, hnl_363, hnl_378);
nor #(1) U798(hnl_381, needRestore, RASpending_b);
nor #(1) U775(hnl_269, hnl_357, PD64after);
nor #(1) U732(hnl_359, RASsense, RASpowerDown);
nor #(1) U683(setRSTR_b, hnl_249, setPDEarly);
nand #(0) U685(hnl_353, RAScntZ, RS_0_, RS_1_, RS_b_2_);
nand #(0) U560(m11, RAScntZ, RS_b_1_, RS_b_0_, RS_b_2_);
nand #(0) U190(hnl_350, RASn3, RASidleLocal_b, hnl_361, RAScount_b);
nand #(1) U724(hnl_371, PDreq2, hnl_369);
nand #(1) U691(m12, RS_1_, RS_b_0_);
nand #(1) U660(hnl_379, RS_b_2_, RS_1_);
nand #(1) U562(m14, RASpendingD_b, RS_1_);
nand #(1) U561(m16, RS_b_2_, RS_1_);
nand #(1) U559(m15, RS_1_, RS_b_0_);
not #(1) U845(hnl_348, hnl_372);
not #(1) U840(hnl_356, hnl_382);
not #(1) U839(hnl_382, hnl_383);
not #(1) U838(hnl_383, hnl_242);
not #(1) U837(hnl_242, localRSTR_b);
not #(1) U621(RASholdOff, RASholdOff_b);
nand #(1) U702(m21, RAScntZ, RS_1_, RS_b_2_);
nand #(1) U701(m23, RAScntZ_b, RS_2_, RS_b_1_);
nand #(1) U699(m22, RAScntZ_b, RS_2_, RS_b_0_);
nand #(1) U663(hnl_380, needRestore_b, RS_1_, RASpending);
nand #(1) U647(hnl_365, hnl_306, RASholdOff_b, reset_b);
nand #(1) U557(m02, RAScntZ, RS_b_1_, RS_2_);
nand #(1) U555(m03, RASpendingD_b, RS_0_, RS_2_);
nand #(1) U553(m04, RAScntZ_b, RS_0_, RS_b_2_);
mux21 #(1) I532(hnl_366, RASn3, RASn2, RAScntLSBdel);
endmodule

module u5Rfsh0 (RefCount, RefLoad, cout_b, dataZ01, dataZ23, rfshEqualsZero, cin_b, cnt, dataIn01, dataIn23, evalRfshCount, readR_4_, reset_b, writeR_4_);
output RefCount, RefLoad, cout_b;
inout dataZ01, dataZ23, rfshEqualsZero;
input cin_b, cnt, dataIn01, dataIn23, evalRfshCount, readR_4_, reset_b, writeR_4_;
supply1 vdd;
supply0 gnd;
latRB #(1) I58(RefLoad, dataIn23, writeR_4_, reset_b);
countupx I57(cout_b, RefCount, cin_b, rfshEqualsZero, writeR_4_, reset_b, dataIn01, cnt, RefLoad);
not #(1) U48(hnl_220, RefCount);
nandpd2 U42(dataZ23, RefLoad, readR_4_);
nandpd2 U38(dataZ01, RefCount, readR_4_);
nandpc2 U36(rfshEqualsZero, hnl_220, evalRfshCount);
endmodule

module u5MscR7 (control_7_, control_5_, control_4_, control_3_, dataZ0, dataZ1, dataZ2, dataZ3, DAmode, dataIn0, dataIn1, dataIn2, dataIn3, ictrl_5_, ictrl_4_, ictrl_3_, readR_9_, readR_7_, readR_3_,
readR_0_, reset, writeR_3_);
output control_7_, control_5_, control_4_, control_3_;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input DAmode, dataIn0, dataIn1, dataIn2, dataIn3, ictrl_5_, ictrl_4_, ictrl_3_, readR_9_, readR_7_, readR_3_, readR_0_, reset, writeR_3_;
supply1 vdd;
supply0 gnd;
nor #(1) I149(control_5_, DAmode, hnl_384);
not #(1) U150(hnl_384, C5);
pdnull U147(dataZ1, readR_9_);
pdnull U146(dataZ0, readR_9_);
pdnull U145(dataZ3, readR_0_);
latBarSB #(1) I143_0_(control_7_, dataIn0, writeR_3_, reset);
latBarSB #(1) I143_1_(C5, dataIn1, writeR_3_, reset);
latBarSB #(1) I143_2_(control_4_, dataIn2, writeR_3_, reset);
latBarSB #(1) I143_3_(control_3_, dataIn3, writeR_3_, reset);
nandpd1 U148(dataZ3, readR_7_);
nandpd1 U242(dataZ0, readR_0_);
nandpd1 U138(dataZ2, readR_7_);
nandpd2 U133(dataZ0, control_7_, readR_3_);
nandpd2 U131_0_(dataZ1, ictrl_5_, readR_3_);
nandpd2 U131_1_(dataZ2, ictrl_4_, readR_3_);
nandpd2 U131_2_(dataZ3, ictrl_3_, readR_3_);
endmodule

module u5bit78 (ADR_6_, CASctCy70, NSWE_7_, RfshRwCy70, bcastWriteB, chainOut_8_, control_7_, control_5_, control_4_, control_3_, opcode_3_, opcode_0_, pd2_7_, dataZ0_7_, dataZ1_7_, dataZ2_7_,
dataZ3_7_, idHitA, rfshEqualsZero, rowHitLeftB, rowHitRightB, CASctCy67, DAmode_b, NSAdr_6_, RASaddrEnable, RfshCntCary67, RfshRwCy67, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn1_7_,
dataIn2_7_, dataIn3_7_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, ictrl_5_, ictrl_4_, ictrl_3_, incColAdr_b, incRfshInterval, incRfshRow_b, loadNSWE,
localBSEL, partialId_b_4_, pd0_7_, pd0_8_, pd1_7_, pd1_8_, pd2_8_, pd3_7_, pd3_8_, rclk, readR_5_, readR_4_, readR_3_, readR_1_, readR_0_, readR_10_, readR_9_, readR_8_, readR_7_, reset,
restoreBank0, restoreBank1, testBD_8_, unloadNSWE, updateRowAddr, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
output ADR_6_, CASctCy70, NSWE_7_, RfshRwCy70, bcastWriteB, chainOut_8_, control_7_, control_5_, control_4_, control_3_, opcode_3_, opcode_0_, pd2_7_;
inout dataZ0_7_, dataZ1_7_, dataZ2_7_, dataZ3_7_, idHitA, rfshEqualsZero, rowHitLeftB, rowHitRightB;
input CASctCy67, DAmode_b, NSAdr_6_, RASaddrEnable, RfshCntCary67, RfshRwCy67, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn1_7_, dataIn2_7_, dataIn3_7_, driveColAdr, driveNSAdr,
drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, ictrl_5_, ictrl_4_, ictrl_3_, incColAdr_b, incRfshInterval, incRfshRow_b, loadNSWE, localBSEL, partialId_b_4_, pd0_7_, pd0_8_, pd1_7_,
pd1_8_, pd2_8_, pd3_7_, pd3_8_, rclk, readR_5_, readR_4_, readR_3_, readR_1_, readR_0_, readR_10_, readR_9_, readR_8_, readR_7_, reset, restoreBank0, restoreBank1, testBD_8_, unloadNSWE,
updateRowAddr, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
aoi21A #(1) F94AV(hnl_385, gnd, gnd, gnd);
ffBarRA F94AU(hnl_386, gnd, gnd, vdd);
ltxRB F94AT(hnl_387, gnd, gnd, vdd);
ffC #(1) F94AS(hnl_388, gnd, gnd);
nand #(0) F94AP(hnl_389, gnd, gnd, gnd, gnd);
nor #(1) F94AR(hnl_390, gnd, gnd);
nor #(1) F94AQ(hnl_391, gnd, gnd);
nand #(1) F94AO(hnl_392, gnd, gnd);
nand #(1) F94AN(hnl_393, gnd, gnd);
ltxSB I572(hnl_394, hnl_63, writeA0123, reset);
ltxBarSB op0(A0_8_, writeA0123x, pd0_8_, reset);
ltxBarSB op3(hnl_395, writeA0123x, pd1_8_, reset);
ltxBarB Addr35(Addr_35_, writeA0123, pd3_8_);
ltxBarB Addr34(Addr_34_, writeA0123, pd3_7_);
latBNcA I584(packetRowAddr_6_, RASaddrEnable, packetRowAddr_b_6_);
mux71x AdrMUX6(ADR_6_, ColAdr_6_, NSAdr_6_, packetRowAddr_6_, rfshRowAddr_6_, bank0RowAddr_6_, bank1RowAddr_6_, testBD_8_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_396, restoreBank0,
restoreBank1, DAmode);
not #(1) U574(bcastWriteB, hnl_394);
not #(1) I544(opcode_0_, A0_8_);
not #(1) U543(opcode_3_, hnl_395);
nand #(1) U571(hnl_63, pd1_8_, pd0_8_);
u5NSWErg NSWErg7(NSWE_7_, selectEven_7_, loadNSWE, pd2_7_, pd3_7_, rclk, unloadNSWE);
u5Rfsh0 RefCnt8(RefCount_8_, RefLoad_8_, n12_1_, dataZ1_7_, dataZ3_7_, rfshEqualsZero, n12_0_, incRfshInterval, dataIn1_7_, dataIn3_7_, evalRfshCount, readR_4_, reset_b, writeR_4_);
u5Rfsh0 RefCnt7(RefCount_7_, RefLoad_7_, n12_0_, dataZ0_7_, dataZ2_7_, rfshEqualsZero, RfshCntCary67, incRfshInterval, dataIn0_7_, dataIn2_7_, evalRfshCount, readR_4_, reset_b, writeR_4_);
not #(1) I556(DAmode, DAmode_b);
nor #(1) I552(hnl_396, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U548(RfshRwCy70, hnl_397);
not #(1) U547(CASctCy70, hnl_79);
not #(1) U549(hnl_397, hnl_398);
not #(1) U546(hnl_79, net690);
not #(1) U545(chainOut_8_, hnl_69);
not #(1) U539(hnl_69, hnl_399);
mux21 #(1) I537(hnl_399, chainOutEven_8_, chainOutOdd_8_, rclk);
not #(1) U519(ColAdr_6_, net689);
countup Col_6_(net690, net689, incColAdr_b, CASctCy67, writeA0123x, pd0_7_);
u5id Id26_35(id_35_, id_26_, dataZ1_7_, dataZ3_7_, idHitA, partialId_b_5_, Addr_35_, dataIn1_7_, dataIn3_7_, eval, readR_1_, reset_b, writeR_1_);
u5id Id25_34(id_34_, id_25_, dataZ0_7_, dataZ2_7_, idHitA, partialId_b_4_, Addr_34_, dataIn0_7_, dataIn2_7_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_6_(bank0RowAddr_6_, bank1RowAddr_6_, dataZ0_7_, dataZ2_7_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_6_, packetRowAddr_b_6_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr6(adrSelReg_6_, partialId_b_5_, packetRowAddr_b_6_, dataZ0_7_, dataIn0_7_, pd1_7_, pd2_8_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw6(hnl_398, rfshRowAddr_6_, dataZ0_7_, RfshRwCy67, dataIn0_7_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR7 MscR7(control_7_, control_5_, control_4_, control_3_, dataZ0_7_, dataZ1_7_, dataZ2_7_, dataZ3_7_, DAmode, dataIn0_7_, dataIn1_7_, dataIn2_7_, dataIn3_7_, ictrl_5_, ictrl_4_, ictrl_3_,
readR_9_, readR_7_, readR_3_, readR_0_, reset, writeR_3_);
not #(1) F94AM(hnl_400, gnd);
not #(1) F94AL(hnl_401, gnd);
not #(1) U511(reset_b, reset);
endmodule

module u5CCct (out, q, bypassIn, clk_b, errorIn, load, resetCnt_b, sel);
output out, q;
input bypassIn, clk_b, errorIn, load, resetCnt_b, sel;
supply1 vdd;
supply0 gnd;
nor #(1) U18(hnl_402, hnl_403, errorIn);
ffBNcRA I17(hnl_403, clk_b, q, resetCnt_b);
not #(1) U4(hnl_404, bypassIn);
latBarA I2(hnl_405, load, clk_b);
not #(1) I21(q, hnl_402);
not #(1) U11(out, hnl_406);
mux21 #(1) I3(hnl_406, hnl_405, hnl_404, sel);
endmodule

module u5CCLog (count, loadIctrl, powerOn, resetCap, resetCnt_b, done, evalRfshCount, mclk, reset, writeA0123);
output count, loadIctrl, powerOn, resetCap, resetCnt_b;
input done, evalRfshCount, mclk, reset, writeA0123;
supply1 vdd;
supply0 gnd;
aoi21A #(1) U42(resetCnt_b, s0_b, resetCap, reset);
aoi21A #(1) U2(hnl_407, done_b, s1_b, s0_b);
ffB #(1) I36(s0, mclk, hnl_408);
ffB #(1) I35(resetCap, mclk, hnl_407);
not #(1) U34(s0_b, s0);
not #(1) U33(s1_b, resetCap);
nor #(1) I32(done_b, done, reset);
oai21A U3(hnl_408, s1_b, hnl_145, done_b);
nand #(0) U7(hnl_409, evalRfshCount, writeA0123, s0, resetCap);
nand #(0) U24(hnl_410, done_b, s1_b, s0_b, mclk);
nand #(1) I18(powerOn, resetCap, s0);
not #(1) U43(hnl_145, evalRfshCount);
not #(1) I21(count, hnl_410);
ffBarA #(1) I6(loadIctrl, mclk, hnl_409);
endmodule

module u5CCctl (ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, powerOn, resetCap, control_7_, control_6_, control_5_, control_4_, control_3_, control_2_, control_1_, control_0_, done,
evalRfshCount, mclk, reset, writeA0123);
output ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, powerOn, resetCap;
input control_7_, control_6_, control_5_, control_4_, control_3_, control_2_, control_1_, control_0_, done, evalRfshCount, mclk, reset, writeA0123;
supply1 vdd;
supply0 gnd;
u5CCct CCct_0_(ictrl_0_, CCn1_1_, control_0_, CCn1_0_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_1_(ictrl_1_, CCn1_2_, control_1_, CCn1_1_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_2_(ictrl_2_, CCn1_3_, control_2_, CCn1_2_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_3_(ictrl_3_, CCn1_4_, control_3_, CCn1_3_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_4_(ictrl_4_, CCn1_5_, control_4_, CCn1_4_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_5_(ictrl_5_, error, control_5_, CCn1_5_, gnd, loadIctrl, resetCnt_b, control_7_);
ffBNcRA I52(hnl_411, count, hnl_411, resetCnt_b);
mux21 #(1) I46(CCn1_0_, hnl_411, count, control_6_);
u5CCLog CCLog(count, loadIctrl, powerOn, resetCap, resetCnt_b, done, evalRfshCount, mclk, reset, writeA0123);
endmodule

module u5CASdy0 (readDelay_0_, writeDelay_0_, dataZ1, dataZ3, dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_);
output readDelay_0_, writeDelay_0_;
inout dataZ1, dataZ3;
input dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
latSB #(1) I398(readDelay_0_, dataIn1, writeR_2_, reset);
latRB #(1) I397(writeDelay_0_, dataIn3, writeR_2_, reset_b);
nandpd2 U402(dataZ1, readDelay_0_, readR_2_);
nandpd2 U395(dataZ3, writeDelay_0_, readR_2_);
endmodule

module u5MscR3 (ackDelay, ackWinDelay, setRE, skipBit, dataZ0, dataZ1, dataZ2, dataIn0, dataIn2, dataIn3, readR_9_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeA0123x, writeR_7_, writeR_3_,
writeR_2_);
output ackDelay, ackWinDelay, setRE, skipBit;
inout dataZ0, dataZ1, dataZ2;
input dataIn0, dataIn2, dataIn3, readR_9_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeA0123x, writeR_7_, writeR_3_, writeR_2_;
supply1 vdd;
supply0 gnd;
nor #(1) U164(hnl_412, writeA0123x, reset);
pdnull U157(dataZ1, readR_9_);
pdnull U156(dataZ0, readR_9_);
latRB #(1) I162(setRE, dataIn3, writeR_7_, hnl_412);
latRB #(1) I158(skipBit, dataIn0, writeR_3_, reset_b);
latRB #(1) I155(ackWinDelay, dataIn0, writeR_2_, reset_b);
latRB #(1) hnl_413(ackDelay, dataIn2, writeR_2_, reset_b);
nandpd1 U128(dataZ1, readR_0_);
nandpd2 U161(dataZ0, skipBit, readR_3_);
nandpd2 U238(dataZ2, ackDelay, readR_2_);
nandpd2 U132(dataZ0, ackWinDelay, readR_2_);
endmodule

module u5bit3 (ADR_2_, CASctCy34, Count_1_, DAR_2_, NSWE_3_, RASctCy32, RfshCntCary34, RfshRwCy34, ackDelay_0_, ackWinDelay_0_, partialId_b_1_, pd2_3_, readDelay_0_, rfshBSEL, setRE, skipBit,
writeDelay_0_, dataZ0_3_, dataZ1_3_, dataZ2_3_, dataZ3_3_, idHitB, rfshEqualsZero, rowHitLeftB, rowHitRightB, CASctCy23, DAmode_b, NSAdr_2_, RASaddrEnable, RAScount_b, RASldCount, RASsel_3_,
RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary23, RfshRwCy23, dataIn0_3_, dataIn1_3_, dataIn2_3_, dataIn3_3_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount,
incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_0_, pd0_3_, pd1_3_, pd2_4_, pd3_3_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_,
readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, testBD_4_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_,
writeR_4_, writeR_3_, writeR_2_, writeR_1_);
output ADR_2_, CASctCy34, Count_1_, DAR_2_, NSWE_3_, RASctCy32, RfshCntCary34, RfshRwCy34, ackDelay_0_, ackWinDelay_0_, partialId_b_1_, pd2_3_, readDelay_0_, rfshBSEL, setRE, skipBit, writeDelay_0_;
inout dataZ0_3_, dataZ1_3_, dataZ2_3_, dataZ3_3_, idHitB, rfshEqualsZero, rowHitLeftB, rowHitRightB;
input CASctCy23, DAmode_b, NSAdr_2_, RASaddrEnable, RAScount_b, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary23, RfshRwCy23, dataIn0_3_, dataIn1_3_, dataIn2_3_, dataIn3_3_,
driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_0_, pd0_3_, pd1_3_, pd2_4_,
pd3_3_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, testBD_4_, unloadNSWE, updateRowAddr,
writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_2_, writeR_1_;
supply1 vdd;
supply0 gnd;
latSRB rowExpRest1(rowExpRest_1_, dataIn3_3_, writeR_6_, reset_b, gnd);
latSRB rowImpRest1(rowImpRest_1_, dataIn2_3_, writeR_6_, vdd, reset);
latSRB rowAcc1(rowAcc_1_, dataIn1_3_, writeR_6_, reset_b, gnd);
latSRB rowPre1(rowPre_1_, dataIn0_3_, writeR_6_, vdd, reset);
ltxBarB Count1(Count_b_1_, writeA45, pd3_3_);
ltxBarB Addr30(Addr_30_, writeA0123, pd3_3_);
latBNcA I578(packetRowAddr_2_, RASaddrEnable, packetRowAddr_b_2_);
mux71x AdrMUX2(ADR_2_, ColAdr_2_, NSAdr_2_, packetRowAddr_2_, rfshRowAddr_2_, bank0RowAddr_2_, bank1RowAddr_2_, testBD_4_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_225, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg3(NSWE_3_, selectEven_3_, loadNSWE, pd2_3_, pd3_3_, rclk, unloadNSWE);
not #(1) I571(DAmode, DAmode_b);
nor #(1) I567(hnl_225, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U553(Count_1_, Count_b_1_);
u5RfshRw RfshRw2(RfshRwCy34, rfshRowAddr_2_, dataZ0_3_, n3_0_, dataIn0_3_, incRfshRow_b, readR_5_, writeR_5_);
u5RfshRw RfshBS(n3_0_, rfshBSEL, dataZ1_3_, RfshRwCy23, dataIn1_3_, incRfshRow_b, readR_5_, writeR_5_);
mux41 #(1) I548(cnt1, rowPre_1_, rowAcc_1_, rowImpRest_1_, rowExpRest_1_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
nandpd2 U547(dataZ3_3_, rowExpRest_1_, readR_6_);
nandpd2 U529(dataZ2_3_, rowImpRest_1_, readR_6_);
nandpd2 U517(dataZ0_3_, rowPre_1_, readR_6_);
nandpd2 U515(dataZ1_3_, rowAcc_1_, readR_6_);
u5id Id21_30(id_30_, id_21_, dataZ0_3_, dataZ2_3_, idHitB, partialId_b_0_, Addr_30_, dataIn0_3_, dataIn2_3_, eval, readR_1_, reset_b, writeR_1_);
u5DARbit DARbit2(DAR_2_, loadDAR, DAmode, setDAR, testBD_4_);
not #(1) U555(ColAdr_2_, net2784);
countup RASct1(RASctCy32, RAScnt_1_, RAScount_b, gnd, RASldCount, cnt1);
countup Col_2_(CASctCy34, net2784, incColAdr_b, CASctCy23, writeA0123x, pd0_3_);
u5Rhit Rhit_2_(bank0RowAddr_2_, bank1RowAddr_2_, dataZ0_3_, dataZ2_3_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_2_, packetRowAddr_b_2_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr2(adrSelReg_2_, partialId_b_1_, packetRowAddr_b_2_, dataZ0_3_, dataIn0_3_, pd1_3_, pd2_4_, readR_8_, reset_b, writeA0123, writeR_8_);
u5Rfsh1 RefCnt3(RefCount_3_, RefLoad_3_, RfshCntCary34, dataZ0_3_, dataZ2_3_, rfshEqualsZero, RfshCntCary23, incRfshInterval, dataIn0_3_, dataIn2_3_, evalRfshCount, readR_4_, reset, reset_b,
writeR_4_);
u5CASdy0 CASdy0(readDelay_0_, writeDelay_0_, dataZ1_3_, dataZ3_3_, dataIn1_3_, dataIn3_3_, readR_2_, reset, reset_b, writeR_2_);
u5MscR3 MscR3(ackDelay_0_, ackWinDelay_0_, setRE, skipBit, dataZ0_3_, dataZ1_3_, dataZ2_3_, dataIn0_3_, dataIn2_3_, dataIn3_3_, readR_9_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeA0123x,
writeR_7_, writeR_3_, writeR_2_);
not #(1) U490(reset_b, reset);
endmodule

module u5DirtyB (dirtyB0, dirtyB1, needRestore, CASwrite, localRSTR_b, packetBSELx, rclk, reset);
output dirtyB0, dirtyB1, needRestore;
input CASwrite, localRSTR_b, packetBSELx, rclk, reset;
supply1 vdd;
supply0 gnd;
not #(1) U55(needRestore, hnl_145);
nor #(1) U52(clearDirtyB, localRSTR_b, hnl_414);
ffBarA #(1) I51(hnl_414, rclk, localRSTR_b);
aoi21A #(1) U49(hnl_415, packetBSELx, clearDirtyB, reset);
aoi21A #(1) U48(hnl_220, clearDirtyB, hnl_408, reset);
nand #(1) U4(hnl_404, CASwrite, hnl_408);
nand #(1) U9(hnl_416, CASwrite, packetBSELx);
not #(1) U3(hnl_408, packetBSELx);
not #(1) U27(hnl_417, packetBSELx);
aoi22A U43(hnl_145, hnl_417, dirtyB0, packetBSELx, dirtyB1);
srff I10(dirtyB1, hnl_416, hnl_415);
srff I5(dirtyB0, hnl_404, hnl_220);
endmodule

module u5Wcntl (TestMPBT, TestWE, TestWML, TestWPBT, TestWRITE, TestRASB, TestRSTR, TimingTest, WPB_MPBTest, rawTestWE);
output TestMPBT, TestWE, TestWML, TestWPBT, TestWRITE;
input TestRASB, TestRSTR, TimingTest, WPB_MPBTest, rawTestWE;
supply1 vdd;
supply0 gnd;
not #(1) U130(TestRAS, TestRASB);
nor #(1) U177(hnl_418, WEatRSTRfall_b, hnl_419);
not #(1) I186(TestWPBT, hnl_420);
not #(1) I185(TestWML, hnl_421);
not #(1) I184(TestWE, hnl_422);
not #(1) I183(TestMPBT, hnl_423);
not #(1) I171(TestWRITE, hnl_424);
ffBNcRA I18(WEatRSTRfall_b, TestRSTR, rawTestWE, TestRAS);
ffNcA I17(WEatRASBfall, rawTestWE, TestRASB);
nand #(1) I160(hnl_425, hnl_426, WEatRSTRfall, WEatRASBfall_b);
nand #(1) U144(hnl_427, hnl_428, TimingTest, hnl_429);
not #(1) U20(WEatRSTRfall, WEatRSTRfall_b);
not #(1) U182(hnl_430, hnl_431);
nor #(1) I173(hnl_431, rawTestWE, hnl_418);
nor #(1) U175(hnl_419, TimingTest, WPB_MPBTest);
nand #(0) U79(hnl_432, rawTestWE, WEatRSTRfall, WEatRASBfall, TimingTest);
nand #(1) I168(hnl_433, hnl_432, hnl_434);
nand #(1) U104(hnl_421, rawTestWE, WEatRSTRfall, TestWPBT);
nand #(1) U155(hnl_422, hnl_427, TestRAS);
nand #(1) U170(hnl_424, hnl_430, TestRAS);
nand #(1) U169(hnl_434, WEatRASBfall_b, WPB_MPBTest);
nand #(1) U165(hnl_423, hnl_433, TestRAS);
nand #(1) U125(hnl_420, TestRAS, WPB_MPBTest);
not #(1) I181(hnl_426, rawTestWE);
not #(1) U180(hnl_429, WPB_MPBTest);
not #(1) U151(hnl_428, hnl_425);
not #(1) U100(WEatRASBfall_b, WEatRASBfall);
endmodule

module u5DAdec (AGEGND, AGEING, CMPV, HVST, PDMD, ROLLC, SDST, SerialMode, SimpleMode, TimingTest, VCMNA, VRST, WPB_MPBTest, chain_b, pwrdnRcvrs, BIMDI, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_,
DAmode, powerDownMode, runclk_b);
output AGEGND, AGEING, CMPV, HVST, PDMD, ROLLC, SDST, SerialMode, SimpleMode, TimingTest, VCMNA, VRST, WPB_MPBTest, chain_b, pwrdnRcvrs;
input BIMDI, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, DAmode, powerDownMode, runclk_b;
supply1 vdd;
supply0 gnd;
nor #(1) U413(hnl_435, runclk_b, powerDownMode);
nand #(1) U328(hnl_436, hnl_36, hnl_435, hnl_295);
not #(1) I403(DARt_2_, hnl_437);
nand #(1) U331(DRAMtest, DARt_3_, DARt_4_);
not #(1) U366(hnl_131, powerDownMode);
not #(1) U410(DAR_b_2_, hnl_438);
not #(1) U579(BIMD_b, BIMDI);
invEE I290(chain_b, hnl_436);
not #(1) I390(ROLLC, hnl_439);
not #(1) I389(AGEGND, hnl_298);
not #(1) I344(AGEING, hnl_440);
not #(1) I397(pwrdnRcvrs, hnl_435);
not #(1) I352(pwrdnRcvrs, hnl_435);
not #(1) I395(PDMD, hnl_441);
not #(1) I394(VRST, hnl_442);
not #(1) I393(VCMNA, hnl_443);
not #(1) I392(HVST, hnl_444);
not #(1) I391(SDST, hnl_445);
nor #(1) U411(hnl_438, hnl_293, BIMDI);
nor #(1) U372(DA0, DARt_0_, DARt_1_);
nor #(1) U371(DA1, DAR_b_0_, DARt_1_);
nor #(1) U370(DA2, DARt_0_, DAR_b_1_);
nor #(1) U369(DA3, DAR_b_0_, DAR_b_1_);
nand #(1) I365(hnl_446, hnl_131, hnl_447);
nand #(1) U350(hnl_298, SimpleMode, DAR_b_2_, DA2);
nand #(1) U336(hnl_272, DAR_b_4_, DAR_b_2_, DA1);
nand #(1) U338(hnl_440, SimpleMode, DAR_b_2_, DA1);
nand #(1) U368(hnl_439, R_IFTest, DAR_b_2_, DA0);
nand #(1) U347(hnl_448, R_IFTest, DAR_b_2_, DA1);
nand #(1) U348(hnl_449, DAR_b_4_, DAR_b_2_, DA2);
nand #(1) U400(hnl_437, DAR_2_, BIMD_b, DAmode);
nand #(1) U363(hnl_442, DRAMtest, DARt_2_, DA3);
nand #(1) U361(hnl_443, DRAMtest, DARt_2_, DA2);
nand #(1) U358(hnl_447, DRAMtest, DAR_b_2_, DA3);
nand #(1) U357(hnl_445, DRAMtest, DARt_2_, DA0);
nand #(1) U354(hnl_444, DRAMtest, DARt_2_, DA1);
nor #(1) U412(hnl_293, DAR_2_, hnl_450);
nor #(1) U405(DAR_b_3_, DAR_3_, BIMDI);
not #(1) U404(hnl_450, DAmode);
not #(1) U396(hnl_441, hnl_446);
nand #(1) U408(hnl_295, DARt_3_, DAmode);
nand #(1) U398_0_(DAR_b_4_, DAR_4_, BIMD_b);
nand #(1) U398_1_(DAR_b_1_, DAR_1_, BIMD_b);
nand #(1) U398_2_(DAR_b_0_, DAR_0_, BIMD_b);
nand #(1) U330(hnl_36, DAR_b_3_, DARt_4_);
not #(1) I417(CMPV, hnl_448);
not #(1) I351(WPB_MPBTest, hnl_449);
not #(1) I345(TimingTest, hnl_272);
not #(1) I407(SerialMode, hnl_295);
not #(1) I406(DARt_3_, DAR_b_3_);
not #(1) I399_0_(DARt_4_, DAR_b_4_);
not #(1) I399_1_(DARt_1_, DAR_b_1_);
not #(1) I399_2_(DARt_0_, DAR_b_0_);
not #(1) I292(SimpleMode, hnl_36);
not #(1) I275(R_IFTest, DRAMtest);
endmodule

module u5TstCtl (AGEGND, AGEING, CMPV, DAWD0123, DAWD4567, DAmode_b, DLLByPassMode_b, HVST, PDMD, ROLLC, SDST, TestMPBT, TestSOut, TestWE, TestWML, TestWPBT, TestWRITE, VCMNA, VRST, chain_b,
enableSOut, loadDAR, needRestore, pwrdnRcvrs, testLoad_b, BIMDI, CASwrite, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, RCRED, SInRaw_b, SuperBE_b, TestCAS, TestRASB, TestRSTR, chainOut_8_, localBSEL,
localRSTR_b, lowVref, powerDownMode, rclk, reset, resetDAmode_b, runclk_b, slow, testBD_b_0_);
output AGEGND, AGEING, CMPV, DAWD0123, DAWD4567, DAmode_b, DLLByPassMode_b, HVST, PDMD, ROLLC, SDST, TestMPBT, TestSOut, TestWE, TestWML, TestWPBT, TestWRITE, VCMNA, VRST, chain_b, enableSOut,
loadDAR, needRestore, pwrdnRcvrs, testLoad_b;
input BIMDI, CASwrite, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, RCRED, SInRaw_b, SuperBE_b, TestCAS, TestRASB, TestRSTR, chainOut_8_, localBSEL, localRSTR_b, lowVref, powerDownMode, rclk, reset,
resetDAmode_b, runclk_b, slow, testBD_b_0_;
supply1 vdd;
supply0 gnd;
nor #(1) I351(DAmode, hnl_451, DLLByPassMode_b);
latRA #(1) I318(hnl_452, SInRaw_b, lowVref, resetDAmode_b);
u5DirtyB DirtyB(dirtyB0, dirtyB1, needRestore, CASwrite, localRSTR_b, localBSEL, rclk, reset);
srff I313(hnl_453, TestRASB, hnl_454);
u5Wcntl Wcntl(TestMPBT, TestWE, TestWML, TestWPBT, TestWRITE, TestRASB, TestRSTR, TimingTest, WPB_MPBTest, rawTestWE);
u5DAdec DAdec(AGEGND, AGEING, CMPV, HVST, PDMD, ROLLC, SDST, SerialMode, SimpleMode, TimingTest, VCMNA, VRST, WPB_MPBTest, chain_b, pwrdnRcvrs, BIMDI, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, DAmode,
powerDownMode, runclk_b);
nand #(1) U213(hnl_454, DAmode, rclk);
invEE U251(DAmode_b, DAmode);
not #(1) U295(testLoad_b, hnl_455);
not #(1) I287(TestSOut, hnl_456);
not #(1) I289(loadDAR, hnl_457);
oai21A U255(hnl_457, TestCAS, DAmode_b, TestRASB);
mux31 #(1) I273(hnl_458, chainOut_8_, FailDetectOut_b, hnl_459, hnl_52, SimpleMode, ROLLC);
mux21 #(1) I262(hnl_460, DAcnt_b_1_, hnl_461, DAcnt_0_);
nand #(1) U308(hnl_462, TestCAS, TestRASB, SimpleMode);
nand #(1) I243(hnl_463, hnl_464, hnl_465);
nor #(1) U236(hnl_52, hnl_466, ROLLC);
not #(1) I312(enableSOut, hnl_56);
not #(1) I285(DAWD4567, hnl_467);
not #(1) I230(DAWD0123, hnl_468);
nand #(1) I229(hnl_469, hnl_140, hnl_462, DAmode);
ffBNcRA I305(hnl_470, hnl_471, gnd, TestCAS_b);
ffBNcRA I296(hnl_472, hnl_454, hnl_473, hnl_474);
ffBNcRA I293(hnl_475, SOutClk_b, hnl_476, resetFailDet_b);
ffBNcRA I286(hnl_477, SOutClk, hnl_478, resetFailDet_b);
ffBNcRA I249(hnl_479, TestCAS, gnd, TestRASB);
ffBNcRA I245(hnl_480, hnl_471, hnl_481, TestCAS_b);
ffBNcRA I242(hnl_473, hnl_454, gnd, hnl_474);
ffBNcRA I240(DAcnt_1_, hnl_482, hnl_460, testCntReset_b);
ffBNcRA I226(DAcnt_0_, hnl_482, DAcnt_0_, testCntReset_b);
not #(1) I301(cmpData, testBD_b_0_);
not #(1) I278(xor_result, hnl_483);
not #(1) I258(DAcnt_b_1_, DAcnt_1_);
not #(1) I232(rawTestWE, SInRaw_b);
not #(1) I290(TestRAS, TestRASB);
not #(1) I223(hnl_455, hnl_484);
nor #(1) U352(hnl_451, BIMDI, hnl_452);
nor #(1) U270(FailDetectOut_b, hnl_477, hnl_475);
nor #(1) U264(hnl_478, hnl_477, xor_result);
nor #(1) U259(hnl_476, hnl_475, xor_result);
nor #(1) U235(hnl_482, hnl_454, TestRAS);
nand #(1) I216(SOutClk, hnl_480, hnl_471, TestRAS);
not #(1) U339(hnl_485, powerDownMode);
not #(1) U313(hnl_56, hnl_469);
not #(1) U297(hnl_466, SerialMode);
not #(1) U294(hnl_483, hnl_463);
not #(1) U292(TestCAS_b, TestCAS);
not #(1) U288(hnl_486, chainOut_8_);
not #(1) U271(hnl_461, DAcnt_b_1_);
not #(1) U263(hnl_456, hnl_458);
not #(1) U257(hnl_459, RCRED);
not #(1) U250(SOutClk_b, SOutClk);
not #(1) U241(hnl_481, hnl_470);
nand #(1) U336(DLLByPassMode_b, hnl_485, slow);
nand #(1) U314(testCntReset_b, hnl_453, TestRASB);
nand #(1) U247(resetFailDet_b, hnl_479, DAmode);
nand #(1) U298(hnl_465, testBD_b_0_, hnl_486);
nand #(1) U282(hnl_467, DAcnt_0_, DAcnt_b_1_);
nand #(1) U277(hnl_474, TestCAS, TestRAS);
nand #(1) U265(hnl_464, chainOut_8_, cmpData);
nand #(1) U252(hnl_468, DAcnt_0_, DAcnt_1_);
nand #(1) U244(hnl_471, hnl_454, TestRAS);
nand #(1) U228(hnl_484, hnl_472, TestRAS);
nand #(1) U225(hnl_140, TestRAS, SerialMode);
endmodule

module RWDfthru (RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_);
inout RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_;
supply1 vdd;
supply0 gnd;
endmodule

module u5idA (debug, dataZA3, idhit, A3_b, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID);
output debug;
inout dataZA3, idhit;
input A3_b, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID;
supply1 vdd;
supply0 gnd;
latRA #(1) I53(debug, dataInA3, writeDeviceID, reset_b);
xnandpc2 U51(idhit, debug, evalId, A3_b);
nandpd2 U48(dataZA3, debug, readDeviceId);
endmodule

module u5MscR0 (enableRefreshMode, setRR_b, dataZ0, dataZ1, dataZ2, dataZ3, clearRE, dataIn0, dataIn3, incRfshRow_b, powerDownReq_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, setRE, writeR_7_,
writeR_3_);
output enableRefreshMode, setRR_b;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input clearRE, dataIn0, dataIn3, incRfshRow_b, powerDownReq_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, setRE, writeR_7_, writeR_3_;
supply1 vdd;
supply0 gnd;
latSRB I180(hnl_487, dataIn0, writeR_3_, hnl_488, setRE);
nor #(1) U178(hnl_488, hnl_489, clearRE, reset);
not #(1) I179(hnl_489, powerDownReq_b);
not #(1) U176(hnl_490, incRfshRow_b);
not #(1) U173(hnl_491, hnl_487);
not #(1) U174(enableRefreshMode, hnl_491);
not #(1) U172(setRR_b, hnl_492);
nor #(1) U171(clearSetRR_b, reset, hnl_490);
pdnull U164(dataZ1, readR_9_);
pdnull U163(dataZ0, readR_9_);
latRB #(1) I175(hnl_492, dataIn3, writeR_7_, clearSetRR_b);
nandpd1 U155(dataZ2, readR_9_);
nandpd1 U148(dataZ1, readR_0_);
nandpd1 U133(dataZ3, readR_2_);
nandpd1 U131(dataZ0, readR_2_);
nandpd1 U132(dataZ1, readR_2_);
nandpd2 U147(dataZ0, hnl_487, readR_3_);
endmodule

module u5bit0 (ADR_7_, Addr_0_, Addr_2_, NSWE_0_, RASoverflow_b, RfshCntCary01, RfshRwCy01, enableRefreshMode, muxBS8, setRR_b, testBD_b_0_, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, idHitB,
rfshEqualsZero, rowHitLeftA, rowHitRightA, CASctCy70, DAmode_b, NSAdr_7_, RASaddrEnable, RAScount_b, RASctCy10, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy70, clearRE,
dataIn0_0_, dataIn1_0_, dataIn2_0_, dataIn3_0_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE,
localBSEL, pd0_0_, pd1_0_, pd2_0_, pd3_0_, powerDownReq_b, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0,
restoreBank1, setRE, testBD_0_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
output ADR_7_, Addr_0_, Addr_2_, NSWE_0_, RASoverflow_b, RfshCntCary01, RfshRwCy01, enableRefreshMode, muxBS8, setRR_b, testBD_b_0_;
inout dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, idHitB, rfshEqualsZero, rowHitLeftA, rowHitRightA;
input CASctCy70, DAmode_b, NSAdr_7_, RASaddrEnable, RAScount_b, RASctCy10, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy70, clearRE, dataIn0_0_, dataIn1_0_, dataIn2_0_, dataIn3_0_,
driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, pd0_0_, pd1_0_, pd2_0_, pd3_0_,
powerDownReq_b, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setRE, testBD_0_, unloadNSWE,
updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
aoi21A #(1) F94AJ(hnl_493, gnd, gnd, gnd);
ffBarRA F94AK(hnl_494, gnd, gnd, vdd);
ltxRB F94AI(hnl_495, gnd, gnd, vdd);
ffC #(1) F94AH(hnl_496, gnd, gnd);
nand #(0) F94AE(hnl_497, gnd, gnd, gnd, gnd);
nor #(1) F94AG(hnl_498, gnd, gnd);
nor #(1) F94AF(hnl_499, gnd, gnd);
nand #(1) F94AD(hnl_500, gnd, gnd);
nand #(1) F94AC(hnl_501, gnd, gnd);
latSRB rowExpRest4(rowExpRest_4_, dataIn3_0_, writeR_6_, reset_b, gnd);
latSRB rowImpRest4(rowImpRest_4_, dataIn2_0_, writeR_6_, reset_b, gnd);
latSRB rowAcc4(rowAcc_4_, dataIn1_0_, writeR_6_, reset_b, gnd);
latSRB rowPre4(rowPre_4_, dataIn0_0_, writeR_6_, reset_b, gnd);
ltxBarB Addr0(Addr_b_0_, writeA45, pd3_0_);
ltxBarSB Addr2(A0_0_, writeA0123x, pd0_0_, reset);
latBNcA I522(packetRowAddr_7_, RASaddrEnable, packetRowAddr_b_7_);
mux71x AdrMUX7(ADR_7_, ColAdr_7_, NSAdr_7_, packetRowAddr_7_, rfshRowAddr_7_, bank0RowAddr_7_, bank1RowAddr_7_, testBD_0_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_502, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg0(NSWE_0_, selectEven_0_, loadNSWE, pd2_0_, pd3_0_, rclk, unloadNSWE);
nor #(1) U516(hnl_502, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U515(Addr_0_, Addr_b_0_);
not #(1) U513(muxBS8, hnl_503);
ffBNcRA I505(hnl_503, hnl_504, testBD_0_, DAmode);
mux41 #(1) I502(cnt4, rowPre_4_, rowAcc_4_, rowImpRest_4_, rowExpRest_4_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
not #(1) U506(hnl_504, loadDAR);
nandpd2 U501(dataZ3_0_, rowExpRest_4_, readR_6_);
nandpd2 U495(dataZ2_0_, rowImpRest_4_, readR_6_);
nandpd2 U493(dataZ1_0_, rowAcc_4_, readR_6_);
nandpd2 U489(dataZ0_0_, rowPre_4_, readR_6_);
not #(1) U470(ColAdr_7_, net1816);
not #(1) U528(RASoverflow_b, hnl_505);
not #(1) U463(testBD_b_0_, testBD_0_);
not #(1) U514(Addr_2_, A0_0_);
countup RASct4(hnl_506, RAScnt_4_, RAScount_b, RASctCy10, RASldCount, cnt4);
countup Col_7_(net1815, net1816, incColAdr_b, CASctCy70, writeA0123x, pd1_0_);
u5idA Id27(id_27_, dataZ2_0_, idHitB, partialId_b_6_, dataIn2_0_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_7_(bank0RowAddr_7_, bank1RowAddr_7_, dataZ1_0_, dataZ3_0_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_7_, packetRowAddr_b_7_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr7(adrSelReg_7_, partialId_b_6_, packetRowAddr_b_7_, dataZ1_0_, dataIn1_0_, pd2_0_, pd3_0_, readR_8_, reset_b, writeA0123, writeR_8_);
u5Rfsh0 RefCnt0(RefCount_0_, RefLoad_0_, RfshCntCary01, dataZ0_0_, dataZ2_0_, rfshEqualsZero, gnd, incRfshInterval, dataIn0_0_, dataIn2_0_, evalRfshCount, readR_4_, reset_b, writeR_4_);
u5RfshRw RfshRw7(RfshRwCy01, rfshRowAddr_7_, dataZ2_0_, RfshRwCy70, dataIn2_0_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR0 MscR0(enableRefreshMode, setRR_b, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, clearRE, dataIn0_0_, dataIn3_0_, incRfshRow_b, powerDownReq_b, readR_9_, readR_3_, readR_2_, readR_0_, reset,
setRE, writeR_7_, writeR_3_);
not #(1) U527(hnl_505, hnl_506);
not #(1) I465(DAmode, DAmode_b);
not #(1) F94AB(hnl_507, gnd);
not #(1) F94AA(hnl_508, gnd);
not #(1) U458(reset_b, reset);
endmodule

module u5CASdy2 (readDelay, writeDelay, dataZ1, dataZ3, dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_);
output readDelay, writeDelay;
inout dataZ1, dataZ3;
input dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
latSB #(1) I413(writeDelay, dataIn3, writeR_2_, reset);
latRB #(1) I396(readDelay, dataIn1, writeR_2_, reset_b);
nandpd2 U402(dataZ1, readDelay, readR_2_);
nandpd2 U395(dataZ3, writeDelay, readR_2_);
endmodule

module u5MscR5 (PDslow, ackWinDelay, dataZ0, dataZ1, dataZ3, dataIn0, readR_9_, readR_7_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeR_3_, writeR_2_);
output PDslow, ackWinDelay;
inout dataZ0, dataZ1, dataZ3;
input dataIn0, readR_9_, readR_7_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeR_3_, writeR_2_;
supply1 vdd;
supply0 gnd;
latRB #(1) I145(PDslow, dataIn0, writeR_3_, reset_b);
pdnull U144(dataZ1, readR_9_);
pdnull U143(dataZ0, readR_9_);
pdnull U142(dataZ3, readR_0_);
latSB #(1) I131(ackWinDelay, dataIn0, writeR_2_, reset);
nandpd1 U132(dataZ3, readR_7_);
nandpd1 U125(dataZ0, readR_0_);
nandpd2 U148(dataZ0, PDslow, readR_3_);
nandpd2 U127(dataZ0, ackWinDelay, readR_2_);
endmodule

module u5bit5 (ADR_4_, CASctCy56, DAR_4_, NSWE_5_, PDslow, RfshCntCary56, RfshRwCy56, XferCntBorw56, ackWinDelay_2_, partialId_b_3_, pd2_5_, readDelay_2_, setDAR, writeDelay_2_, xcnt4321, dataZ0_5_,
dataZ1_5_, dataZ2_5_, dataZ3_5_, idHitA, rfshEqualsZero, rowHitLeftB, rowHitRightB, CASctCy45, DAmode_b, NSAdr_4_, RASaddrEnable, RfshCntCary45, RfshRwCy45, XferCntBorw45, dataIn0_5_, dataIn1_5_,
dataIn2_5_, dataIn3_5_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL,
partialId_b_2_, pd0_5_, pd1_5_, pd2_6_, pd3_5_, rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1,
testBD_6_, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_2_, writeR_1_, xcnt_b_4_, xcnt_b_3_);
output ADR_4_, CASctCy56, DAR_4_, NSWE_5_, PDslow, RfshCntCary56, RfshRwCy56, XferCntBorw56, ackWinDelay_2_, partialId_b_3_, pd2_5_, readDelay_2_, setDAR, writeDelay_2_, xcnt4321;
inout dataZ0_5_, dataZ1_5_, dataZ2_5_, dataZ3_5_, idHitA, rfshEqualsZero, rowHitLeftB, rowHitRightB;
input CASctCy45, DAmode_b, NSAdr_4_, RASaddrEnable, RfshCntCary45, RfshRwCy45, XferCntBorw45, dataIn0_5_, dataIn1_5_, dataIn2_5_, dataIn3_5_, decXferCnt_b, driveColAdr, driveNSAdr,
drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_2_, pd0_5_, pd1_5_, pd2_6_, pd3_5_, rclk, readR_10_,
readR_9_, readR_8_, readR_7_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_6_, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123,
writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_2_, writeR_1_, xcnt_b_4_, xcnt_b_3_;
supply1 vdd;
supply0 gnd;
ltxBarB Addr32(Addr_32_, writeA0123, pd3_5_);
latBNcA I566(packetRowAddr_4_, RASaddrEnable, packetRowAddr_b_4_);
mux71x AdrMUX4(ADR_4_, ColAdr_4_, NSAdr_4_, packetRowAddr_4_, rfshRowAddr_4_, bank0RowAddr_4_, bank1RowAddr_4_, testBD_6_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_509, restoreBank0,
restoreBank1, DAmode);
nand #(0) U561(hnl_510, xcnt_b_1_, xcnt_b_2_, xcnt_b_3_, xcnt_b_4_);
u5NSWErg NSWErg5(NSWE_5_, selectEven_5_, loadNSWE, pd2_5_, pd3_5_, rclk, unloadNSWE);
not #(1) I544(DAmode, DAmode_b);
nor #(1) I540(hnl_509, driveRfshAddr_b, restoreBank0, restoreBank1);
u5id Id23_32(id_32_, id_23_, dataZ0_5_, dataZ2_5_, idHitA, partialId_b_2_, Addr_32_, dataIn0_5_, dataIn2_5_, eval, readR_1_, reset_b, writeR_1_);
u5DARbit DARbit4(DAR_4_, loadDAR, DAmode, setDAR, testBD_6_);
not #(1) U510(ColAdr_4_, net533);
countdn Count5(XferCntBorw56, xcnt_b_2_, decXferCnt_b, n8, writeA45, pd3_5_);
countdn Count4(n8, xcnt_b_1_, decXferCnt_b, XferCntBorw45, writeA45, pd2_5_);
countup Col_4_(CASctCy56, net533, incColAdr_b, CASctCy45, writeA0123x, pd0_5_);
u5Rhit Rhit_4_(bank0RowAddr_4_, bank1RowAddr_4_, dataZ0_5_, dataZ2_5_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_4_, packetRowAddr_b_4_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr4(adrSelReg_4_, partialId_b_3_, packetRowAddr_b_4_, dataZ0_5_, dataIn0_5_, pd1_5_, pd2_6_, readR_8_, reset_b, writeA0123, writeR_8_);
u5Rfsh1 RefCnt5(RefCount_5_, RefLoad_5_, RfshCntCary56, dataZ0_5_, dataZ2_5_, rfshEqualsZero, RfshCntCary45, incRfshInterval, dataIn0_5_, dataIn2_5_, evalRfshCount, readR_4_, reset, reset_b,
writeR_4_);
u5RfshRw RfshRw4(RfshRwCy56, rfshRowAddr_4_, dataZ0_5_, RfshRwCy45, dataIn0_5_, incRfshRow_b, readR_5_, writeR_5_);
u5CASdy2 CASdy2(readDelay_2_, writeDelay_2_, dataZ1_5_, dataZ3_5_, dataIn1_5_, dataIn3_5_, readR_2_, reset, reset_b, writeR_2_);
u5MscR5 MscR5(PDslow, ackWinDelay_2_, dataZ0_5_, dataZ1_5_, dataZ3_5_, dataIn0_5_, readR_9_, readR_7_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeR_3_, writeR_2_);
not #(1) U519(hnl_511, testBD_7_);
not #(1) I562(xcnt4321, hnl_510);
not #(1) U513(setDAR, hnl_511);
not #(1) U505(reset_b, reset);
endmodule

module u5RstCtr (PD64after, clearCount_b, endPowerDown_b, reset, resetDAmode_b, turboDLL_b, DAmode_b, PDreq2, PDslow, PON, Rx_2, rawBE_b);
output PD64after, clearCount_b, endPowerDown_b, reset, resetDAmode_b, turboDLL_b;
input DAmode_b, PDreq2, PDslow, PON, Rx_2, rawBE_b;
supply1 vdd;
supply0 gnd;
not #(1) U258(reset_b, hnl_512);
invFF U257(reset, reset_b);
nor #(1) U251(hnl_513, PD64after, PDreq2_b, forceCounting_b);
nand #(1) U260(hnl_514, PON, PON);
nand #(1) U249(clearCount, hnl_515, PON);
not #(1) U261(resetDAmode_b, hnl_514);
not #(1) U246(endPowerDown_b, hnl_516);
not #(1) U252(turboDLL_b, hnl_513);
not #(1) U247(clearCount_b, clearCount);
not #(1) U245(PD64after, hnl_517);
nor #(1) U242(hnl_136, Rx_512, PDreq2_b);
srff I250(hnl_517, PDreq2, hnl_518);
srff I241(forceCounting_b, hnl_136, endPowerDown_b);
nand #(1) U259(countEq224_b, Rx_256, Rx_128, Rx_64);
nand #(1) U238(countEq76_b, Rx_128, Rx_16, Rx_8);
not #(1) U239(Rx_512_b, Rx_512);
not #(1) U230(PDreq2_b, PDreq2);
not #(1) U229(localClearCount_b, clearCount);
nand #(1) U240(hnl_515, rawBE_b, forceCounting_b);
oai21A U227(hnl_516, clearCount, finishPowerDown_b, reset_b);
mux21 #(1) I237(finishPowerDown_b, countEq12_b, countEq160_b, PDslow);
mux21 #(1) I221(hnl_518, countEq76_b, countEq224_b, PDslow);
ffBNcRA I214(Rx_512, Rx_256, Rx_512, localClearCount_b);
ffBNcRA I213(Rx_256, Rx_128, Rx_256, localClearCount_b);
ffBNcRA I212(Rx_128, Rx_64, Rx_128, localClearCount_b);
ffBNcRA I211(Rx_64, Rx_32, Rx_64, localClearCount_b);
ffBNcRA I210(Rx_32, Rx_16, Rx_32, localClearCount_b);
ffBNcRA I209(Rx_16, Rx_8, Rx_16, localClearCount_b);
ffBNcRA I208(Rx_8, Rx_4, Rx_8, localClearCount_b);
ffBNcRA I207(Rx_4, Rx_2, Rx_4, localClearCount_b);
nand #(1) U197(hnl_512, Rx_512_b, PON, DAmode_b);
nand #(1) U226(countEq160_b, Rx_256, Rx_64);
nand #(1) U224(countEq12_b, Rx_16, Rx_8);
endmodule

module u5BEminC (standby, stbybWak, DLLByPassMode_b, DeviceBusy, clockedBE_b, mclk, powerDownMode, rclk, rdPipeBusy_b, reset_b, trueEvalRfshCount);
output standby, stbybWak;
input DLLByPassMode_b, DeviceBusy, clockedBE_b, mclk, powerDownMode, rclk, rdPipeBusy_b, reset_b, trueEvalRfshCount;
supply1 vdd;
supply0 gnd;
nand #(1) U220(stbybWak, clockedBE_b, trueEvalRfshCount, hnl_519);
nand #(1) I215(ksink, clockedBE_b, reset_b, trueEvalRfshCount);
not #(1) U243(hnl_520, powerDownMode);
ffSB I233(wake, rclk, hnl_481, ksink);
ffRA I209(standby_b, mclk, reset_b, hnl_47);
nor #(1) I228(hnl_521, ksink, wake);
nor #(1) U226(hnl_519, hnl_522, wake);
not #(1) U222(wake_b, wake);
ffB #(1) I219(BEm4, rclk, hnl_523);
not #(1) U214(standby, standby_b);
nand #(1) I212(hnl_47, rdPipeBusy_b, countIs15or0, wake_b);
oai21A U211(hnl_523, countIs15or0, hnl_524, hnl_521);
ffBarA #(1) I208(BEm3, rclk, hnl_512);
xor #(1) U203(hnl_524, BEm3, BEm4);
nor #(1) U199(countIs15or0, BEm4, BEm1, BEm2);
nand #(1) U241(hnl_481, hnl_482, hnl_136);
nand #(1) U235(hnl_482, countIs15or0, wake);
nand #(1) U221(hnl_525, wake_b, BEm1);
nand #(1) U198(hnl_526, wake_b, BEm4);
nand #(1) U197(hnl_512, wake_b, BEm2);
nand #(1) U242(hnl_136, hnl_520, DeviceBusy);
nand #(1) I227(hnl_522, DLLByPassMode_b, standby);
ffBarB #(1) I195(BEm1, rclk, hnl_526);
ffBarB #(1) I194(BEm2, rclk, hnl_525);
endmodule

module u5PreScl (PreScx_b, evalRfshCount, evalRfshCount_b, incRfshInterval, decXferCnt_b, enableRefreshMode, mclk, rclk, reset);
output PreScx_b, evalRfshCount, evalRfshCount_b, incRfshInterval;
input decXferCnt_b, enableRefreshMode, mclk, rclk, reset;
supply1 vdd;
supply0 gnd;
nand #(1) U283(hnl_527, q0, clear_b);
nor #(1) U187(hnl_528, hnl_527, hnl_488);
nand #(1) U280(preRsh, q2, q1, hnl_528);
ffRC I278(q0, mclk, clear_b, hnl_128);
invEE U264(incRfshInterval, hnl_529);
ffA I261(hnl_530, evalRfshCount_b, mclk);
ffBarB #(1) I239(n2, rclk, n1);
not #(1) U188(clear_b, clear);
ffB #(1) I238(n1, rclk, latchedEnRfsh);
invFF U256(evalRfshCount, evalRfshCount_b);
ffBarD I241(evalRfshCount_b, mclk, preRsh);
oai21A U196(clear, n1, n2, reset_b);
ffC #(1) I282(hnl_529, mclk, hnl_50);
ffC #(1) I243(PreScx_b, mclk, hnl_530);
nand #(0) U178(hnl_488, q3, q5, q6, q7);
nand #(0) U281(hnl_50, hnl_528, q1, q2, enableRefreshMode);
not #(1) U279(hnl_128, q0);
not #(1) U277(hnl_474, decXferCnt_b);
not #(1) U244(reset_b, reset);
latBarSB #(1) I247(latchedEnRfsh, enableRefreshMode, hnl_474, reset);
latBarSB #(1) I175(q5, hnl_531, q4, clear2);
latBarSB #(1) I193(q1, hnl_532, q0, clear);
latBarSB #(1) I189(q3, hnl_533, q2, clear2);
latNBarA #(1) I198(hnl_532, hnl_534, q0);
latNBarA #(1) I192(hnl_531, hnl_535, q4);
latNBarA #(1) I195(q7, hnl_487, q6);
latNBarA #(1) I197(q2, q1, q0);
latNBarA #(1) I182(q6, q5, q4);
latNBarA #(1) I199(q4, q3, q2);
latNBarA #(1) I183(hnl_533, hnl_536, q2);
latSA #(1) I201(hnl_535, q6, q4, clear2);
latSA #(1) I202(hnl_536, q4, q2, clear2);
latSA #(1) I176(hnl_534, q2, q0, clear);
latSA #(1) I180(hnl_487, q7, q6, clear2);
srff I177(clear2, clear_b, q1);
endmodule

module u5BElog (PD64after, PreScx_b, clearCount_b, endPowerDown_b, evalRfshCount, incRfshInterval, reset, resetDAmode_b, standby, stbybWak, turboDLL_b, DAmode_b, DLLByPassMode_b, DeviceBusy, PDreq2,
PDslow, PON, Rx_2, clockedBE_b, decXferCnt_b, enableRefreshMode, mclk, powerDownMode, rawBE_b, rclk, rdPipeBusy_b);
output PD64after, PreScx_b, clearCount_b, endPowerDown_b, evalRfshCount, incRfshInterval, reset, resetDAmode_b, standby, stbybWak, turboDLL_b;
input DAmode_b, DLLByPassMode_b, DeviceBusy, PDreq2, PDslow, PON, Rx_2, clockedBE_b, decXferCnt_b, enableRefreshMode, mclk, powerDownMode, rawBE_b, rclk, rdPipeBusy_b;
supply1 vdd;
supply0 gnd;
nor #(1) F94CE(hnl_537, gnd, gnd);
not #(1) F94CB(hnl_538, gnd);
not #(1) F94CA(hnl_539, gnd);
nand #(1) F94CD(hnl_540, gnd, gnd);
nand #(1) F94CC(hnl_541, gnd, gnd);
nand #(1) U85(hnl_542, hnl_543, enableRefreshMode);
u5RstCtr RstCtr(PD64after, clearCount_b, endPowerDown_b, reset, resetDAmode_b, turboDLL_b, DAmode_b, PDreq2, PDslow, PON, Rx_2, rawBE_b);
u5BEminC BEminC(standby, stbybWak, DLLByPassMode_b, DeviceBusy, clockedBE_b, mclk, powerDownMode, rclk, rdPipeBusy_b, reset_b, hnl_542);
u5PreScl PreScl(PreScx_b, evalRfshCount, hnl_543, incRfshInterval, decXferCnt_b, enableRefreshMode, mclk, rclk, reset);
not #(1) U71(reset_b, reset);
endmodule

module u5WEgen (ADRx_6_, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, earlyDone, loadNSWE, ADR_6_, Addr_2_, Addr_1_, Addr_0_, CASstate1_b, Count_2_, Count_1_, Count_0_, DAmode_b, Last_b,
NSOp, NSWE_7_, NSWE_6_, NSWE_5_, NSWE_4_, NSWE_3_, NSWE_2_, NSWE_1_, NSWE_0_, RASB, RawLast, TestWE, firstCycWE_b, loadLast, preloadNSWE, rclk, regOp, reset, trueCASstate1_b, writeA0123x,
writeMaskedNSOp_b, writeOp_b, xcnt4321, xcnt_b_0_);
output ADRx_6_, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, earlyDone, loadNSWE;
input ADR_6_, Addr_2_, Addr_1_, Addr_0_, CASstate1_b, Count_2_, Count_1_, Count_0_, DAmode_b, Last_b, NSOp, NSWE_7_, NSWE_6_, NSWE_5_, NSWE_4_, NSWE_3_, NSWE_2_, NSWE_1_, NSWE_0_, RASB, RawLast,
TestWE, firstCycWE_b, loadLast, preloadNSWE, rclk, regOp, reset, trueCASstate1_b, writeA0123x, writeMaskedNSOp_b, writeOp_b, xcnt4321, xcnt_b_0_;
supply1 vdd;
supply0 gnd;
ltxRB F94BD(hnl_544, gnd, gnd, vdd);
nand #(0) F94BA(hnl_545, gnd, gnd, gnd, gnd);
nor #(1) F94BC(hnl_546, gnd, gnd);
nor #(1) F94BB(hnl_547, gnd, gnd);
nand #(1) F94AZ(hnl_548, gnd, gnd);
nand #(1) F94AY(hnl_549, gnd, gnd);
not #(1) F94AX(hnl_550, gnd);
not #(1) F94AW(hnl_551, gnd);
nor #(1) U320(hnl_552, writeA0123x, reset, RASB);
aoi21A #(1) U339(hnl_485, xcnt_b_0_, xcnt4321, regOp);
ffA I341(hnl_553, hnl_552, rclk);
ffA I328(hnl_554, hnl_485, rclk);
oai21A U318(hnl_555, CASstate1_b, Last_b, hnl_556);
ffRC I317(earlyDone, rclk, hnl_553, hnl_557);
invFF U314(loadNSWE, preloadNSWE);
not #(1) U311(ADRx_6_, hnl_558);
nor #(1) U305(hnl_559, NSOp, writeOp_b);
not #(1) U304(lastMaskEnable, hnl_560);
nand #(1) U303(hnl_560, xcnt_b_0_, xcnt4321, hnl_559);
ffC #(1) I297(firstMaskEnable, rclk, hnl_561);
nor #(1) I288(hnl_561, firstCycWE_b, NSOp, writeOp_b);
DAff I286_0_(ubWE_7_, rclk, assertWE, net1266_0_, DAmode_b);
DAff I286_1_(ubWE_6_, rclk, assertWE, net1266_1_, DAmode_b);
DAff I286_2_(ubWE_5_, rclk, assertWE, net1266_2_, DAmode_b);
DAff I286_3_(ubWE_4_, rclk, assertWE, net1266_3_, DAmode_b);
DAff I286_4_(ubWE_3_, rclk, assertWE, net1266_4_, DAmode_b);
DAff I286_5_(ubWE_2_, rclk, assertWE, net1266_5_, DAmode_b);
DAff I286_6_(ubWE_1_, rclk, assertWE, net1266_6_, DAmode_b);
DAff I286_7_(ubWE_0_, rclk, assertWE, net1266_7_, DAmode_b);
nand #(1) U327(hnl_562, Last_b, hnl_36, hnl_554);
nand #(1) U298(hnl_465, Count_2_, Count_1_, Count_0_);
nand #(1) U283(hnl_527, Addr_b_2_, Addr_b_1_, Addr_b_0_);
not #(1) U262(assertWE, hnl_563);
not #(1) U280_0_(WE_7_, ubWE_7_);
not #(1) U280_1_(WE_6_, ubWE_6_);
not #(1) U280_2_(WE_5_, ubWE_5_);
not #(1) U280_3_(WE_4_, ubWE_4_);
not #(1) U280_4_(WE_3_, ubWE_3_);
not #(1) U280_5_(WE_2_, ubWE_2_);
not #(1) U280_6_(WE_1_, ubWE_1_);
not #(1) U280_7_(WE_0_, ubWE_0_);
mux21 #(1) I319(hnl_557, hnl_562, hnl_555, trueCASstate1_b);
mux21 #(1) I261_0_(net1266_0_, NSWE_7_, rawWE_b_7_, writeMaskedNSOp_b);
mux21 #(1) I261_1_(net1266_1_, NSWE_6_, rawWE_b_6_, writeMaskedNSOp_b);
mux21 #(1) I261_2_(net1266_2_, NSWE_5_, rawWE_b_5_, writeMaskedNSOp_b);
mux21 #(1) I261_3_(net1266_3_, NSWE_4_, rawWE_b_4_, writeMaskedNSOp_b);
mux21 #(1) I261_4_(net1266_4_, NSWE_3_, rawWE_b_3_, writeMaskedNSOp_b);
mux21 #(1) I261_5_(net1266_5_, NSWE_2_, rawWE_b_2_, writeMaskedNSOp_b);
mux21 #(1) I261_6_(net1266_6_, NSWE_1_, rawWE_b_1_, writeMaskedNSOp_b);
mux21 #(1) I261_7_(net1266_7_, NSWE_0_, rawWE_b_0_, writeMaskedNSOp_b);
nand #(0) I282(Mask_6_, Addr_2_, Addr_1_, Addr_0_, firstMaskEnable);
nand #(0) I258(Mask_9_, Count_b_2_, Count_b_1_, Count_b_0_, lastMaskEnable);
not #(1) U323(hnl_556, earlyDone);
not #(1) U310(hnl_558, ADR_6_);
not #(1) U309(rawWE_b_7_, Mask_15_);
not #(1) U307(hnl_563, TestWE);
not #(1) U289(rawWE_b_0_, Mask_0_);
not #(1) U295_0_(Addr_b_2_, Addr_2_);
not #(1) U295_1_(Addr_b_1_, Addr_1_);
not #(1) U295_2_(Addr_b_0_, Addr_0_);
not #(1) U255_0_(Count_b_2_, Count_2_);
not #(1) U255_1_(Count_b_1_, Count_1_);
not #(1) U255_2_(Count_b_0_, Count_0_);
nand #(1) U330(hnl_36, loadLast, RawLast);
nand #(1) U300(rawWE_b_1_, Mask_9_, Mask_1_);
nand #(1) U293(rawWE_b_4_, Mask_12_, Mask_4_);
nand #(1) U292(hnl_564, Addr_b_2_, Addr_b_0_);
nand #(1) U287(hnl_565, Count_1_, Count_0_);
nand #(1) U285(rawWE_b_5_, Mask_13_, Mask_5_);
nand #(1) U278(hnl_130, Count_2_, Count_0_);
nand #(1) U273(hnl_566, Count_2_, Count_1_);
nand #(1) U269(rawWE_b_6_, Mask_14_, Mask_6_);
nand #(1) U267(hnl_567, Addr_b_1_, Addr_b_0_);
nand #(1) U266(rawWE_b_2_, Mask_10_, Mask_2_);
nand #(1) U265(hnl_464, Addr_b_2_, Addr_b_1_);
nand #(1) U259(rawWE_b_3_, Mask_11_, Mask_3_);
nand #(1) I302(Mask_14_, hnl_566, lastMaskEnable);
nand #(1) I299(Mask_1_, hnl_464, firstMaskEnable);
nand #(1) I291(Mask_0_, hnl_527, firstMaskEnable);
nand #(1) I275(Mask_15_, hnl_465, lastMaskEnable);
nand #(1) I253(Mask_3_, Addr_2_, firstMaskEnable);
nand #(1) I251(Mask_12_, Count_b_2_, lastMaskEnable);
nand #(1) I277(Mask_10_, Count_b_2_, Count_b_1_, lastMaskEnable);
nand #(1) I274(Mask_4_, hnl_567, Addr_2_, firstMaskEnable);
nand #(1) I263(Mask_13_, hnl_566, hnl_130, lastMaskEnable);
nand #(1) I257(Mask_11_, hnl_565, Count_b_2_, lastMaskEnable);
nand #(1) I250(Mask_2_, hnl_464, hnl_564, firstMaskEnable);
nand #(1) I248(Mask_5_, Addr_2_, Addr_1_, firstMaskEnable);
endmodule

module bufEE (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) I17(hnl_33, A);
not #(1) U9(Y, hnl_33);
endmodule

module u5MscR2 (autoSkipEn, powerDownReq_b, dataZ0, dataZ1, dataZ2, dataZ3, dataIn0, dataIn3, endPowerDown_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, writeR_7_, writeR_3_);
output autoSkipEn, powerDownReq_b;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn0, dataIn3, endPowerDown_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, writeR_7_, writeR_3_;
supply1 vdd;
supply0 gnd;
nandpd2 U166(dataZ0, autoSkipEn, readR_3_);
latSB #(1) I162(autoSkipEn, dataIn0, writeR_3_, reset);
pdnull U126(dataZ3, readR_2_);
pdnull U125(dataZ1, readR_2_);
pdnull U161(dataZ1, readR_9_);
pdnull U160(dataZ0, readR_9_);
not #(1) U142(powerDownReq_b, powerDownReq);
latRB #(1) I129(powerDownReq, dataIn3, writeR_7_, endPowerDown_b);
nandpd1 U138(dataZ2, readR_9_);
nandpd1 U225(dataZ0, readR_0_);
endmodule

module u5bit2 (ADR_1_, BSEL, CASctCy23, Count_0_, DAR_1_, NSWE_2_, RASctCy21, RfshCntCary23, RfshRwCy23, autoSkipEn, localBSEL, packetBSELx, partialId_b_0_, pd2_2_, powerDownReq_b, rfshCout_1_,
dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, idHitB, rfshEqualsZero, rowHitLeftA, rowHitRightA, CASctCy12, DAmode_b, NSAdr_1_, RASaddrEnable, RAScount_b, RASctCy32, RASldCount, RASsel_3_, RASsel_2_,
RASsel_1_, RASsel_0_, RfshCntCary12, RfshRwCy12, dataIn0_2_, dataIn1_2_, dataIn2_2_, dataIn3_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, endPowerDown_b, eval, evalRfshCount,
incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, packetBSEL, pd0_2_, pd1_2_, pd2_3_, pd3_2_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_,
readR_1_, readR_0_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_3_, testBSEL, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_,
writeR_4_, writeR_3_, writeR_1_);
output ADR_1_, BSEL, CASctCy23, Count_0_, DAR_1_, NSWE_2_, RASctCy21, RfshCntCary23, RfshRwCy23, autoSkipEn, localBSEL, packetBSELx, partialId_b_0_, pd2_2_, powerDownReq_b, rfshCout_1_;
inout dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, idHitB, rfshEqualsZero, rowHitLeftA, rowHitRightA;
input CASctCy12, DAmode_b, NSAdr_1_, RASaddrEnable, RAScount_b, RASctCy32, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary12, RfshRwCy12, dataIn0_2_, dataIn1_2_, dataIn2_2_,
dataIn3_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, endPowerDown_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, packetBSEL, pd0_2_,
pd1_2_, pd2_3_, pd3_2_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_3_,
testBSEL, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
latSRB rowExpRest2(rowExpRest_2_, dataIn3_2_, writeR_6_, vdd, reset);
latSRB rowImpRest2(rowImpRest_2_, dataIn2_2_, writeR_6_, vdd, reset);
latSRB rowAcc2(rowAcc_2_, dataIn1_2_, writeR_6_, reset_b, gnd);
latSRB rowPre2(rowPre_2_, dataIn0_2_, writeR_6_, reset_b, gnd);
ltxBarB Count0(Count_b_0_, writeA45, pd3_2_);
ltxBarB Addr29(Addr_29_, writeA0123, pd3_2_);
latBNcA I577(packetRowAddr_1_, RASaddrEnable, packetRowAddr_b_1_);
mux71x AdrMUX1(ADR_1_, ColAdr_1_, NSAdr_1_, packetRowAddr_1_, rfshRowAddr_1_, bank0RowAddr_1_, bank1RowAddr_1_, testBD_3_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_568, restoreBank0,
restoreBank1, DAmode);
mux71x BSMUX(BSEL, hnl_106, hnl_106, hnl_106, rfshBSEL, gnd, vdd, testBSEL, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_568, restoreBank0, restoreBank1, DAmode);
u5NSWErg NSWErg2(NSWE_2_, selectEven_2_, loadNSWE, pd2_2_, pd3_2_, rclk, unloadNSWE);
bufEE U571(packetBSELx, hnl_569);
mux21 #(1) I569(hnl_569, hnl_394, hnl_570, driveRfshAddr_b);
not #(1) I557(DAmode, DAmode_b);
nor #(1) I553(hnl_568, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U549(rfshCout_1_, RfshRwCy23);
not #(1) U547(Count_0_, Count_b_0_);
invEEbuf U545(localBSEL, hnl_61);
mux41 #(1) I537(cnt2, rowPre_2_, rowAcc_2_, rowImpRest_2_, rowExpRest_2_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
nandpd2 U524(dataZ0_2_, rowPre_2_, readR_6_);
nandpd2 U536(dataZ3_2_, rowExpRest_2_, readR_6_);
nandpd2 U530(dataZ2_2_, rowImpRest_2_, readR_6_);
nandpd2 U528(dataZ1_2_, rowAcc_2_, readR_6_);
u5DARbit DARbit1(DAR_1_, loadDAR, DAmode, setDAR, testBD_3_);
latB I572(hnl_394, rfshBSEL, driveRfshAddr_b);
latB I570(hnl_570, packetBSEL, writeA45);
latB I508(hnl_106, packetBSEL, writeA45);
not #(1) U550(ColAdr_1_, net3394);
countup RASct2(RASctCy21, RAScnt_2_, RAScount_b, RASctCy32, RASldCount, cnt2);
countup Col_1_(CASctCy23, net3394, incColAdr_b, CASctCy12, writeA0123x, pd0_2_);
u5idA Id29(id_29_, dataZ2_2_, idHitB, Addr_29_, dataIn2_2_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_1_(bank0RowAddr_1_, bank1RowAddr_1_, dataZ0_2_, dataZ2_2_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_1_, packetRowAddr_b_1_, readR_10_, reset_b, updateRowAddr);
u5Rfsh1 RefCnt2(RefCount_2_, RefLoad_2_, RfshCntCary23, dataZ0_2_, dataZ2_2_, rfshEqualsZero, RfshCntCary12, incRfshInterval, dataIn0_2_, dataIn2_2_, evalRfshCount, readR_4_, reset, reset_b,
writeR_4_);
u5RASadr RASadr1(adrSelReg_1_, partialId_b_0_, packetRowAddr_b_1_, dataZ0_2_, dataIn0_2_, pd1_2_, pd2_3_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw1(RfshRwCy23, rfshRowAddr_1_, dataZ0_2_, RfshRwCy12, dataIn0_2_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR2 MscR2(autoSkipEn, powerDownReq_b, dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, dataIn0_2_, dataIn3_2_, endPowerDown_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, writeR_7_, writeR_3_);
not #(1) U575(hnl_61, BSEL);
not #(1) U463(reset_b, reset);
endmodule

module u5MscR6 (control_6_, control_2_, control_1_, control_0_, dataZ0, dataZ1, dataZ2, dataZ3, dataIn0, dataIn1, dataIn2, dataIn3, ictrl_2_, ictrl_1_, ictrl_0_, readR_9_, readR_7_, readR_3_,
readR_0_, reset, writeR_3_);
output control_6_, control_2_, control_1_, control_0_;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn0, dataIn1, dataIn2, dataIn3, ictrl_2_, ictrl_1_, ictrl_0_, readR_9_, readR_7_, readR_3_, readR_0_, reset, writeR_3_;
supply1 vdd;
supply0 gnd;
pdnull U148(dataZ1, readR_9_);
pdnull U147(dataZ0, readR_9_);
pdnull U146(dataZ3, readR_0_);
latBarSB #(1) I143_0_(control_6_, dataIn0, writeR_3_, reset);
latBarSB #(1) I143_1_(control_2_, dataIn1, writeR_3_, reset);
latBarSB #(1) I143_2_(control_1_, dataIn2, writeR_3_, reset);
latBarSB #(1) I143_3_(control_0_, dataIn3, writeR_3_, reset);
nandpd1 U150(dataZ3, readR_7_);
nandpd1 U149(dataZ2, readR_7_);
nandpd1 U136(dataZ1, readR_7_);
nandpd2 U130_0_(dataZ1, ictrl_2_, readR_3_);
nandpd2 U130_1_(dataZ2, ictrl_1_, readR_3_);
nandpd2 U130_2_(dataZ3, ictrl_0_, readR_3_);
nandpd2 U263(dataZ0, control_6_, readR_3_);
endmodule

module u5bit6 (ADR_5_, CASctCy67, NSWE_6_, RfshCntCary67, RfshRwCy67, control_6_, control_2_, control_1_, control_0_, partialId_b_4_, pd2_6_, xcnt_b_4_, xcnt_b_3_, dataZ0_6_, dataZ1_6_, dataZ2_6_,
dataZ3_6_, idHitA, rfshEqualsZero, rowHitLeftB, rowHitRightB, CASctCy56, DAmode_b, NSAdr_5_, RASaddrEnable, RfshCntCary56, RfshRwCy56, XferCntBorw56, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_,
decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, ictrl_2_, ictrl_1_, ictrl_0_, incColAdr_b, incRfshInterval, incRfshRow_b, loadNSWE, localBSEL,
partialId_b_3_, pd0_6_, pd1_6_, pd2_7_, pd3_6_, rclk, readR_5_, readR_4_, readR_3_, readR_1_, readR_0_, readR_10_, readR_9_, readR_8_, readR_7_, reset, restoreBank0, restoreBank1, testBD_7_,
unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
output ADR_5_, CASctCy67, NSWE_6_, RfshCntCary67, RfshRwCy67, control_6_, control_2_, control_1_, control_0_, partialId_b_4_, pd2_6_, xcnt_b_4_, xcnt_b_3_;
inout dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_, idHitA, rfshEqualsZero, rowHitLeftB, rowHitRightB;
input CASctCy56, DAmode_b, NSAdr_5_, RASaddrEnable, RfshCntCary56, RfshRwCy56, XferCntBorw56, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_, decXferCnt_b, driveColAdr, driveNSAdr,
drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, ictrl_2_, ictrl_1_, ictrl_0_, incColAdr_b, incRfshInterval, incRfshRow_b, loadNSWE, localBSEL, partialId_b_3_, pd0_6_, pd1_6_, pd2_7_,
pd3_6_, rclk, readR_5_, readR_4_, readR_3_, readR_1_, readR_0_, readR_10_, readR_9_, readR_8_, readR_7_, reset, restoreBank0, restoreBank1, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123,
writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
ltxBarB Addr33(Addr_33_, writeA0123, pd3_6_);
latBNcA I551(packetRowAddr_5_, RASaddrEnable, packetRowAddr_b_5_);
mux71x AdrMUX5(ADR_5_, ColAdr_5_, NSAdr_5_, packetRowAddr_5_, rfshRowAddr_5_, bank0RowAddr_5_, bank1RowAddr_5_, testBD_7_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_571, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg6(NSWE_6_, selectEven_6_, loadNSWE, pd2_6_, pd3_6_, rclk, unloadNSWE);
not #(1) I535(DAmode, DAmode_b);
nor #(1) I531(hnl_571, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U504(ColAdr_5_, net186);
countdn Count7(hnl_572, xcnt_b_4_, decXferCnt_b, n8, writeA45, pd3_6_);
countdn Count6(n8, xcnt_b_3_, decXferCnt_b, XferCntBorw56, writeA45, pd2_6_);
countup Col_5_(CASctCy67, net186, incColAdr_b, CASctCy56, writeA0123x, pd0_6_);
u5id Id24_33(id_33_, id_24_, dataZ0_6_, dataZ2_6_, idHitA, partialId_b_3_, Addr_33_, dataIn0_6_, dataIn2_6_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_5_(bank0RowAddr_5_, bank1RowAddr_5_, dataZ0_6_, dataZ2_6_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_5_, packetRowAddr_b_5_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr5(adrSelReg_5_, partialId_b_4_, packetRowAddr_b_5_, dataZ0_6_, dataIn0_6_, pd1_6_, pd2_7_, readR_8_, reset_b, writeA0123, writeR_8_);
u5Rfsh0 RefCnt6(RefCount_6_, RefLoad_6_, RfshCntCary67, dataZ0_6_, dataZ2_6_, rfshEqualsZero, RfshCntCary56, incRfshInterval, dataIn0_6_, dataIn2_6_, evalRfshCount, readR_4_, reset_b, writeR_4_);
u5RfshRw RfshRw5(RfshRwCy67, rfshRowAddr_5_, dataZ0_6_, RfshRwCy56, dataIn0_6_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR6 MscR6(control_6_, control_2_, control_1_, control_0_, dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_, ictrl_2_, ictrl_1_, ictrl_0_, readR_9_,
readR_7_, readR_3_, readR_0_, reset, writeR_3_);
not #(1) U499(reset_b, reset);
endmodule

module u5MscR1 (clearRE, deviceEnableMode, dataZ0, dataZ1, dataZ2, dataZ3, dataIn0, dataIn3, readR_9_, readR_3_, readR_2_, reset, reset_b, writeA0123x, writeR_7_, writeR_3_);
output clearRE, deviceEnableMode;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn0, dataIn3, readR_9_, readR_3_, readR_2_, reset, reset_b, writeA0123x, writeR_7_, writeR_3_;
supply1 vdd;
supply0 gnd;
nor #(1) U156(hnl_573, writeA0123x, reset);
not #(1) U153(deviceEnableMode, hnl_574);
not #(1) U152(hnl_574, hnl_575);
pdnull U151(dataZ1, readR_9_);
pdnull U150(dataZ0, readR_9_);
latRB #(1) I154(clearRE, dataIn3, writeR_7_, hnl_573);
latRB #(1) I132(hnl_575, dataIn0, writeR_3_, reset_b);
nandpd1 U162(dataZ1, readR_2_);
nandpd1 U161(dataZ3, readR_2_);
nandpd1 U129(dataZ2, readR_2_);
nandpd1 U128(dataZ0, readR_2_);
nandpd2 U131(dataZ0, hnl_575, readR_3_);
endmodule

module u5bit1 (ADR_8_, ADR_0_, Addr_1_, CASctCy12, DAR_0_, NSWE_1_, RASctCy10, RfshCntCary12, RfshRwCy12, clearRE, deviceEnableMode, packetBSEL, testBSEL, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_,
idHitB, rfshEqualsZero, rowHitLeftA, rowHitRightA, BIMDI, DAmode_b, NSAdr_0_, RASaddrEnable, RAScount_b, RASctCy21, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary01, RfshRwCy01,
dataIn0_1_, dataIn1_1_, dataIn2_1_, dataIn3_1_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE,
localBSEL, muxBS8, pd0_1_, pd1_1_, pd2_1_, pd2_2_, pd3_1_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, reset, restoreBank0, restoreBank1,
rfshBSEL, setDAR, testBD_1_, testBD_2_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
output ADR_8_, ADR_0_, Addr_1_, CASctCy12, DAR_0_, NSWE_1_, RASctCy10, RfshCntCary12, RfshRwCy12, clearRE, deviceEnableMode, packetBSEL, testBSEL;
inout dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, idHitB, rfshEqualsZero, rowHitLeftA, rowHitRightA;
input BIMDI, DAmode_b, NSAdr_0_, RASaddrEnable, RAScount_b, RASctCy21, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary01, RfshRwCy01, dataIn0_1_, dataIn1_1_, dataIn2_1_,
dataIn3_1_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, muxBS8, pd0_1_, pd1_1_,
pd2_1_, pd2_2_, pd3_1_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_1_, testBD_2_,
unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
latSRB rowExpRest3(rowExpRest_3_, dataIn3_1_, writeR_6_, reset_b, gnd);
latSRB rowImpRest3(rowImpRest_3_, dataIn2_1_, writeR_6_, vdd, reset);
latSRB rowAcc3(rowAcc_3_, dataIn1_1_, writeR_6_, vdd, reset);
latSRB rowPre3(rowPre_3_, dataIn0_1_, writeR_6_, reset_b, gnd);
ltxBarB Addr1(Addr_b_1_, writeA45, pd3_1_);
latBNcA I569_0_(packetRowAddr_8_, RASaddrEnable, packetRowAddr_b_8_);
latBNcA I569_1_(packetRowAddr_0_, RASaddrEnable, packetRowAddr_b_0_);
mux71x AdrMUX8(ADR_8_, gnd, gnd, packetRowAddr_8_, rfshRowAddr_8_, bank0RowAddr_8_, bank1RowAddr_8_, testADR8, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfAddr, restoreBank0, restoreBank1,
DAmode);
mux71x AdrMUX0(ADR_0_, ColAdr_0_, NSAdr_0_, packetRowAddr_0_, rfshRowAddr_0_, bank0RowAddr_0_, bank1RowAddr_0_, testBD_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfAddr, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg1(NSWE_1_, selectEven_1_, loadNSWE, pd2_1_, pd3_1_, rclk, unloadNSWE);
not #(1) I562(DAmode, DAmode_b);
nor #(1) I558(driveRfAddr, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) I555(testADR8, hnl_399);
not #(1) U554(testBSEL, hnl_576);
invEEbuf U553(packetBSEL, n1_b);
not #(1) U552(Addr_1_, Addr_b_1_);
nand #(1) U547(hnl_577, muxBS8, hnl_75);
mux21 #(1) I544(hnl_576, hnl_79, hnl_85, hnl_577);
mux21 #(1) I537(hnl_399, hnl_85, hnl_79, hnl_577);
DAff I533(hnl_578, hnl_81, hnl_76, testBD_1_, hnl_75);
mux41 #(1) I520(cnt3, rowPre_3_, rowAcc_3_, rowImpRest_3_, rowExpRest_3_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
not #(1) U548(hnl_76, rfshBSEL);
not #(1) U546(hnl_79, testBD_1_);
not #(1) U545(hnl_75, BIMDI);
not #(1) U543(hnl_81, loadDAR);
not #(1) U534(hnl_85, hnl_578);
nandpd2 U508(dataZ0_1_, rowPre_3_, readR_6_);
nandpd2 U519(dataZ3_1_, rowExpRest_3_, readR_6_);
nandpd2 U514(dataZ2_1_, rowImpRest_3_, readR_6_);
nandpd2 U512(dataZ1_1_, rowAcc_3_, readR_6_);
u5DARbit DARbit0(DAR_0_, loadDAR, DAmode, setDAR, testBD_2_);
not #(1) U480(ColAdr_0_, net3986);
countup RASct3(RASctCy10, RAScnt_3_, RAScount_b, RASctCy21, RASldCount, cnt3);
countup Col_0_(CASctCy12, net3986, incColAdr_b, gnd, writeA0123x, pd0_1_);
u5idA Id28(id_28_, dataZ2_1_, idHitB, partialId_b_7_, dataIn2_1_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_8_(bank0RowAddr_8_, bank1RowAddr_8_, dataZ1_1_, dataZ3_1_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_8_, packetRowAddr_b_8_, readR_10_, reset_b, updateRowAddr);
u5Rhit Rhit_0_(bank0RowAddr_0_, bank1RowAddr_0_, dataZ0_1_, dataZ2_1_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_0_, packetRowAddr_b_0_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr8(adrSelReg_8_, partialId_b_7_, packetRowAddr_b_8_, dataZ1_1_, dataIn1_1_, pd2_1_, pd3_1_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RASadr RASadr0(adrSelReg_0_, n1_b, packetRowAddr_b_0_, dataZ0_1_, dataIn0_1_, pd1_1_, pd2_2_, readR_8_, reset_b, writeA0123, writeR_8_);
u5Rfsh0 RefCnt1(RefCount_1_, RefLoad_1_, RfshCntCary12, dataZ0_1_, dataZ2_1_, rfshEqualsZero, RfshCntCary01, incRfshInterval, dataIn0_1_, dataIn2_1_, evalRfshCount, readR_4_, reset_b, writeR_4_);
u5RfshRw RfshRw8(dbIllegal4034_0_, rfshRowAddr_8_, dataZ2_1_, RfshRwCy01, dataIn2_1_, incRfshRow_b, readR_5_, writeR_5_);
u5RfshRw RfshRw0(RfshRwCy12, rfshRowAddr_0_, dataZ0_1_, gnd, dataIn0_1_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR1 MscR1(clearRE, deviceEnableMode, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, dataIn0_1_, dataIn3_1_, readR_9_, readR_3_, readR_2_, reset, reset_b, writeA0123x, writeR_7_, writeR_3_);
not #(1) U470(reset_b, reset);
endmodule

module u5StdCel (ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_, AGEGND, AGEING, BCOeven_b, BCOodd_b, BSEL, CAS, CMPF, CMPV, DAmode_b, DLLByPassMode_b, HVST, MPBT, PDMD, RASB,
REQ, ROLLC, RSTR, SDST, TestSOut, VCMNA, VRST, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, WML, WPBT, WRITE, ackWinOverD, chain_b, clearCount_b, control_5_, control_4_, control_3_,
control_2_, control_1_, control_0_, deviceEnableMode, enableSOut, framePulseX, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, powerOn, pwrdnRcvrs, reset,
resetCap, runtclk, selRegData, standby, stbybWak, sytload_b, testLoad_b, turboDLL_b, writeA45, writeA0123, writeA0123x, writeD0123, writeD4567, writeSenseAmpPipe, RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_,
RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_, RDL3_7_, RDL3_6_,
RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_,
RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_,
RDL8_1_, RDL8_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_,
dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_, dataZ3_0_, BEevenD, BEoddD, BIMDI,
Last_b, OpX_1_, OpX_0_, PON, RCRED, RawLast, Rx_2, SInRaw_b, SuperBE_b, TestCAS, TestRASB, TestRSTR, VREG, Vrefin, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_, WDL1_7_,
WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_,
WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_,
WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_, autoSkip, bcastWriteA,
chainOutEven_8_, chainOutOdd_8_, clockedBE_b, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_,
dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_,
dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, done, frameEnableX, framePulse_b, frameRaw_b, lowVref, mclk, mtclk, opcode_b_2_, opcode_b_1_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_,
pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_,
pd3_3_, pd3_2_, pd3_1_, pd3_0_, rawBE_b, rclk, runclk_b, slow, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_);
output ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_, AGEGND, AGEING, BCOeven_b, BCOodd_b, BSEL, CAS, CMPF, CMPV, DAmode_b, DLLByPassMode_b, HVST, MPBT, PDMD, RASB, REQ,
ROLLC, RSTR, SDST, TestSOut, VCMNA, VRST, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, WML, WPBT, WRITE, ackWinOverD, chain_b, clearCount_b, control_5_, control_4_, control_3_, control_2_,
control_1_, control_0_, deviceEnableMode, enableSOut, framePulseX, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, powerOn, pwrdnRcvrs, reset, resetCap, runtclk,
selRegData, standby, stbybWak, sytload_b, testLoad_b, turboDLL_b, writeA45, writeA0123, writeA0123x, writeD0123, writeD4567, writeSenseAmpPipe;
inout RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_,
RDL2_2_, RDL2_1_, RDL2_0_, RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_,
RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_,
RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_,
dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_,
dataZ3_1_, dataZ3_0_;
input BEevenD, BEoddD, BIMDI, Last_b, OpX_1_, OpX_0_, PON, RCRED, RawLast, Rx_2, SInRaw_b, SuperBE_b, TestCAS, TestRASB, TestRSTR, VREG, Vrefin, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_,
WDL0_1_, WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_,
WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_,
WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_,
autoSkip, bcastWriteA, chainOutEven_8_, chainOutOdd_8_, clockedBE_b, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_,
dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_,
dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, done, frameEnableX, framePulse_b, frameRaw_b, lowVref, mclk, mtclk, opcode_b_2_, opcode_b_1_, pd0_8_, pd0_7_, pd0_6_, pd0_5_,
pd0_4_, pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_,
pd3_6_, pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_, pd3_0_, rawBE_b, rclk, runclk_b, slow, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_;
supply1 vdd;
supply0 gnd;
u5BENSad I978(NSAdr_7_, NSAdr_6_, NSAdr_5_, NSAdr_4_, NSAdr_3_, NSAdr_2_, NSAdr_1_, NSAdr_0_, BEevenD, BEoddD, loadNSAdr, rclk, writeOp_b);
u5CDOpCk CdOpCk(MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, regOp, startCycle_b, writeMaskedNSOp_b, writeOp_b, CASenable, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT,
deviceEnableMode, opcode_3_, opcode_0_, opcode_b_2_, opcode_b_1_, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_);
u5XS XS(rdPipeBusy_b, tclkDisable_b, CASenable, CASstate3_buf, ackWinOver, busyError_b, earlyDone, rclk, reset, writeOp_b);
u5BSNack BSNack(BCOeven_b, BCOodd_b, RASaddrEnable, sytload_b, BusCtrlEn_b, LoadShiftRegister_b, ackLatch, bcastWrite, idHitA, idHitB, latchAbort_b, mtclk, nack, rclk, reset, skip, writeA45);
u5CMPV VREGcmp(CMPF, CMPV, vdd, Vrefin, VREG);
u5RshCtl RshCtl(AUXRASreq, AUXorPDcycle, AUXpending_b, PDreq2, RASrfshRetD, RefreshReturn_b, close0Req_b, close1Req_b, closeCycle, closeCycle_b, doAUXcycle, driveRfshAddr_b, endCycleD_buf,
restoreBank0, restoreBank1, PD64after, PreScx_b, RASAUXRet_b, RASidle_b, clearPDreq2, close0Pending_b, close0Selected, close1Pending_b, close1Selected, decXferCnt_b, enableRefreshMode, evalRfshCount,
explicitRestore, idle, incRfshRow_b, packetBSELx, powerDownReq_b, rclk, reFetchCycle, reset, rfshEqualsZero, setRR_b, writeA45, writeA0123x);
u5Rasb Rasb(RASB, RASpending, RASpending_b, clearPDreq2, drivePacketRASaddr, incRfshRow_b, powerDownMode, reFetchCycle, reFetchCycle_b, updateRowAddr, AUXRASreq, BIMDI, DAmode_b, PDreq2, RASkill,
RASprecharge, RASrfshRetD, RASstate4, RS_0_, SInRaw_b, TestRASB, clearRASpending_b, doAUXcycle, endPowerDown_b, explicitRestore, idHitRowMiss, latchAbort, rclk, reset, rfshCout_1_, setPD, standby,
writeA0123x);
u5AkWDly AkWDly(BusCtrlEn_b, ackClear, ackLatch, ackWinOver, ackWinOverD, inhLoadLast_b, ackDelay_1_, ackDelay_0_, ackWinDelay_2_, ackWinDelay_1_, ackWinDelay_0_, evalR, framePulseX, rclk, reset);
u5bit4 bit4(ADR_3_, CASctCy45, Count_2_, DAR_3_, NSWE_4_, RAScountLSB_b, RfshCntCary45, RfshRwCy45, XfrCntBorw45, ackDelay_1_, ackWinDelay_1_, partialId_b_2_, pd2_4_, readDelay_1_, skip,
writeDelay_1_, xcnt_b_0_, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, idHitB, rfshEqualsZero, row0hitA, row1hitA, CASctCy34, DAmode_b, DLLByPassMode_b, NSAdr_3_, RASaddrEnable, RASldCount, RASsel_3_,
RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary34, RfshRwCy34, autoSkip, autoSkipEn, dataIn0_4_, dataIn1_4_, dataIn2_4_, dataIn3_4_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr,
driveRfshAddr_b, evalR, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_1_, pd0_4_, pd1_4_, pd2_5_, pd3_4_, rclk, readR_10_, readR_9_, readR_8_,
readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, skipBit, testBD_5_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x,
writeR_8_, writeR_6_, writeR_5_, writeR_4_, writeR_2_, writeR_1_);
u5CAScyc CAScyc(CAS, CASstate1_b, CASstate3_buf, CASwrite, LoadShiftRegister_b, WML, WRITE, decXferCnt_b, earlyREQinhibit, firstCycWE_b, incColAdr_b, loadLast, loadNSAdr, preloadNSWE, selRegData,
startNSAdr_b, trueCASstate1_b, unloadNSWE, writeD0123, writeD4567, writeSenseAmpPipe, CASenable, DAWD0123, DAWD4567, DAmode_b, NSOp, REQinhibiten, TestCAS, TestRASB, TestWML, TestWRITE, WPBNP,
abortOperation_b, earlyDone, inhLoadLast_b, localREQ, rclk, regOp, reset, standby, startCycle_b, virtuallyDone, writeA45, writeMaskedNSOp_b, writeOp_b);
u5RegDec RegDec(framePulseX, readR_10_, readR_9_, readR_8_, readR_7_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_,
writeR_3_, writeR_2_, writeR_1_, ADRx_6_, ADR_2_, ADR_1_, ADR_0_, Addr_2_, PDMD, framePulse_b, reset, selRegData, writeD4567);
u5PreHit PreHit(CASenable, RASkill, RASstate4, REQ, bcastWrite, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idHitRowMiss, idle, latchAbort, latchAbort_b, localREQ, nack, runtclk,
virtuallyDone, writeA45, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b, DLLByPassMode_b, NSOp, PDMD, RASidle_b, RASreturn_b, RefreshReturn_b, TestRASB, abortOperation_b, ackClear,
bcastWriteA, bcastWriteB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB,
startNSAdr_b, tclkDisable_b, updateRowAddr, writeOp_b);
u5RAScyc RAScyc(DeviceBusy, RASAUXRet_b, RAScount_b, RASidle_b, RASldCount, RASprecharge, RASreturn_b, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RS_0_, RSTR, clearRASpending_b, close0Pending_b,
close0Selected, close1Pending_b, close1Selected, explicitRestore, localRSTR_b, setPD, DAmode_b, PD64after, PDreq2, RAScountLSB_b, RASoverflow_b, RASpending, RASpending_b, TestRSTR, busy_b,
close0Req_b, close1Req_b, closeCycle, closeCycle_b, doAUXcycle, endCycleD_buf, needRestore, powerDownReq_b, rclk, reFetchCycle_b, reset, turboDLL_b);
u5bit78 bit78(ADR_6_, CASctCy70, NSWE_7_, RfshRwCy70, bcastWriteB, chainOut_8_, control_7_, control_5_, control_4_, control_3_, opcode_3_, opcode_0_, pd2_7_, dataZ0_7_, dataZ1_7_, dataZ2_7_,
dataZ3_7_, idHitA, rfshEqualsZero, row0hitB, row1hitB, CASctCy67, DAmode_b, NSAdr_6_, RASaddrEnable, RfshCntCary67, RfshRwCy67, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn1_7_, dataIn2_7_,
dataIn3_7_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalL, evalRfshCount, ictrl_5_, ictrl_4_, ictrl_3_, incColAdr_b, incRfshInterval, incRfshRow_b, loadNSWE, localBSEL,
partialId_b_4_, pd0_7_, pd0_8_, pd1_7_, pd1_8_, pd2_8_, pd3_7_, pd3_8_, rclk, readR_5_, readR_4_, readR_3_, readR_1_, readR_0_, readR_10_, readR_9_, readR_8_, readR_7_, reset, restoreBank0,
restoreBank1, testBD_8_, unloadNSWE, updateRowAddr, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
u5CCctl CCctl(ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, powerOn, resetCap, control_7_, control_6_, control_5_, control_4_, control_3_, control_2_, control_1_, control_0_, done,
evalRfshCount, mclk, reset, writeA0123);
u5bit3 bit3(ADR_2_, CASctCy34, Count_1_, DAR_2_, NSWE_3_, RASctCy32, RfshCntCary34, RfshRwCy34, ackDelay_0_, ackWinDelay_0_, partialId_b_1_, pd2_3_, readDelay_0_, rfshBSEL, setRE, skipBit,
writeDelay_0_, dataZ0_3_, dataZ1_3_, dataZ2_3_, dataZ3_3_, idHitB, rfshEqualsZero, row0hitA, row1hitA, CASctCy23, DAmode_b, NSAdr_2_, RASaddrEnable, RAScount_b, RASldCount, RASsel_3_, RASsel_2_,
RASsel_1_, RASsel_0_, RfshCntCary23, RfshRwCy23, dataIn0_3_, dataIn1_3_, dataIn2_3_, dataIn3_3_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalR, evalRfshCount, incColAdr_b,
incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_0_, pd0_3_, pd1_3_, pd2_4_, pd3_3_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_,
readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, testBD_4_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_,
writeR_3_, writeR_2_, writeR_1_);
u5TstCtl TstCtl(AGEGND, AGEING, CMPV, DAWD0123, DAWD4567, DAmode_b, DLLByPassMode_b, HVST, PDMD, ROLLC, SDST, TestMPBT, TestSOut, TestWE, TestWML, TestWPBT, TestWRITE, VCMNA, VRST, chain_b,
enableSOut, loadDAR, needRestore, pwrdnRcvrs, testLoad_b, BIMDI, CASwrite, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, RCRED, SInRaw_b, SuperBE_b, TestCAS, TestRASB, TestRSTR, chainOut_8_, localBSEL,
localRSTR_b, lowVref, powerDownMode, rclk, reset, resetDAmode_b, runclk_b, slow, testBD_b_0_);
RWDfthru I652_8_(RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_);
RWDfthru I652_7_(RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_);
RWDfthru I652_6_(RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_);
RWDfthru I652_5_(RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_);
RWDfthru I652_4_(RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_);
RWDfthru I652_3_(RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_);
RWDfthru I652_2_(RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_);
RWDfthru I652_1_(RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_);
RWDfthru I652_0_(RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_);
u5bit0 bit0(ADR_7_, Addr_0_, Addr_2_, NSWE_0_, RASoverflow_b, RfshCntCary01, RfshRwCy01, enableRefreshMode, muxBS8, setRR_b, testBD_b_0_, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, idHitB,
rfshEqualsZero, row0hitA, row1hitA, CASctCy70, DAmode_b, NSAdr_7_, RASaddrEnable, RAScount_b, RASctCy10, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy70, clearRE, dataIn0_0_,
dataIn1_0_, dataIn2_0_, dataIn3_0_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalR, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL,
pd0_0_, pd1_0_, pd2_0_, pd3_0_, powerDownReq_b, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setRE,
testBD_0_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
u5bit5 bit5(ADR_4_, CASctCy56, DAR_4_, NSWE_5_, PDslow, RfshCntCary56, RfshRwCy56, XfrCntBorw56, ackWinDelay_2_, partialId_b_3_, pd2_5_, readDelay_2_, setDAR, writeDelay_2_, xcnt4321, dataZ0_5_,
dataZ1_5_, dataZ2_5_, dataZ3_5_, idHitA, rfshEqualsZero, row0hitB, row1hitB, CASctCy45, DAmode_b, NSAdr_4_, RASaddrEnable, RfshCntCary45, RfshRwCy45, XfrCntBorw45, dataIn0_5_, dataIn1_5_, dataIn2_5_,
dataIn3_5_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalL, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_2_,
pd0_5_, pd1_5_, pd2_6_, pd3_5_, rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_6_, testBD_7_,
unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_2_, writeR_1_, xcnt_b_4_, xcnt_b_3_);
u5BElog BElog(PD64after, PreScx_b, clearCount_b, endPowerDown_b, evalRfshCount, incRfshInterval, reset, resetDAmode_b, standby, stbybWak, turboDLL_b, DAmode_b, DLLByPassMode_b, DeviceBusy, PDreq2,
PDslow, PON, Rx_2, clockedBE_b, decXferCnt_b, enableRefreshMode, mclk, powerDownMode, rawBE_b, rclk, rdPipeBusy_b);
u5WEgen WEgen(ADRx_6_, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, earlyDone, loadNSWE, ADR_6_, Addr_2_, Addr_1_, Addr_0_, CASstate1_b, Count_2_, Count_1_, Count_0_, DAmode_b, Last_b,
NSOp, NSWE_7_, NSWE_6_, NSWE_5_, NSWE_4_, NSWE_3_, NSWE_2_, NSWE_1_, NSWE_0_, RASB, RawLast, TestWE, firstCycWE_b, loadLast, preloadNSWE, rclk, regOp, reset, trueCASstate1_b, writeA0123x,
writeMaskedNSOp_b, writeOp_b, xcnt4321, xcnt_b_0_);
u5bit2 bit2(ADR_1_, BSEL, CASctCy23, Count_0_, DAR_1_, NSWE_2_, RASctCy21, RfshCntCary23, RfshRwCy23, autoSkipEn, localBSEL, packetBSELx, partialId_b_0_, pd2_2_, powerDownReq_b, rfshCout_1_,
dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, idHitB, rfshEqualsZero, row0hitA, row1hitA, CASctCy12, DAmode_b, NSAdr_1_, RASaddrEnable, RAScount_b, RASctCy32, RASldCount, RASsel_3_, RASsel_2_,
RASsel_1_, RASsel_0_, RfshCntCary12, RfshRwCy12, dataIn0_2_, dataIn1_2_, dataIn2_2_, dataIn3_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, endPowerDown_b, evalR, evalRfshCount,
incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE, packetBSEL, pd0_2_, pd1_2_, pd2_3_, pd3_2_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_,
readR_1_, readR_0_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_3_, testBSEL, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_,
writeR_4_, writeR_3_, writeR_1_);
u5bit6 bit6(ADR_5_, CASctCy67, NSWE_6_, RfshCntCary67, RfshRwCy67, control_6_, control_2_, control_1_, control_0_, partialId_b_4_, pd2_6_, xcnt_b_4_, xcnt_b_3_, dataZ0_6_, dataZ1_6_, dataZ2_6_,
dataZ3_6_, idHitA, rfshEqualsZero, row0hitB, row1hitB, CASctCy56, DAmode_b, NSAdr_5_, RASaddrEnable, RfshCntCary56, RfshRwCy56, XfrCntBorw56, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_,
decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalL, evalRfshCount, ictrl_2_, ictrl_1_, ictrl_0_, incColAdr_b, incRfshInterval, incRfshRow_b, loadNSWE, localBSEL,
partialId_b_3_, pd0_6_, pd1_6_, pd2_7_, pd3_6_, rclk, readR_5_, readR_4_, readR_3_, readR_1_, readR_0_, readR_10_, readR_9_, readR_8_, readR_7_, reset, restoreBank0, restoreBank1, testBD_7_,
unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
u5bit1 bit1(ADR_8_, ADR_0_, Addr_1_, CASctCy12, DAR_0_, NSWE_1_, RASctCy10, RfshCntCary12, RfshRwCy12, clearRE, deviceEnableMode, packetBSEL, testBSEL, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_,
idHitB, rfshEqualsZero, row0hitA, row1hitA, BIMDI, DAmode_b, NSAdr_0_, RASaddrEnable, RAScount_b, RASctCy21, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshCntCary01, RfshRwCy01,
dataIn0_1_, dataIn1_1_, dataIn2_1_, dataIn3_1_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalR, evalRfshCount, incColAdr_b, incRfshInterval, incRfshRow_b, loadDAR, loadNSWE,
localBSEL, muxBS8, pd0_1_, pd1_1_, pd2_1_, pd2_2_, pd3_1_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_4_, readR_3_, readR_2_, readR_1_, reset, restoreBank0, restoreBank1,
rfshBSEL, setDAR, testBD_1_, testBD_2_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_4_, writeR_3_, writeR_1_);
endmodule

module probe (probe);
inout probe;
supply1 vdd;
supply0 gnd;
endmodule

// verilog header
module u5TstStr ();
supply1 vdd;
supply0 gnd;
endmodule

module u5IOgnd (gnd, vdd);
input gnd, vdd;
supply1 vdd;
supply0 gnd;
endmodule

module u5InProt (padin, pad);
output padin;
inout pad;
supply1 vdd;
supply0 gnd;
P4res Rin(pad, padin);
tranif1 N18(gnd, pad, gnd);
tranif1 N15(gnd, pad, gnd);
tranif1 N11(gnd, pad, gnd);
tranif1 N6(gnd, pad, gnd);
tranif1 N5(gnd, pad, gnd);
tranif1 N2(gnd, pad, gnd);
endmodule

module u5DABuf (Out, En_b, In);
output Out;
input En_b, In;
supply1 vdd;
supply0 gnd;
not (weak0,weak1) #(1) U33(out0B, out1);
nand #(1) U37(hnl_580, out1, En);
not #(1) I32(out1, out0B);
not #(1) I31(En, En_b);
not #(1) I36(Out, hnl_580);
tranif1 N29(hnl_581, gnd, In);
tranif1 N27(out0B, hnl_581, En);
tranif0 P25(out0B, hnl_582, En_b);
tranif0 P28(hnl_582, vdd, In);
endmodule

module cxfr (D, GN, GP, S);
output D;
input GN, GP, S;
supply1 vdd;
supply0 gnd;
tranif0 P8(S, D, GP);
tranif1 N9(S, D, GN);
endmodule

module u5DfLatB (Q, D, DB, enb, pdb);
output Q;
input D, DB, enb, pdb;
supply1 vdd;
supply0 gnd;
nand #(1) nandd(outd, outc, pdb);
nand #(1) nandb(lclkb, outa, pdb);
rtranif1 N100(ds, gnd, dsb);
rtranif0 P99(ds, vdd, dsb);
not (weak0,weak1) #(1) U94(dsb, ds);
not #(1) ine(lclk, outd);
not #(1) inc(outc, enb);
not #(1) ina(outa, enb);
cxfr U85(dsb, lclk, lclkb, D);
cxfr U64(ds, lclk, lclkb, DB);
not #(1) U65(Q, ds);
endmodule

module u5DfLat (Q, D, DB, en, pdb);
output Q;
input D, DB, en, pdb;
supply1 vdd;
supply0 gnd;
nand #(1) nandc(outc, en, pdb);
nand #(1) nanda(outa, en, pdb);
rtranif0 P101(ds, vdd, dsb);
rtranif1 N100(ds, gnd, dsb);
not (weak0,weak1) #(1) U94(dsb, ds);
not #(1) ind(outd, outc);
not #(1) inb(lclk, outa);
cxfr U85(dsb, lclk, lclkb, D);
cxfr U64(ds, lclk, lclkb, DB);
not #(1) ine(lclkb, outd);
not #(1) U65(Q, ds);
endmodule

module u5BEInpt (BEevenD, BEoddD, SuperBE_b, TestRSTR, clockedBE_b, rawBE_b, runclk_b, BusEnable, DAmode_b, VRefin, mclk, powerDownMode, rclk, stbybWak);
output BEevenD, BEoddD, SuperBE_b, TestRSTR, clockedBE_b, rawBE_b, runclk_b;
input BusEnable, DAmode_b, VRefin, mclk, powerDownMode, rclk, stbybWak;
supply1 vdd;
supply0 gnd;
nand #(1) U439(clockedBE_b, pwrdnB, BEeven);
lvtncap C462(gnd, gnd);
ffB #(1) I460(hnl_583, rclk, BEodd);
ffB #(1) I459(BEevenD, rclk, hnl_438);
not #(1) U458(BEoddD, hnl_583);
u5InProt BEinProt(BusEnableIn, BusEnable);
u5DABuf RSTRDAbuf(TestRSTR, DAmode_b, BusEnableIn);
u5TstIn TstIn(SuperBE_b, BusEnableIn, powerDownMode);
u5BEsnif BEsnif(rawBE_b, VRefin, BusEnableIn);
u5DfLatB I436(BEeven, eq, eqb, mclk, pwrdnB);
u5DfLat I435(BEodd, oq, oqb, mclk, pwrdnB);
u5EIRcvr Reven(eq, eqb, powerDownMode, VRefin, BusEnableIn, mclk);
u5OIRcvr ROdd(oqb, oq, powerDownMode, BusEnableIn, mclk, VRefin);
not #(1) U411(hnl_438, BEeven);
nand #(1) U313(hnl_56, hnl_584, clockedBE_b);
not #(1) U461(pwrdnB, powerDownMode);
not #(1) U308(runclk_b, hnl_56);
not #(1) U302(hnl_584, stbybWak);
endmodule

module u5VrfLow (lowVref, VRefin);
output lowVref;
input VRefin;
supply1 vdd;
supply0 gnd;
not #(1) U5(hnl_585, o1);
not #(1) U3(o1, VRefin);
not #(1) I6(lowVref, hnl_585);
endmodule

module u5SIO (SInRaw_b, SOut, VRefin, lowVref, CMPF, CMPV, DAmode_b, SIn, TestSOut, VRef, deviceEnableMode, enableSOut, tclk);
output SInRaw_b, SOut, VRefin, lowVref;
input CMPF, CMPV, DAmode_b, SIn, TestSOut, VRef, deviceEnableMode, enableSOut, tclk;
supply1 vdd;
supply0 gnd;
u5VrfLow I167(lowVref, VRefin);
u5InProt Sininprot(hnl_586, SIn);
u5InProt Vrefinprot(VRefin, VRef);
u5OscMJ OscMJ(osc, oscen);
u5SoDrv SoDrv(oscen, SOut, hnl_587, osc, hnl_17);
nor #(1) U143(hnl_588, CMPV, DAmode_b);
probe I159(osc);
u5SioMux I150(hnl_589, hnl_590, hnl_591, CMPF, DAmode_b, CMPV, hnl_588);
not #(1) U77(hnl_283, hnl_592);
not #(1) I153(hnl_593, SInRaw_b);
not #(1) I152(hnl_17, hnl_428);
not #(1) I149(hnl_594, hnl_595);
nand #(1) U154(hnl_590, hnl_593, deviceEnableMode);
nand #(1) U148(hnl_595, hnl_589, hnl_17);
not #(1) LowB(hnl_596, hnl_586);
not #(1) HighB(hnl_597, hnl_586);
not #(1) U76(hnl_592, hnl_586);
not #(1) U142(hnl_591, TestSOut);
not #(1) U151(hnl_428, enableSOut);
not #(1) U146(hnl_587, hnl_594);
not #(1) U75(SInRaw_b, hnl_283);
endmodule

module latW (Y, A);
output Y;
inout A;
supply1 vdd;
supply0 gnd;
rtranif1 N22(A, gnd, Y);
tranif1 N27(Y, gnd, A);
rtranif0 P21(A, vdd, Y);
tranif0 P28(Y, vdd, A);
endmodule

module u5OutDrv (pad, q0, q1, q2, q3, q4, q5);
inout pad;
input q0, q1, q2, q3, q4, q5;
supply1 vdd;
supply0 gnd;
tranif1 N4(gnd, pad, q0);
tranif1 N1(gnd, pad, q4);
tranif1 N33(gnd, pad, q3);
tranif1 N43(gnd, pad, q2);
tranif1 N44(gnd, pad, q1);
tranif1 N42(gnd, pad, q5);
endmodule

module u5OutMux (q0, q1, q2, q3, q4, q5, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b);
output q0, q1, q2, q3, q4, q5;
input evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b;
supply1 vdd;
supply0 gnd;
not #(1) U90(q3, d3);
not #(1) U82(q0, d0);
not #(1) U74(q1, d1);
not #(1) U88(q2, d2);
not #(1) U69(q4, d4);
not #(1) U91(q5, d5);
nand #(1) U61(o3, oddData, ictrl_3_);
nand #(1) U126(e3, evenData, ictrl_3_);
nand #(1) U134(e4, evenData, ictrl_4_);
nand #(1) U51(o4, oddData, ictrl_4_);
nand #(1) U77(o5, oddData, ictrl_5_);
nand #(1) U133(e5, evenData, ictrl_5_);
nand #(1) U132(e0, evenData, ictrl_0_);
nand #(1) U131(o0, oddData, ictrl_0_);
nand #(1) U130(e1, evenData, ictrl_1_);
nand #(1) U129(o1, oddData, ictrl_1_);
nand #(1) U128(e2, evenData, ictrl_2_);
nand #(1) U127(o2, oddData, ictrl_2_);
cxfr U56(d3, tclkL, tclkL_b, o3);
cxfr U119(d3, tclkL_b, tclkL, e3);
cxfr U140(d0, tclkL_b, tclkL, e0);
cxfr U139(d0, tclkL, tclkL_b, o0);
cxfr U138(d1, tclkL_b, tclkL, e1);
cxfr U137(d1, tclkL, tclkL_b, o1);
cxfr U136(d2, tclkL_b, tclkL, e2);
cxfr U135(d2, tclkL, tclkL_b, o2);
cxfr U99(d4, tclkL_b, tclkL, e4);
cxfr U52(d4, tclkL, tclkL_b, o4);
cxfr U76(d5, tclkL, tclkL_b, o5);
cxfr U118(d5, tclkL_b, tclkL, e5);
endmodule

module u5OutLat3 (out, load, loadB, pipeB, rdl, wrtPipe, wrtPipeB);
output out;
input load, loadB, pipeB, rdl, wrtPipe, wrtPipeB;
supply1 vdd;
supply0 gnd;
latW U35(lat1, hnl_598);
not #(1) U67(rdlB, rdl);
cxfr U34(hnl_598, wrtPipe, wrtPipeB, rdlB);
tranif1 N59(hnl_599, gnd, pipeB);
tranif1 N56(out, hnl_599, loadB);
tranif1 N53(out, hnl_600, load);
tranif1 N51(hnl_600, gnd, lat1);
tranif0 P57(out, hnl_601, load);
tranif0 P55(hnl_601, vdd, pipeB);
tranif0 P54(hnl_602, vdd, lat1);
tranif0 P52(out, hnl_602, loadB);
endmodule

module u5OutLat2 (out, load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB);
output out;
input load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB;
supply1 vdd;
supply0 gnd;
not #(1) U32(hnl_603, regin);
latW U35(lat1, hnl_598);
cxfr U34(hnl_598, wrtPipe, wrtPipeB, mux1);
tranif1 N64(hnl_604, gnd, srdB);
tranif1 N59(hnl_599, hnl_604, pipeB);
tranif1 N56(out, hnl_599, loadB);
tranif1 N53(out, hnl_600, load);
tranif1 N51(hnl_600, gnd, lat1);
tranif1 N50(hnl_605, gnd, hnl_603);
tranif1 N49(mux1, hnl_605, srd);
tranif1 N14(hnl_606, gnd, rdl);
tranif1 N13(mux1, hnl_606, srdB);
rtranif0 P33(regin, vdd, gnd);
tranif0 P62(hnl_601, vdd, srdB);
tranif0 P57(out, hnl_601, load);
tranif0 P55(hnl_601, vdd, pipeB);
tranif0 P54(hnl_602, vdd, lat1);
tranif0 P52(out, hnl_602, loadB);
tranif0 P48(hnl_607, vdd, hnl_603);
tranif0 P47(mux1, hnl_607, srdB);
tranif0 P10(mux1, hnl_608, srd);
tranif0 P11(hnl_608, vdd, rdl);
endmodule

module u5OutLat1 (out, load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB);
output out;
input load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB;
supply1 vdd;
supply0 gnd;
not #(1) U32(hnl_603, regin);
latW U35(lat1, hnl_598);
cxfr U34(hnl_598, wrtPipe, wrtPipeB, mux1);
tranif1 N59(hnl_599, gnd, pipeB);
tranif1 N56(out, hnl_599, loadB);
tranif1 N53(out, hnl_600, load);
tranif1 N51(hnl_600, gnd, lat1);
tranif1 N50(hnl_605, gnd, hnl_603);
tranif1 N49(mux1, hnl_605, srd);
tranif1 N14(hnl_606, gnd, rdl);
tranif1 N13(mux1, hnl_606, srdB);
rtranif0 P33(regin, vdd, gnd);
tranif0 P57(out, hnl_601, load);
tranif0 P55(hnl_601, vdd, pipeB);
tranif0 P54(hnl_602, vdd, lat1);
tranif0 P52(out, hnl_602, loadB);
tranif0 P48(hnl_607, vdd, hnl_603);
tranif0 P47(mux1, hnl_607, srdB);
tranif0 P10(mux1, hnl_608, srd);
tranif0 P11(hnl_608, vdd, rdl);
endmodule

module u5Output (chainOutEven, chainOutOdd, padin1, padin2, pad, RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, chainInEven, chainInOdd, chain_b, ictrl_5_, ictrl_4_, ictrl_3_,
ictrl_2_, ictrl_1_, ictrl_0_, regin0, regin1, regin2, regin3, srd, sytload_b, tclkL, tclkL_b, testLoad_b, writeSenseAmpPipe);
output chainOutEven, chainOutOdd, padin1, padin2;
inout pad;
input RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, chainInEven, chainInOdd, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, regin0, regin1, regin2, regin3,
srd, sytload_b, tclkL, tclkL_b, testLoad_b, writeSenseAmpPipe;
supply1 vdd;
supply0 gnd;
latW U656(hnl_609, hnl_610);
latW U539(hnl_69, hnl_611);
nand #(1) I609(hnl_612, hnl_613, chain_b);
nand #(1) U606(hnl_614, hnl_69, chain_b);
u5OutDrv OutDrv(pad, q0, q1, q2, q3, q4, q5);
P4res Rin3(pad, padin2);
P4res Rin2(hnl_615, padin1);
P4res Rin1(pad, hnl_615);
u5OutMux OutMux(q0, q1, q2, q3, q4, q5, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b);
u5OutLat3 I630(in6, load, load_b, hnl_616, RDL_4_, wrtPipe, wrtPipe_b);
u5OutLat3 I645(in7, load, load_b, hnl_617, RDL_6_, wrtPipe, wrtPipe_b);
u5OutLat3 I647(in3, load, load_b, hnl_618, RDL_7_, wrtPipe, wrtPipe_b);
u5OutLat3 I631(in2, load, load_b, hnl_619, RDL_5_, wrtPipe, wrtPipe_b);
u5OutLat2 I625(in5, load, load_b, hnl_620, RDL_2_, regin2, srd, srd_b, wrtPipe, wrtPipe_b);
u5OutLat2 I627(in1, load, load_b, hnl_621, RDL_3_, regin3, srd, srd_b, wrtPipe, wrtPipe_b);
latW U657(hnl_622, hnl_613);
latW U629(hnl_623, hnl_624);
latW U635(hnl_625, hnl_626);
latW U655(hnl_627, hnl_628);
latW U654(hnl_629, hnl_630);
latW U653(hnl_631, hnl_632);
latW U638(hnl_328, hnl_633);
latW U639(hnl_634, hnl_635);
latW U634(hnl_636, hnl_637);
latW U637(load_b, w2);
latW U636(load, w1);
latW U633(hnl_175, hnl_619);
latW U632(hnl_315, hnl_616);
latW U628(hnl_176, hnl_621);
latW U626(hnl_638, hnl_620);
latW U624(hnl_101, hnl_639);
u5OutLat1 lat1b0(in4, load, load_b, hnl_639, RDL_0_, regin0, srd, srd_b, wrtPipe, wrtPipe_b);
u5OutLat1 I623(in0, load, load_b, hnl_624, RDL_1_, regin1, srd, srd_b, wrtPipe, wrtPipe_b);
nor #(1) U613(chainOutOdd, hnl_640, chain_b);
nor #(1) U611(chainOutEven, hnl_641, chain_b);
nand #(1) U648(hnl_642, chain, chainInOdd);
nand #(1) U579(hnl_643, chain, chainInEven);
nand #(1) U595(hnl_644, sytload_b, testLoad_b);
not #(1) U610(oddData, hnl_612);
not #(1) I607(evenData, hnl_614);
not #(1) I614(wrtPipe, wrtPipe_b);
not #(1) I649(hnl_618, hnl_642);
not #(1) U578(chain, chain_b);
not #(1) I646(hnl_617, hnl_643);
not #(1) U673(hnl_640, hnl_613);
not #(1) U672(hnl_641, hnl_69);
not #(1) U398(wrtPipe_b, writeSenseAmpPipe);
not #(1) U593(hnl_645, hnl_625);
not #(1) U391(srd_b, srd);
cxfr U372(hnl_613, tclkL_b, tclkL, hnl_609);
cxfr U663(hnl_610, tclkL, tclkL_b, in0);
cxfr U667(hnl_624, tclkL_b, tclkL, hnl_627);
cxfr U660(hnl_628, tclkL, tclkL_b, in1);
cxfr U666(hnl_621, tclkL_b, tclkL, hnl_629);
cxfr U659(hnl_630, tclkL, tclkL_b, in2);
cxfr U665(hnl_619, tclkL_b, tclkL, hnl_631);
cxfr U658(hnl_632, tclkL, tclkL_b, in3);
cxfr U596(w2, tclkL_b, tclkL, hnl_645);
cxfr U599(w1, tclkL_b, tclkL, hnl_625);
cxfr U602(hnl_626, tclkL, tclkL_b, hnl_644);
cxfr U303(hnl_611, tclkL, tclkL_b, in4);
cxfr U320(hnl_639, tclkL_b, tclkL, hnl_636);
cxfr U661(hnl_637, tclkL, tclkL_b, in5);
cxfr U664(hnl_620, tclkL_b, tclkL, hnl_634);
cxfr U662(hnl_635, tclkL, tclkL_b, in6);
cxfr U310(hnl_616, tclkL_b, tclkL, hnl_328);
cxfr U311(hnl_633, tclkL, tclkL_b, in7);
endmodule

module u5LtMxDf (pd, D, DB, en, s_b, serialData);
output pd;
input D, DB, en, s_b, serialData;
supply1 vdd;
supply0 gnd;
nand #(1) U108(hnl_646, en, hnl_208);
rtranif0 P111(ds, vdd, dsb);
tranif0 P103(hnl_647, vdd, serialData);
tranif0 P102(dsb, hnl_647, hnl_646);
rtranif1 N110(ds, gnd, dsb);
tranif1 N106(hnl_648, gnd, serialData);
tranif1 N100(dsb, hnl_648, hnl_421);
not (weak0,weak1) #(1) U94(dsb, ds);
nand #(1) nandc(hnl_649, en, s_b);
nand #(1) nanda(hnl_650, en, s_b);
not #(1) ind(hnl_651, hnl_649);
not #(1) inb(lclk, hnl_650);
not #(1) U107(hnl_208, s_b);
not #(1) U104(hnl_421, hnl_646);
not #(1) I79(pd, d_bs1);
cxfr U85(dsb, lclk, lclkb, DB);
cxfr U64(ds, lclk, lclkb, D);
not #(1) ine(lclkb, hnl_651);
not #(1) U65(d_bs1, ds);
endmodule

module u5BLtMxD (pdb, D, DB, enb, s_b, serialDataB);
output pdb;
input D, DB, enb, s_b, serialDataB;
supply1 vdd;
supply0 gnd;
nor #(1) U111(hnl_652, enb, s_b);
rtranif0 P115(dsb, vdd, ds);
tranif0 P108(ds, hnl_653, hnl_654);
tranif0 P109(hnl_653, vdd, serialDataB);
rtranif1 N114(dsb, gnd, ds);
tranif1 N106(hnl_655, gnd, serialDataB);
tranif1 N105(ds, hnl_655, hnl_652);
nand #(1) nandd(outd, outc, s_b);
nand #(1) nandb(lclkb, outa, s_b);
not (weak0,weak1) #(1) U100(ds, dsb);
not #(1) inc(outc, enb);
not #(1) ina(outa, enb);
not #(1) ine(lclk, outd);
not #(1) U65(d_bs1, dsb);
cxfr U85(ds, lclk, lclkb, D);
cxfr U64(dsb, lclk, lclkb, DB);
not #(1) U112(hnl_654, hnl_652);
not #(1) I79(pdb, d_bs1);
endmodule

module u5Input (WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, sampledInEven, sampledInOdd, InClk, InClkB, VRefin, chain_b,
padin, pwrdnRcvrs, rclk, serialInEven, serialInOdd, writeD0123, writeD4567);
output WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, sampledInEven, sampledInOdd;
input InClk, InClkB, VRefin, chain_b, padin, pwrdnRcvrs, rclk, serialInEven, serialInOdd, writeD0123, writeD4567;
supply1 vdd;
supply0 gnd;
u5LtMxDf I311(pd3, DataOdd, DataOddB, rclk, chain_b, serialInOdd);
nand #(1) U315(hnl_656, hnl_657, writeD4567);
nand #(1) U314(hnl_658, rclk, writeD0123);
u5BLtMxD I312(EvenLat, DataEven, DataEvenB, rclk, chain_b, hnl_659);
u5pd2Lat I301(pd2, InClk, EvenLat, InClkB);
u5OIRcvr Odd(DataOddB, DataOdd, pwrdnRcvrs, padin, rclk, VRefin);
u5EIRcvr Even(DataEven, DataEvenB, pwrdnRcvrs, VRefin, padin, rclk);
not #(1) U320(hnl_552, hnl_660);
not #(1) U319(hnl_54, hnl_661);
not #(1) I318(writeD4L, hnl_656);
not #(1) I316(writeD0L, hnl_658);
not #(1) I309(sampledInOdd, hnl_462);
not #(1) I307(sampledInEven, EvenLat);
u5InLat4 I263(WDL_1_, hnl_662, writeD4L, writeD4_B);
u5InLat4 I265(WDL_3_, hnl_663, writeD4L, writeD4_B);
u5InLat4 I264(WDL_5_, hnl_664, writeD4L, writeD4_B);
u5InLat4 I259(WDL_0_, hnl_665, writeD4L, writeD4_B);
u5InLat4 I260(WDL_4_, hnl_666, writeD4L, writeD4_B);
u5InLat4 I266(WDL_7_, hnl_552, writeD4L, writeD4_B);
u5InLat4 I262(WDL_6_, hnl_54, writeD4L, writeD4_B);
u5InLat4 I261(WDL_2_, hnl_667, writeD4L, writeD4_B);
not #(1) U321(hnl_657, rclk);
not #(1) U306(writeD4_B, writeD4L);
not #(1) U308(hnl_462, pd3);
not #(1) U305(writeD0_B, writeD0L);
not #(1) U300(hnl_659, serialInEven);
u5InLat3 I258(dataIn3, hnl_663, writeD0L, pd3, writeD0_B);
u5InLat3 I257(dataIn1, hnl_662, writeD0L, pd1, writeD0_B);
u5InLat3 I256(dataIn2, hnl_667, writeD0L, pd2, writeD0_B);
u5InLat3 I255(dataIn0, hnl_665, writeD0L, pd0, writeD0_B);
u5InLat2 I252(hnl_664, pd1, InClk, hnl_660, InClkB);
u5InLat2 I251(hnl_666, pd0, InClk, hnl_661, InClkB);
u5InLat1 I250(hnl_660, InClkB, pd3, InClk);
u5InLat1 I249(hnl_661, InClkB, pd2, InClk);
endmodule

module u5IOpad (WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, chainOutEven, chainOutOdd, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, testBD, pad, DAmode_b, RDL_7_,
RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, VRefin, chainIn_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, regin0, regin1, regin2, regin3,
serialInEven, serialInOdd, srd, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
output WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, chainOutEven, chainOutOdd, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, testBD;
inout pad;
input DAmode_b, RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, VRefin, chainIn_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, regin0,
regin1, regin2, regin3, serialInEven, serialInOdd, srd, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe;
supply1 vdd;
supply0 gnd;
tranif1 N126(hnl_668, gnd, padin1);
probe I128(hnl_668);
u5OutClk Outclk(tclkl, tclklB, tclk);
u5InClk Inclk(InClk, InClkB, rclk);
u5DABuf DABuf(testBD, DAmode_b, padin2);
u5Output Output(chainOutEven, chainOutOdd, padin1, padin2, pad, RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, inputDataEven, inputDataOdd, chain_b, ictrl_5_, ictrl_4_, ictrl_3_,
ictrl_2_, ictrl_1_, ictrl_0_, regin0, regin1, regin2, regin3, srd, sytload_b, tclkl, tclklB, testLoad_b, writeSenseAmpPipe);
u5Input Input(WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, inputDataEven, inputDataOdd, InClk, InClkB, VRefin, chainIn_b,
padin1, pwrdnRcvrs, rclk, serialInEven, serialInOdd, writeD0123, writeD4567);
endmodule

module u5DataIO (mergedWDL_7_, mergedWDL_6_, mergedWDL_5_, mergedWDL_4_, mergedWDL_3_, mergedWDL_2_, mergedWDL_1_, mergedWDL_0_, mergedWDL_15_, mergedWDL_14_, mergedWDL_13_, mergedWDL_12_,
mergedWDL_11_, mergedWDL_10_, mergedWDL_9_, mergedWDL_8_, mergedWDL_23_, mergedWDL_22_, mergedWDL_21_, mergedWDL_20_, mergedWDL_19_, mergedWDL_18_, mergedWDL_17_, mergedWDL_16_, mergedWDL_31_,
mergedWDL_30_, mergedWDL_29_, mergedWDL_28_, mergedWDL_27_, mergedWDL_26_, mergedWDL_25_, mergedWDL_24_, mergedWDL_39_, mergedWDL_38_, mergedWDL_37_, mergedWDL_36_, mergedWDL_35_, mergedWDL_34_,
mergedWDL_33_, mergedWDL_32_, mergedWDL_47_, mergedWDL_46_, mergedWDL_45_, mergedWDL_44_, mergedWDL_43_, mergedWDL_42_, mergedWDL_41_, mergedWDL_40_, mergedWDL_55_, mergedWDL_54_, mergedWDL_53_,
mergedWDL_52_, mergedWDL_51_, mergedWDL_50_, mergedWDL_49_, mergedWDL_48_, mergedWDL_63_, mergedWDL_62_, mergedWDL_61_, mergedWDL_60_, mergedWDL_59_, mergedWDL_58_, mergedWDL_57_, mergedWDL_56_,
mergedWDL_71_, mergedWDL_70_, mergedWDL_69_, mergedWDL_68_, mergedWDL_67_, mergedWDL_66_, mergedWDL_65_, mergedWDL_64_, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_,
dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_,
dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_,
pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_,
pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_, pd3_0_, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_, BusData_8_, BusData_7_, BusData_6_, BusData_5_,
BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_,
dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_,
dataZ3_1_, dataZ3_0_, DAmode_b, mergedRDL_7_, mergedRDL_6_, mergedRDL_5_, mergedRDL_4_, mergedRDL_3_, mergedRDL_2_, mergedRDL_1_, mergedRDL_0_, mergedRDL_15_, mergedRDL_14_, mergedRDL_13_,
mergedRDL_12_, mergedRDL_11_, mergedRDL_10_, mergedRDL_9_, mergedRDL_8_, mergedRDL_23_, mergedRDL_22_, mergedRDL_21_, mergedRDL_20_, mergedRDL_19_, mergedRDL_18_, mergedRDL_17_, mergedRDL_16_,
mergedRDL_31_, mergedRDL_30_, mergedRDL_29_, mergedRDL_28_, mergedRDL_27_, mergedRDL_26_, mergedRDL_25_, mergedRDL_24_, mergedRDL_39_, mergedRDL_38_, mergedRDL_37_, mergedRDL_36_, mergedRDL_35_,
mergedRDL_34_, mergedRDL_33_, mergedRDL_32_, mergedRDL_47_, mergedRDL_46_, mergedRDL_45_, mergedRDL_44_, mergedRDL_43_, mergedRDL_42_, mergedRDL_41_, mergedRDL_40_, mergedRDL_55_, mergedRDL_54_,
mergedRDL_53_, mergedRDL_52_, mergedRDL_51_, mergedRDL_50_, mergedRDL_49_, mergedRDL_48_, mergedRDL_63_, mergedRDL_62_, mergedRDL_61_, mergedRDL_60_, mergedRDL_59_, mergedRDL_58_, mergedRDL_57_,
mergedRDL_56_, mergedRDL_71_, mergedRDL_70_, mergedRDL_69_, mergedRDL_68_, mergedRDL_67_, mergedRDL_66_, mergedRDL_65_, mergedRDL_64_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_,
ictrl_1_, ictrl_0_, pwrdnB, pwrdnRcvrs, rclk, selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
output mergedWDL_7_, mergedWDL_6_, mergedWDL_5_, mergedWDL_4_, mergedWDL_3_, mergedWDL_2_, mergedWDL_1_, mergedWDL_0_, mergedWDL_15_, mergedWDL_14_, mergedWDL_13_, mergedWDL_12_, mergedWDL_11_,
mergedWDL_10_, mergedWDL_9_, mergedWDL_8_, mergedWDL_23_, mergedWDL_22_, mergedWDL_21_, mergedWDL_20_, mergedWDL_19_, mergedWDL_18_, mergedWDL_17_, mergedWDL_16_, mergedWDL_31_, mergedWDL_30_,
mergedWDL_29_, mergedWDL_28_, mergedWDL_27_, mergedWDL_26_, mergedWDL_25_, mergedWDL_24_, mergedWDL_39_, mergedWDL_38_, mergedWDL_37_, mergedWDL_36_, mergedWDL_35_, mergedWDL_34_, mergedWDL_33_,
mergedWDL_32_, mergedWDL_47_, mergedWDL_46_, mergedWDL_45_, mergedWDL_44_, mergedWDL_43_, mergedWDL_42_, mergedWDL_41_, mergedWDL_40_, mergedWDL_55_, mergedWDL_54_, mergedWDL_53_, mergedWDL_52_,
mergedWDL_51_, mergedWDL_50_, mergedWDL_49_, mergedWDL_48_, mergedWDL_63_, mergedWDL_62_, mergedWDL_61_, mergedWDL_60_, mergedWDL_59_, mergedWDL_58_, mergedWDL_57_, mergedWDL_56_, mergedWDL_71_,
mergedWDL_70_, mergedWDL_69_, mergedWDL_68_, mergedWDL_67_, mergedWDL_66_, mergedWDL_65_, mergedWDL_64_, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_,
dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_,
dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_, pd0_1_,
pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_, pd3_3_,
pd3_2_, pd3_1_, pd3_0_, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_;
inout BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_,
dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_,
dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_, dataZ3_0_;
input DAmode_b, mergedRDL_7_, mergedRDL_6_, mergedRDL_5_, mergedRDL_4_, mergedRDL_3_, mergedRDL_2_, mergedRDL_1_, mergedRDL_0_, mergedRDL_15_, mergedRDL_14_, mergedRDL_13_, mergedRDL_12_,
mergedRDL_11_, mergedRDL_10_, mergedRDL_9_, mergedRDL_8_, mergedRDL_23_, mergedRDL_22_, mergedRDL_21_, mergedRDL_20_, mergedRDL_19_, mergedRDL_18_, mergedRDL_17_, mergedRDL_16_, mergedRDL_31_,
mergedRDL_30_, mergedRDL_29_, mergedRDL_28_, mergedRDL_27_, mergedRDL_26_, mergedRDL_25_, mergedRDL_24_, mergedRDL_39_, mergedRDL_38_, mergedRDL_37_, mergedRDL_36_, mergedRDL_35_, mergedRDL_34_,
mergedRDL_33_, mergedRDL_32_, mergedRDL_47_, mergedRDL_46_, mergedRDL_45_, mergedRDL_44_, mergedRDL_43_, mergedRDL_42_, mergedRDL_41_, mergedRDL_40_, mergedRDL_55_, mergedRDL_54_, mergedRDL_53_,
mergedRDL_52_, mergedRDL_51_, mergedRDL_50_, mergedRDL_49_, mergedRDL_48_, mergedRDL_63_, mergedRDL_62_, mergedRDL_61_, mergedRDL_60_, mergedRDL_59_, mergedRDL_58_, mergedRDL_57_, mergedRDL_56_,
mergedRDL_71_, mergedRDL_70_, mergedRDL_69_, mergedRDL_68_, mergedRDL_67_, mergedRDL_66_, mergedRDL_65_, mergedRDL_64_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
pwrdnB, pwrdnRcvrs, rclk, selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe;
supply1 vdd;
supply0 gnd;
u5IOpad IOpad_8_(mergedWDL_71_, mergedWDL_70_, mergedWDL_69_, mergedWDL_68_, mergedWDL_67_, mergedWDL_66_, mergedWDL_65_, mergedWDL_64_, chainOutEven_8_, chainOutOdd_8_, dataIn0_8_, dataIn1_8_,
dataIn2_8_, dataIn3_8_, pd0_8_, pd1_8_, pd2_8_, pd3_8_, testBD_8_, BusData_8_, DAmode_b, mergedRDL_71_, mergedRDL_70_, mergedRDL_69_, mergedRDL_68_, mergedRDL_67_, mergedRDL_66_, mergedRDL_65_,
mergedRDL_64_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, n0, n1, n2, n3, chainOutEven_7_, chainOutOdd_7_, selRegData, sytload_b, tclk,
testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_7_(mergedWDL_63_, mergedWDL_62_, mergedWDL_61_, mergedWDL_60_, mergedWDL_59_, mergedWDL_58_, mergedWDL_57_, mergedWDL_56_, chainOutEven_7_, chainOutOdd_7_, dataIn0_7_, dataIn1_7_,
dataIn2_7_, dataIn3_7_, pd0_7_, pd1_7_, pd2_7_, pd3_7_, testBD_7_, BusData_7_, DAmode_b, mergedRDL_63_, mergedRDL_62_, mergedRDL_61_, mergedRDL_60_, mergedRDL_59_, mergedRDL_58_, mergedRDL_57_,
mergedRDL_56_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_7_, dataZ1_7_, dataZ2_7_, dataZ3_7_, chainOutEven_6_, chainOutOdd_6_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_6_(mergedWDL_55_, mergedWDL_54_, mergedWDL_53_, mergedWDL_52_, mergedWDL_51_, mergedWDL_50_, mergedWDL_49_, mergedWDL_48_, chainOutEven_6_, chainOutOdd_6_, dataIn0_6_, dataIn1_6_,
dataIn2_6_, dataIn3_6_, pd0_6_, pd1_6_, pd2_6_, pd3_6_, testBD_6_, BusData_6_, DAmode_b, mergedRDL_55_, mergedRDL_54_, mergedRDL_53_, mergedRDL_52_, mergedRDL_51_, mergedRDL_50_, mergedRDL_49_,
mergedRDL_48_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_, chainOutEven_5_, chainOutOdd_5_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_5_(mergedWDL_47_, mergedWDL_46_, mergedWDL_45_, mergedWDL_44_, mergedWDL_43_, mergedWDL_42_, mergedWDL_41_, mergedWDL_40_, chainOutEven_5_, chainOutOdd_5_, dataIn0_5_, dataIn1_5_,
dataIn2_5_, dataIn3_5_, pd0_5_, pd1_5_, pd2_5_, pd3_5_, testBD_5_, BusData_5_, DAmode_b, mergedRDL_47_, mergedRDL_46_, mergedRDL_45_, mergedRDL_44_, mergedRDL_43_, mergedRDL_42_, mergedRDL_41_,
mergedRDL_40_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_5_, dataZ1_5_, dataZ2_5_, dataZ3_5_, chainOutEven_4_, chainOutOdd_4_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_4_(mergedWDL_39_, mergedWDL_38_, mergedWDL_37_, mergedWDL_36_, mergedWDL_35_, mergedWDL_34_, mergedWDL_33_, mergedWDL_32_, chainOutEven_4_, chainOutOdd_4_, dataIn0_4_, dataIn1_4_,
dataIn2_4_, dataIn3_4_, pd0_4_, pd1_4_, pd2_4_, pd3_4_, testBD_4_, BusData_4_, DAmode_b, mergedRDL_39_, mergedRDL_38_, mergedRDL_37_, mergedRDL_36_, mergedRDL_35_, mergedRDL_34_, mergedRDL_33_,
mergedRDL_32_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, chainOutEven_3_, chainOutOdd_3_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_3_(mergedWDL_31_, mergedWDL_30_, mergedWDL_29_, mergedWDL_28_, mergedWDL_27_, mergedWDL_26_, mergedWDL_25_, mergedWDL_24_, chainOutEven_3_, chainOutOdd_3_, dataIn0_3_, dataIn1_3_,
dataIn2_3_, dataIn3_3_, pd0_3_, pd1_3_, pd2_3_, pd3_3_, testBD_3_, BusData_3_, DAmode_b, mergedRDL_31_, mergedRDL_30_, mergedRDL_29_, mergedRDL_28_, mergedRDL_27_, mergedRDL_26_, mergedRDL_25_,
mergedRDL_24_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_3_, dataZ1_3_, dataZ2_3_, dataZ3_3_, chainOutEven_2_, chainOutOdd_2_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_2_(mergedWDL_23_, mergedWDL_22_, mergedWDL_21_, mergedWDL_20_, mergedWDL_19_, mergedWDL_18_, mergedWDL_17_, mergedWDL_16_, chainOutEven_2_, chainOutOdd_2_, dataIn0_2_, dataIn1_2_,
dataIn2_2_, dataIn3_2_, pd0_2_, pd1_2_, pd2_2_, pd3_2_, testBD_2_, BusData_2_, DAmode_b, mergedRDL_23_, mergedRDL_22_, mergedRDL_21_, mergedRDL_20_, mergedRDL_19_, mergedRDL_18_, mergedRDL_17_,
mergedRDL_16_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, chainOutEven_1_, chainOutOdd_1_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_1_(mergedWDL_15_, mergedWDL_14_, mergedWDL_13_, mergedWDL_12_, mergedWDL_11_, mergedWDL_10_, mergedWDL_9_, mergedWDL_8_, chainOutEven_1_, chainOutOdd_1_, dataIn0_1_, dataIn1_1_,
dataIn2_1_, dataIn3_1_, pd0_1_, pd1_1_, pd2_1_, pd3_1_, testBD_1_, BusData_1_, DAmode_b, mergedRDL_15_, mergedRDL_14_, mergedRDL_13_, mergedRDL_12_, mergedRDL_11_, mergedRDL_10_, mergedRDL_9_,
mergedRDL_8_, VRefin, chain_b, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, chainOutEven_0_, chainOutOdd_0_,
selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_0_(mergedWDL_7_, mergedWDL_6_, mergedWDL_5_, mergedWDL_4_, mergedWDL_3_, mergedWDL_2_, mergedWDL_1_, mergedWDL_0_, chainOutEven_0_, chainOutOdd_0_, dataIn0_0_, dataIn1_0_, dataIn2_0_,
dataIn3_0_, pd0_0_, pd1_0_, pd2_0_, pd3_0_, testBD_0_, BusData_0_, DAmode_b, mergedRDL_7_, mergedRDL_6_, mergedRDL_5_, mergedRDL_4_, mergedRDL_3_, mergedRDL_2_, mergedRDL_1_, mergedRDL_0_, VRefin,
pwrdnB, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, gnd, gnd, selRegData, sytload_b, tclk, testLoad_b,
writeD0123, writeD4567, writeSenseAmpPipe);
endmodule

module u5Skip (autoskip, framePulseX, mtclk, rxclkL, txclkL);
output autoskip;
input framePulseX, mtclk, rxclkL, txclkL;
supply1 vdd;
supply0 gnd;
tranif1 N45(hnl_669, hnl_670, txclkL);
tranif1 N38(hnl_670, gnd, vdd);
tranif0 P40(hnl_669, vdd, txclkL);
not #(1) I35(autoskip, hnl_197);
ffSync I34(hnl_197, mtclk, hnl_671);
latB I18(hnl_671, hnl_585, framePulseX);
not #(1) U32(rxdly, hnl_147);
not #(1) U31(hnl_147, rxclkL);
not #(1) U30(hnl_672, gnd);
not #(1) U26(hnl_673, gnd);
not #(1) U25(hnl_674, gnd);
not #(1) U24(hnl_410, gnd);
not #(1) U23(hnl_675, gnd);
not #(1) U16(hnl_34, hnl_672);
nand #(1) U6(skb, hnl_585, rout);
nand #(1) U5(hnl_585, skb, tout);
ffA ffT(tout, rxdly, txclkL);
ffA ffR(rout, txclkL, rxdly);
endmodule

module u5DABufH (Out, En_b, In);
output Out;
input En_b, In;
supply1 vdd;
supply0 gnd;
not (weak0,weak1) #(1) U24(hnl_676, hnl_674);
nor #(1) U35(hnl_87, En_b, hnl_674);
tranif1 N31(hnl_677, gnd, In);
tranif1 N30(hnl_676, hnl_677, hnl_673);
tranif0 P29(hnl_676, hnl_678, En_b);
tranif0 P28(hnl_678, vdd, In);
not #(1) U26(hnl_673, En_b);
not #(1) U25(hnl_674, hnl_676);
not #(1) U17(Out, hnl_87);
endmodule

module u5Clk (Rx_2, TestRASB, autoSkip, mclk, mtclk, rclk_b, slow, tclk_b, DAmode_b, DLLByPassMode_b, RxClk, TxClk, VRefin, clearCount_b, framePulseX, powerDownMode, runclk_b, runtclk, turboDLL_b);
output Rx_2, TestRASB, autoSkip, mclk, mtclk, rclk_b, slow, tclk_b;
input DAmode_b, DLLByPassMode_b, RxClk, TxClk, VRefin, clearCount_b, framePulseX, powerDownMode, runclk_b, runtclk, turboDLL_b;
supply1 vdd;
supply0 gnd;
not #(1) U100(hnl_679, hnl_680);
nor #(1) U99(hnl_680, hnl_210, powerDownMode);
not #(1) U98(hnl_210, DAmode_b);
tranif0 N90(hnl_681, vdd, hnl_682);
tranif1 N86(hnl_683, gnd, hnl_682);
tranif1 N96(hnl_684, gnd, hnl_685);
tranif1 N89(hnl_686, gnd, hnl_682);
probe I95(hnl_684);
probe I93(hnl_681);
probe I92(hnl_686);
probe I85(hnl_683);
u5DLL DLL(rclk_b, mtclk, tclk_b, mclk, Vbiasn, rxclkL, txclkL, slow, runclk_b, runtclk, hnl_685, hnl_682, VRefin, hnl_679, turboDLL_b, DLLByPassMode_b);
u5Skip Skip(autoSkip, framePulseX, mtclk, rxclkL, txclkL);
u5Sync Sync(Rx_2, hnl_685, clearCount_b, VRefin, Vbiasn);
u5DABufH DABufH(TestRASB, DAmode_b, hnl_682);
u5InProt RxClkInProt(hnl_685, RxClk);
u5InProt TxClkInProt(hnl_682, TxClk);
endmodule

module u5ClkDrv (rclk, tclk, rclk_b, tclk_b);
inout rclk, tclk;
input rclk_b, tclk_b;
supply1 vdd;
supply0 gnd;
not #(1) U82(rclk, rclk_b);
not #(1) U80(tclk, tclk_b);
endmodule

module u5BCIn (Last_b, OpX_1_, OpX_0_, RawLast, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl_in, VRefin, ackWinOverD, loadLast, powerDownMode, rclk, reset,
standby, writeA45, writeA0123, writeA0123x);
output Last_b, OpX_1_, OpX_0_, RawLast, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_;
input BusCtrl_in, VRefin, ackWinOverD, loadLast, powerDownMode, rclk, reset, standby, writeA45, writeA0123, writeA0123x;
supply1 vdd;
supply0 gnd;
nand #(1) U116(framePulse_b, frameRaw, frameEnableX);
not #(1) U118(frameRaw_b, frameRaw);
not #(1) U115(hnl_281, writeA45);
ltxRB I103(hnl_203, preOpX_b, writeA0123x, reset_b);
ltxRB I37(hnl_194, preOpX_b, writeA45, reset_b);
ltxRB I35(hnl_196, preOp1, writeA0123x, hnl_687);
ltxRB I42(hnl_688, preOp2, writeA0123x, reset_b);
not #(1) U104(pwrdnB, powerDownMode);
nand #(1) U102(hnl_689, preOp1, preOp2, preOpX_b);
not #(1) U99(OpX_1_, hnl_203);
ffSB I98(hnl_690, rclk, standby, powerDownMode);
latBarSB #(1) I101(hnl_691, preOpX_b, writeA0123D, reset);
latBarSB #(1) I11(Last_b, preOp1, loadLast, hnl_692);
ffA I85(writeA0123D, writeA0123, rclk);
not #(1) I97(opcode_b_1_, hnl_196);
not #(1) I96(opcode_b_2_, hnl_688);
not #(1) U90(OpX_0_, hnl_194);
latSB #(1) I86(hnl_693, hnl_689, writeA0123, reset);
nand #(1) U68(hnl_692, hnl_281, reset_b);
ffQBB I61(hnl_694, frameEnable_b, hnl_695, rclk);
nor #(1) U87(bcastWriteA, hnl_693, hnl_691);
nor #(1) I57(frameEnableX, hnl_690, frameEnable_b);
mux21 #(1) I54(hnl_695, framePulse_b, ackWinOverD, hnl_98);
latBEnbA I50(hnl_696, preOp2, rclk);
latBarA I51(preOpX_b, rclk, frameRaw);
latBarA I49(preOp1, rclk, hnl_696);
u5DfLat I47(preOp2, hnl_697, hnl_698, rclk, pwrdnB);
u5OIRcvr I46(hnl_698, hnl_697, powerDownMode, BusCtrl_in, rclk, VRefin);
u5DfLatB I45(frameRaw, hnl_699, hnl_700, rclk, pwrdnB);
u5EIRcvr I44(hnl_699, hnl_700, powerDownMode, VRefin, BusCtrl_in, rclk);
nor #(1) U70(hnl_687, reset, powerDownMode);
nor #(1) U55(hnl_98, hnl_694, reset);
not #(1) U105(RawLast, hnl_696);
not #(1) U1(reset_b, reset);
endmodule

module u5BCOut (padin1, padin2, pad, BCOeven_b, BCOodd_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tclk);
output padin1, padin2;
inout pad;
input BCOeven_b, BCOodd_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tclk;
supply1 vdd;
supply0 gnd;
P4res Rin3(hnl_701, padin1);
P4res Rin2(pad, hnl_701);
P4res Rin1(pad, padin2);
cxfr U603(hnl_702, tclkL_b, tclkL, BCOodd_b);
cxfr U602(hnl_626, tclkL, tclkL_b, BCOeven_b);
latW U604(nkT14, hnl_702);
latW U601(okT13, hnl_626);
not #(1) ind(outd, outc);
not #(1) inb(tclkL, outa);
u5OutMux I590(q0, q1, q2, q3, q4, q5, okT13, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, nkT14, tclkL, tclkL_b);
u5OutDrv I589(pad, q0, q1, q2, q3, q4, q5);
not #(1) inc(outc, tclk);
not #(1) ine(tclkL_b, outd);
not #(1) ina(outa, tclk);
endmodule

module u5BClog (Last_b, OpX_1_, OpX_0_, RawLast, TestCAS, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl, BCOeven_b, BCOodd_b, DAmode_b, VRefin, ackWinOverD,
ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, rclk, reset, standby, tclk, writeA45, writeA0123, writeA0123x);
output Last_b, OpX_1_, OpX_0_, RawLast, TestCAS, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_;
inout BusCtrl;
input BCOeven_b, BCOodd_b, DAmode_b, VRefin, ackWinOverD, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, rclk, reset, standby, tclk, writeA45, writeA0123,
writeA0123x;
supply1 vdd;
supply0 gnd;
tranif1 N137(hnl_703, gnd, BusCtrl_in);
probe I136(hnl_703);
u5BCIn BCIn(Last_b, OpX_1_, OpX_0_, RawLast, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl_in, VRefin, ackWinOverD, loadLast, powerDownMode, rclk, reset,
standby, writeA45, writeA0123, writeA0123x);
u5DABuf I122(TestCAS, DAmode_b, hnl_704);
u5BCOut BCOut(BusCtrl_in, hnl_704, BusCtrl, BCOeven_b, BCOodd_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tclk);
endmodule

module u5Top(SOut, BusCtrl, BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, BusEnable, RxClk, SIn, TxClk, VRef);
output SOut;
inout BusCtrl, BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, BusEnable;
input RxClk, SIn, TxClk, VRef;
supply1 vdd;
supply0 gnd;
lvtncap Cbypass(gnd, vdd);
u5StdCel I1(ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_, AGEGND, AGEING, BCOeven_b, BCOodd_b, BSEL, CAS, CMPF, CMPV, DAmode_b, DLLByPassMode_b, HVST, MPBT, PDMD, RASB, REQ,
ROLLC, RSTR, SDST, testSOut, VCMNA, VRST, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, WML, WPBT, WRITE, ackWinOverD, chain_b, clearCount_b, control_5_, control_4_, control_3_, control_2_,
control_1_, control_0_, deviceEnableMode, enableSOut, framePulseX, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, powerOn, pwrdnRcvrs, reset, resetCap, runtclk,
selRegData, standby, stbybWak, sytload_b, testLoad_b, turboDLL_b, writeA45, writeA0123, writeA0123x, writeD0123, writeD4567, writeSenseAmpPipe, RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_,
RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_, RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_,
RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_,
RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_,
dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_,
dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_, dataZ3_0_, BEevenD, BEoddD, BIMDI, Last_b, OpX_1_,
OpX_0_, PON, RCRED, RawLast, Rx_2, SInRaw_b, SuperBE_b, TestCAS, TestRASB, TestRSTR, VREG, VRefin, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_,
WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_,
WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_,
WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_, autoSkip, bcastWriteA, chainOutEven_8_,
chainOutOdd_8_, clockedBE_b, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_,
dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_,
dataIn3_1_, dataIn3_0_, done, frameEnableX, framePulse_b, frameRaw_b, lowVref, mclk, mtclk, opcode_b_2_, opcode_b_1_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_,
pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_,
pd3_0_, rawBE_b, rclk, runclk_b, slow, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_);
u5MemC MemC(PON, VREG, RCRED, {RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_}, {RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_}, {RDL2_7_, RDL2_6_,
RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_}, {RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_}, {RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_,
RDL4_0_}, {RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_}, {RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_}, {RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_,
RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_}, {RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_}, BIMDI, {WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_}, WML, REQ, WRITE, CAS,
BSEL, {ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_}, RSTR, RASB, MPBT, WPBT, PDMD, HVST, AGEGND, AGEING, VRST, SDST, ROLLC, VCMNA, {WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_,
WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_}, {WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_}, {WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_}, {WDL1_7_,
WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_}, {WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_}, {WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_,
WDL2_1_, WDL2_0_}, {WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_}, {WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_}, {WDL0_7_, WDL0_6_, WDL0_5_,
WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_});
u5TstStr I259();
u5IOgnd hnl_705(gnd, vdd);
u5IOgnd hnl_706(gnd, vdd);
u5IOgnd hnl_707(gnd, vdd);
u5IOgnd hnl_708(gnd, vdd);
u5IOgnd hnl_709(gnd, vdd);
not #(1) U254(pwrdnB, pwrdnRcvrs);
u5BEInpt BEInpt(BEevenD, BEoddD, SuperBE_b, TestRSTR, clockedBE_b, rawBE_b, runclk_b, BusEnable, DAmode_b, VRefin, mclk, powerDownMode, rclk, stbybWak);
u5SIO SIO(SInRaw_b, SOut, VRefin, lowVref, CMPF, CMPV, DAmode_b, SIn, testSOut, VRef, deviceEnableMode, enableSOut, tclk);
u5DataIO DataIO(WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_,
WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_,
WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_,
WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_,
dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_,
dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_, pd1_7_,
pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_, pd3_0_,
testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_, BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_,
BusData_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_,
dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_, dataZ3_0_, DAmode_b, RDL0_7_, RDL0_6_,
RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_,
RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_,
RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_,
RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnB, pwrdnRcvrs, rclk, selRegData, sytload_b, tclk, testLoad_b, writeD0123,
writeD4567, writeSenseAmpPipe);
u5Clk Clk(Rx_2, TestRASB, autoSkip, mclk, mtclk, rclk_b, slow, tclk_b, DAmode_b, DLLByPassMode_b, RxClk, TxClk, VRefin, clearCount_b, framePulseX, powerDownMode, runclk_b, runtclk, turboDLL_b);
u5ClkDrv LeftCk(rclk, tclk, rclk_b, tclk_b);
u5ClkDrv RightClk(rclk, tclk, rclk_b, tclk_b);
u5CCAna CCAna({ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_}, done, {control_5_, control_4_, control_3_, control_2_, control_1_, control_0_}, resetCap, powerOn, VRefin, mclk,
powerDownMode);
u5BClog BClog(Last_b, OpX_1_, OpX_0_, RawLast, TestCAS, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl, BCOeven_b, BCOodd_b, DAmode_b, VRefin, ackWinOverD,
ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, rclk, reset, standby, tclk, writeA45, writeA0123, writeA0123x);
endmodule
`endprotect