`timescale 100ps/100ps
// rdram.v
// Copyright 1992, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
//
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
//
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

//Revision 4.65  1994/07/04  00:57:37  lai
//Finish up ECO#175: rsim 1.8ns revisited.
//
//Revision 4.64  1994/06/28  01:54:41  lai
//Implemented the following ECOs:
//ECO#158: Make the dirty bit confirm to spec and U2.
//ECO#175: RSIM 1.8ns revisited.
//Also added more labels in CAScyc.
//Comment out the resistors in u5OutDrv for rsim reasons.
//Get rid of test logic structures.  Not needed in logic
//simulation.
//
//Revision 4.63  1994/06/21  18:47:17  lai
//Fixed the gated_mclk to u5CCAna routing problem.
//
//Revision 4.62  1994/06/21  00:25:50  lai
//Implemented the following ECOs:
//ECO#156: Get rif of mclk (phase 2)
//ECO#166: Added spare gate
//ECO#170: Added the checkskip and sampleskip signals
//
//Revision 4.61  1994/06/15  20:45:53  lai
//Implemented the following ECOs:
//ECO#162: Get rid of auto refresh logic.
//ECO#169: RSIM 1.8ns speed path fixes.
//ECO#161: Use mtclk instead of tclk for Ack / Nack.
//
//Revision 4.60  1994/06/03  22:34:02  lai
//Implemented the following ECOs:
//ECO #154: Turn off BusData Receivers when not needed.
//          Fix byte mask gated flip flops.
//ECO #155: Eliminated 9 flip flops.
//ECO #164: Timing fix to make the part run at 1.9ns per half clock.
//ECO #156: Get rid of mclk phase 1: use BE sniffer.
//
//Revision 4.59  1994/05/20  06:11:08  lai
//This revision should be the C.1 version of the rdram
//The following ECO was implemented:
//ECO #153: Timing fix for prewriteD4567 and latchAbort_b
//
//Revision 4.58  1994/05/16  22:45:03  lai
//C.0 step metal mask fix.  Implemented the following ECO:
//ECO #152: Turn off Bus Data receiver during a read or row miss.
//          Fix gated clock problem for byte mask flip flops.
//
//Revision 4.57  1994/04/15  04:40:58  lai
//Implemented ECO#149: Fix to have slow mode, DA mode and normal
//                     mode to have identical data out timing.
//
//Revision 4.56  1994/04/14  21:51:24  lai
//Implemented ECO#148: Optimize REQ, nackNoAction_b, and RASpending
//
//Revision 4.55  1994/04/01  23:57:40  lai
//Revision C.0 step tapeout netlist.
//Implemented the following ECO:
//ECO #147: Remove BusEnable term in resetDAmode_b
//Commented out u5TstStr block and leave cells
//
//Revision 4.54  1994/03/31  09:39:17  lai
//Implemented ECO#144: Add more spare gates
//            ECO#146: Optimize framePulse_b critical path.
//
//Revision 4.53  1994/03/25  08:02:48  lai
//Implemented ECO#143: Optimize RASstate4 signal
//
//Revision 4.52  1994/03/25  01:09:46  lai
//Implemented the following ECOs:
//  ECO#132: Remove old regulator stuff.
//  ECO#135: Add powerdown to phase selector.
//  ECO#137: Optimize startCycle_b signal.
//  ECO#138: Optimize earlyDone to REQ signal.
//  ECO#139: Correction of RfshCtl (found by RAVs).
//  ECO#140: DLL Bypass mode change (Part II).
//  ECO#141: Sync setRR with decXferCnt.
//  ECO#142: DLL Bypass mode change (Part III).
//
//Revision 4.51  1994/03/18  10:16:29  lai
//Implemented ECO#133: Optimized startCycle_b and framePulse signals
//            ECO#134: Change reset value of RASinterval register
//
//Revision 4.50  1994/03/12  01:01:27  lai
//Implemented ECO#130: Fix register operation driving data during
//                     standby (Part 2)
//
//Revision 4.49  1994/03/11  08:25:30  lai
//Implemented ECO#127: Auto refresh reduce power fix.
//            ECO#128: Remove dead logic, floating poly and feedthrus.
//            ECO#129: Modify u5CCAna current control.
//
//Revision 4.48  1994/02/26  01:23:55  lai
//Implemented the following ECOs:
//  ECO #126: Set current control to 'b011111 in DA mode.
//
//Revision 4.47  1994/02/25  20:46:27  lai
//This is basically the logical tapeout for C.0 step.
//The following have been implemented:
//  ECO #118: Set RasInterval reset values to optimal ones for U5
//  ECO #119: Set RasInterval reset values to max of U2 and U5
//  ECO #120: Turn off the DLL in DAmode
//  ECO #121: Optimize framePulse_b in u5BCIn block
//  ECO #122: Optimize signal lines that uses excessive feedthrus
//  ECO #123: Optimize u5PreCyc block
//
//Revision 4.46  1994/02/22  00:31:44  lai
//Implemented the following:
//  ECO#100: Check in modified version of u5CdlyCt block.
//  ECO#103: Timing fix for preloadNSWE signal.
//  ECO#104: Fix register read driving data during standby.
//  ECO#105: Optimize writeOp signal in u5OpDeco block.
//  ECO#106: Add reset back to earlyDone
//
//Revision 4.45  1994/02/16  00:11:50  lai
//Implemented the following ECOs for C-step:
//    ECO #74: ROM bit change for read / write delay
//    ECO #77: ROM bit change for MinInterval Register
//    ECO #102: Fix tclk stays on during standby bug
//
//Revision 4.44  1994/02/12  02:02:22  lai
//Implemented the following ECO for C-step:
//    ECO #95: Fix hazard with BEeven block
//    ECO #96: Change all feedthru poly to sandwich poly (layout only)
//    ECO #97: Fix RAScount_b delay problem
//    ECO #98: Misc clean up and optimization (layout only)
//    ECO #99: Get rid of dead logic
//    ECO #100: Completely redo the CdlyCt and support logic
//    ECO #101: Improve drive for signal in u5DAdec block
//
//Revision 4.43  1994/01/27  10:11:13  lai
//Implemented ECO#92: idmiss before auto refresh bug fix.
//            ECO#93: idmiss rsvr cause WML line to assert bug fix.
//
//Revision 4.42  1994/01/06  21:24:06  lai
//Rechecked in version of schematic after lost of data
//from hard drive crash.  Should be functionally be the
//same as revision 4.41.
//
//Revision 4.41  1993/12/17  19:59:15  lai
//Final Revision A.1 to NEC.  Contains the following changes
//over A.0:
//ECO:    Description:              Status:
//----    ------------              -------
//74      ROM bit fix               Not Done
//75      Close operation bug fix   Done
//76      CAS after Refresh bug fix Done
//77      more ROM bit fix          Not Done
//78      Optimize clearRSTR path   Done
//81      Logic optimization        Not Done
//82      Receiver turn off @ stnby Done
//83      SetPD during Imp Rstr bug Done
//84      SRFF race condition bug   Done
//85      Feedthru for WRITEA0123
//        WRITEA0123X, and WRITEA45 Done
//86      Zerbo latch change        Done
//87      Auto current bug fix      Done
//88      Feedthru optimizations    Done
//89      u6CkBufT revision         Done
//-------------------------------------------
//
//Revision 4.40  1993/12/06  23:09:15  lai
//Implemented ECO#84: Fix glitch bug in u5RdTclk block.
//
//Revision 4.39  1993/11/23  22:12:50  lai
//More A.1 stuff:
//ECO#82: Fixed RAVS discovered bug for setting powerdown during
//        Implicit Restore of RAS cycle.
//Also fix up behavioral model for ffSB.
//
//Revision 4.38  1993/11/11  23:58:20  lai
//Release A.1 Contains the following:
//ECO#75: Close operation bug.
//ECO#76: CAS after refresh bug.
//ECO#78: Got rid of clearRSTR to lighten load.
//ECO#82: Receiver standby current improvement.
//The following ECOs are still on hold:
//ECO#74: Read and write delay ROM bits change.
//ECO#77: MinInterval Register ROM bits change.
//ECO#81: Logic optimization to generate spare gates.
//Note: ECO#80 is not possible because of tight rsim timing.
//
//Revision 4.37  1993/10/27  00:54:28  lai
//Implemented ECO#80: Got rid of one RAS overhead.
//Implemented ECO#81: Optimization for u5CDlyCt block.
//
//Revision 4.36  1993/10/23  01:24:36  lai
//Implemented ECO#78: Kill clearRSTR from u5bit{0,1,2,3}
//
//Revision 4.35  1993/10/06  19:28:53  lai
//Implemented ECO#76: CAS followed by a refresh bug
//Implemented ECO#77: ROM bit changes for MinInterval register
//
//Revision 4.34  1993/09/29  22:21:33  lai
//Implemented ECO#74 and ECO#75.  These are changes slated for
//the next metal mask change opportunity.
//ECO#74: ROM bit changes for read and write delay.
//ECO#75: close cycle exception fix.
//
//Revision 4.33  1993/09/16  00:48:39  lai
//Resolved ECO#73
//
//Revision 4.32  1993/09/16  00:09:02  lai
//Update memory core model to add 100ps of margin.  This
//is to solve the ras_ras.v program violation.
//
//Revision 4.31  1993/09/15  21:46:45  lai
//Include ECO#70, #71, and #72
//
//Revision 4.30  1993/09/03  15:56:42  matt
//NEC PR4.0 Transmission
//
//Revision 4.29  1993/09/02  04:22:33  lai
//Incorporated ECO#65, #66, and #67 changes.
//
//Revision 4.28  1993/08/30  22:56:49  matt
// Modified to conform to read/write delays of 7-14 and 1-8 for reads and writes respectively
//
//Revision 4.27  1993/08/29  06:29:23  lai
//Included new core model revision 1.20
//
//Revision 4.26  1993/08/29  04:31:06  lai
//Implemented ECO#63
//
//Revision 4.25  1993/08/29  00:35:54  lai
//Extracted Netlist: Includes ECO#61 and #62
//
//Revision 4.24  1993/08/28  11:50:08  lai
//Implemented ECO#61.  Fixed Powerdown set valid bit bug.
//
//Revision 4.23  1993/08/28  09:03:21  lai
//Implemented ECO#59
//
//Revision 4.22  1993/08/28  07:10:44  lai
//Include proposed fix for ECO#60 (RAS / CAS overlap bug)
//
//Revision 4.21  1993/08/28  01:56:09  lai
//Implemented ECO#55 and ECO#57
//
//Revision 4.20  1993/08/27  08:55:15  lai
//Implemented ECO#35.  Speed path fix for wake_b
//
//Revision 4.19  1993/08/26  22:34:40  lai
//Changed PON signal to add 20 more ns.
//
//Revision 4.18  1993/08/26  21:02:00  lai
//Extracted netlist for ECO#43, #46, #47
//Also added extracted netlist for ECO#37, 44, 49
//
//Revision 4.17  1993/08/25  07:03:02  lai
//Implemented ECO#45
//Spec now conform to solution#2 of Kamisaki's
//FAX circa Aug 13th, 93:
//tWH=2ns and tWS=10ns
//
//Revision 4.16  1993/08/24  06:10:17  lai
//checked in hacked netlist to fix:
//ECO#46: REQ becoming X for 1 clock
//ECO#47: Refresh bank select bug during powerdown
//
//Revision 4.15  1993/08/24  00:45:17  matt
//Fixed timing difference for testmode derived rclk for new u5DLL
//
//Revision 4.14  1993/08/23  07:56:18  lai
//Fix for erroneously driving column address prior to powerdown
//
//Revision 4.13  1993/08/23  05:41:50  matt
//x) included fixed u5DLL
//xx) fix #1 & #2 for gating clockedBE_b & rclk clocking of standby_b
//
//Revision 4.12  1993/08/22  08:27:54  lai
//Contains all the fixes for all the ECOs up to and including
//ECO#42 for logic and timing EXCEPT ECO#35 and ECO#37 (both
//minor timing fixes).
//
//Revision 4.11  1993/08/21  06:50:22  lai
//More timing fixes.  Snap shot of main database
//on Aug 20th night.
//
//Revision 4.10  1993/08/20  14:56:26  lai
//Lots of speed optimizations.  At least ECO#17, 33, 34, and 39
//were rolled in.
//
//Revision 4.9  1993/08/17  23:22:50  lai
//Fixed mux31 in u5CdlyCt to be less pessimistic.
//This is for fixing RAVS failures.
//
//Revision 4.8  1993/08/17  04:51:39  lai
//Fixed powerdown long problem.
//Fixed DAmode error.
//
//Revision 4.7  1993/08/16  06:23:11  lai
//Fixed the AC timing problem related to moving OpX_1_ field
//Lots of speed fixes
//Moved u5BENSad to u5StdCel level
//Fixed the prescalar counter so that it always counts.
//
//Revision 4.6  1993/08/12  06:14:07  lai
//Fixed the terminate bit location for write non-sequential
//address packages.
//
//Revision 4.5  1993/08/12  00:45:20  lai
//Implemented Dr. Pepper change to 5/13
//Moved OpX1 to close bit location
//
//Revision 4.4  1993/08/10  05:26:30  lai
//Implemented the Dr. Pepper change to 2 clock cycles earlier
//than the end of the write delay.
//Fixed a bug in my RAS/Refresh arbitration.
//
//Revision 4.3  1993/08/08  10:12:13  lai
//Previous version does not work because I left out an invertor
//Use revision 4.3 instead.
//
//Revision 4.2  1993/08/08  09:41:24  lai
//Implemented the following:
//ECO 01: Fixed "hazard" found in the serial test mode test.
//ECO 02: Allow NEC to test the core timing parameter tDA.
//ECO 03: Defeature of the close bit.
//ECO 04: RAS and Refresh conflict fix.
//ECO 05: Turn off incRfshInterval when enableRefreshMode is disabled.
//ECO 07: Remove OpX_b<1> from function of writeOp_b
//Also added new_mux41 to help with RAVs X testing
//Changed tWS to be 8ns instead of 10ns
//
//Revision 4.1  1993/08/04  21:13:55  lai
//Checked in u5MemC.v revision 1.18
//Included the newmux41 for u5 opcode decode block.
//Useful for RAVS x-testing
//
//Revision 4.0  1993/07/31  15:19:18  lai
//PR4.0:
//------
//Fixed AR13.
//rsim fixes for speed optimization (20 speed fixes).
//Modified tWS to be 8ns instead of 10ns.
//tRQL is 4ns instead of 8ns.
//
//Revision 1.58  1993/07/26  06:44:19  lai
//Fixed the following BRs:
//BR#31: Register operations now ignores close bit.
//BR#32: The restore RAS cycle after powerdown no longer sets valid bit.
//BR#33: Going into powerdown clears rfshPending latch.
//Backed out of the proposed change for BR#26 and BR#30.  Need to look
//at this problem closer.
//
//Revision 1.57  1993/07/23  01:37:37  lai
//Fixed the following logic bugs:
//BR10: Col Address is driven during power-down
//BR22: Deadlock between (WregBn or Rsrv) and Refresh
//BR26: Broadcast write during refresh or RAS don't NACK
//BR29: RAS before a refresh causes the busy to not go away
//BR30: During refresh WregBn and Rsrv Nacks instead of nonextistent
//Plus Jared's block shuffling for placement issues
//Plus Tom's ongoing work on test and clock logic
//
//Revision 1.56  1993/07/22  02:01:24  matt
//Added 5 verilog tick delay to txdly signal
//Corrected txclkL generation from buf to not
//
//Revision 1.55  1993/07/20  01:34:26  lai
//PR3.3 release
//Put in the fix to strobe the terminate bit in the right place.
//This is for reads.
//
//Revision 1.54  1993/07/18  06:53:12  lai
//Fixed BR#24
//Fixed the address setup time problem with regards to RSTR
//Put in Tom Lee's fixes for TestCtl block
//Uses Greg's latest core model (version 1.16)
//Removed the fudge factor of 700 ps and replace with 200 ps
//Modified tWS to be 8 ns instead of 10 ns because of logic bug
//(this will have to be identified as soon as possible)
//
//Revision 1.53  1993/07/18  01:20:43  matt
//Added the latest G. Davis core model
//NOTE: fudge factor set to 700ps
//This will be removed once Larry fixes Addr to RSTR for explicit restores
//
//Revision 1.52  1993/07/16  06:57:25  lai
//Fixed AC timings for BR#08
//Fixed VeriClk to have proper logic (u5DLL)
//Fixed BR#007
//Note: This release uses the old core model.
//      Also, serial non-sequential address is now 13 clocks
//      instead of 12 clocks.
//
//Revision 1.51  1993/07/14  00:15:58  paley
//Refined last version to include better comments.
//
//Revision 1.50  1993/07/14  00:10:58  paley
//Integrated Dual Core Model technology into latest
//Rdram.v.  Will unify on single core model when possible
//Per Matt G.
//request.
//
//Revision 1.49  1993/07/12  04:57:28  lai
//Put in Tom's changes to u5Sync
//Really solved BR#16.
//Incoporates John Atwood's change for BR#9
//
//Revision 1.48  1993/07/04  07:32:23  lai
//Fixed BR#16 and BR#20.  Some optimization.
//
//Revision 1.47  1993/07/03  03:44:00  lai
//Added labels for RAS counter values
//Fixed the polarity problem in u5BEsnif
//Fixed BR#16: Request sneaks past "burstPending" gate
//Fixed BR#18: 2nd power-down close cycle has too-short RSTR
//Fixed BR#23: Dirty bits selected by wrong BSEL signal
//
//Revision 1.46  1993/06/30  01:53:33  lai
//- Changed writeD4567 timing in u5input block
//- Added in corrected DLL bypass circuitry (BR#5)
//- Fixed clk shutting off before RSTR changes in
//  powerdown (BR#7)
//- Added in fix for req timing (BR#8)
//- Fix problem where column address is being driven
//  during powerdown mode (BR#10)
//- Fix problem with start bit being interpreted
//  as a terminate bit for corner cases (BR#13)
//- Fixed problem with refresh burst initiated by
//  setRR not stopping in time (BR#15)
//- Fixed WregBn writes when it shouldn't.  Now
//  it couldn't. (BR#17)
//
//Revision 1.45  1993/06/23  00:23:45  atwood
//Bus data input pipe changed to delay WDL by 2ns, to allow
//tDH and tMDH to be correct (4ns). Greg's core model, rev 1.7,
//is used with no parameter alterations.
//
//This version is tagged: "PR 3.2"
//
//Revision 1.44  1993/06/22  17:00:58  atwood
//1. Fixed bug that caused terminate bit to be sampled one clock
//   late for writes.
//2. Added UDP model for new std cell ffSync. This got rid of "x"
//   on autoskip bit.
//3. Changed DAmode gating of writeSenseAmpPipe to be the same as
//   original (PR 1.8) design.
//
//This version is tagged: "PR 3.1.2"
//
//Revision 1.43  1993/06/20  01:58:57  atwood
//**> Major change: moved CAS state machine timing later by one
//    clock. This had lots of side effects, but most changes
//    were in u5CAScyc and u5NSWErg.
//Also: fixed problem with when the close bit was set, and put
//in numerous timing fixes.
//
//This model uses rev 1.7 of Greg Davis' core model with tDH
//and tMDH hand-changed from 4ns to 2ns.
//
//This version is tagged: "PR3.1.1"
//
//Revision 1.42  1993/06/11  20:04:40  atwood
// 1. Made delays of latB, latBarA, latBarB = 2 units (to better
//    match actual behavior).
// 2. Fixed bug in refresh logic that caused wrong address to be
//    refetched at the end of a refresh burst. (BR #002)
// 3. Fixed bug in RAScyc logic that caused wrong core timings in
//    refresh mode.
// 4. WriteSenseAmpPipe delay registers bypassed when in DAmode
//    (BR #002).
// 5. Most u5BCOut logic and all of u5BDSync moved to a new standard
//    cell: u5BSNack.
//
//(note: in item 2 above, BR should be BR #001)
//
//This version is tagged: "PR 3.0.5"
//
//Revision 1.41  1993/06/06  01:13:54  atwood
// 1. Modified u5DLL verilog model to shut off clocks during
//    power-down mode. This reflects the behavior of Tom's
//    DLL design.
// 2. Blocked frame pulses while in power-down.
// 3. Completed AR#76 to add a clearRE bit to the Special
//    Function field.
//
//This version is tagged "PR 3.0.4".
//
//Revision 1.40  1993/06/04  01:12:04  atwood
// 1. Updated Greg's core model to rev 1.7
// 2. Fixed bug in u5RshCtl that prevented sucessful exiting of
//    power-down mode.
// 3. Inhibit localREQ and writeMemOp from affecting WRITE signal
//    during DAmode.
//
//This version is tagged "PR 3.0.3"
//
//Revision 1.39  1993/06/02  23:45:18  atwood
// 1. Greg Davis' core model included.
// 2. AR #41 solution D implemented (except for "setRE" function).
// 3. Fixed CAS state machine to correctly handle non-sequential
//    byte-masked writes with counts of 1, 9, 17, or 25.
//
//This version is tagged "PR 3.0.2"
//
//Revision 1.38  1993/05/28  23:57:51  atwood
// 1. Change usages of Vref within the chip to Vrefin.
// 2. Modified NS address latching in u5BENSad and u5BEInpt to
//    improve timings.
// 3. Qualified powerDownReq_b with trueCASstate2_b to avoid
//    asynchronous signal.
// 4. Altered initial loading of rasInterval counter to avoid
//    timing problem in loading counter. Note: this changes
//    recommended values of rasSense, rasPrecharge, and rasImpRestore.
// 5. Added reset to setPD flip-flip.  This may help power-up
//    problems in DA or DLLbyPass modes.
//
//This version is tagged "PR 3.0.1".  Note: the previous two releases
//(ver 1.36, 1.37) correspond to the PR 3.0 released database.
//
//***> Note: this version does NOT use Greg Davis's new core model.
//
//Revision 1.37  1993/05/26  18:34:12  matt
//Initial release of Greg D.'s horrific core model
//
//Revision 1.36  93/05/25  01:19:32  01:19:32  atwood (John Atwood)
// 1. Fixed timing bug in NS address logic - which caused a
//    race condition in verilog. N.B. Use 12 clocks for
//    serial read offset.
// 2. Fixed NS address timing to core.
//
//This rev tagged: "PR 2.5.5"
//
//Revision 1.35  1993/05/24  18:44:14  atwood
// 1. Moved CAS address to core back 1/2 clock - to help meet
//    core timing spec.
// 2. Beefed-up WPBT, MPBT drivers.
// 3. Adjusted inhLoadLast timing so that terminate bit is
//    rejected if it falls within ackWinDelay period (solution
//    D of AR#43).
// 4. Moved u5CMPV block to inside standard cell area.
// 5. Disabled frame pulse recognition while in standby mode.
//
//This version is tagged: "PR 2.5.4"
//
//Revision 1.34  1993/05/22  00:34:19  atwood
//The major change in this revision is the shortened input
//receiver timings, coupled with altered ackDelay, ackWinDelay,
//and readDelay circuits to compensate for the shorter timings.
//This and other changes are:
// 1. Shortened ackDelay, ackWInDelay, and readDelay.
// 2. Refresh prescaler now gets correctly reset when refresh
//    mode is enabled.
// 3. u5DABuf block hdl model hacked to fix an "X" problem in
//    DAmode.  More accurate model coming on next release.
// 4. Added hacked hdl model for xnandpc2 cell to solve a strange
//    "x" problem when reading row address registers.
//
//This version is tagged "PR 2.5.3"
//
//Revision 1.33  1993/05/20  02:43:18  atwood
//Jared's busdata circuits, BusEnable block, and a preliminary
//BusControl block are the main changes. Special hdl models for
//the new input receivers make them emulate the timing of the
//old input samplers. Other changes are:
// 1. Fixed problems in reading back RAS address and ackDelay
//    registers.
// 2. Start CAS delay count on writeA0123x instead of writeA45
//    (timing fix)
// 3. Sped-up RASidle path in u5RAScyc.
// 4. loadMask_b (in u5CAScyc) only enabled during non-sequential
//    operations.
// 5. Enabled tclk to ack transactions when the device is busy.
// 6. Applied Ohno's fix to test logic, removed Dan Paley's fix.
//
//This version is tagged "2.5.2"
//
//Revision 1.32  1993/05/07  21:35:13  atwood
// 1. tclk enabling really works now. (tclk was on all the time before)
// 2. Changed u5BCOut to use non-x-generating latches.
// 3. CMPV block moved to u5Top level.
// 4. Made exiting of powerdown mode more robust.
//
//This version is tagged "PR 2.5.1"
//
//Revision 1.31  1993/05/01  22:21:11  atwood
// 1. Fixed bug introduced in last rev that caused RefInterval[8:6]
//    to reset incorrectly.
// 2. Added gating to prevent unknown id field from corrupting the
//    handling of a transaction with an illegal opcode.
// 3. Incorporated improved u5Sync circuit into reset counter, moved
//    u5Sync into u5Clk block.
// 4. Added back u5Skip, u5DABufH blocks to u5Clk, hdl model of clock
//    is now at u5DLL level.
// 5. Changed RAScycle counting control logic to shorten a critical
//    path.
// 6. Corrected byte masking of first octbyte of a WseqBpb (write-per-
//    bit, non-persistant).
// 7. Added inverter to testCntReset_b signal in u5TstCtl, per Dan
//    Paley's request.
//
//This version is tagged: "PR 2.1"
//
//Revision 1.30  1993/04/29  01:05:44  atwood
// 1. Fixed illegal opcode decoding for memory reads.
// 2. Inverted polarity of reset value of RefInterval register,
//    to match spec. (Note: this will affect tests that check
//    the RefInterval value).
// 3. Fixed problem in exiting power-down mode.
// 4. Incorporated Jared's SIO block. HDL models are used for
//    u5CMPV, u5SioMux, u5SoDrv, and u5OscMJ.
//
//This revision is tagged PR 2.0.6.
//
//Revision 1.29  1993/04/27  01:14:14  atwood
// 1. Fixed bug that caused Delay register to get trashed
//    when a register write is preceeded by a memory write
//    with writePipeDelay = 2 clks.
// 2. Numerous minor optimizations to reduce critical paths,
//    especially the startCycle path, and regOp decode paths.
//
//This version is tagged "PR 2.0.5".
//
//Revision 1.28  1993/04/24  19:23:49  atwood
// 1. Fixed logic that inhibited Count/Adr byte masking during
//    Non-sequential writes.
// 2. Refresh logic now working! Give it a try.
//
//This version of the netlist is tagged "PR 2.0.4"
//
//Revision 1.27  1993/04/22  02:10:30  atwood
// 1. Fixed bugs introduced in rev 1.26 that broke Rnsq and
//    WnsqBpb operations.
// 2. Fixed bug that hurt most byte-masked operations.
// 3. Changed packetBSELx generation to allow correct explicit
//    restores to happen during burst refreshes.
//This version of the netlist is tagged "PR 2.0.3".
//
//Revision 1.26  1993/04/20  01:48:14  lai
//Added optimized logic on the u5opDeco block.
//Changes made relating to refresh.
//
//Revision 1.25  1993/04/19  21:23:56  atwood
//1. Fixed bug that caused Close cycle to start prematurely.
//2. Improved latWA hdl model (doesn't cause rfsh counter to go X).
//3. Various fixes related to refresh, including victor's new
//   countupx cell.
//
//Revision 1.24  1993/04/16  23:56:30  atwood
//1. Power-down mode now works correctly.
//2. Larry's even-less pessimistic latches, ffs, and hitsel UDP
//   models are used.
//3. BSEL driven to core at correct time for RAS cycles.
//4. Ohno's test logic changes done (from FAXs of 4/12 and 4/16/93).
//5. Larry's improved illegal opcode decoder incorporated.
//6. Jared's wider writeSenseAmpPipe signal generated.
//
//Revision 1.23  1993/04/15  02:27:40  lai
//Translated the hitSel block into a primitive model.  This is
//to fix the Address Select problem and add less pessimism.
//
//Revision 1.22  1993/04/13  17:47:05  lai
//Modified the following flip flops to add less pessimism:
//ffBarRA, ffRA, ffBNcRA, and ffSB
//
//Revision 1.21  1993/04/09  21:55:02  lai
//Changed latch models to properly propagate x's.
//
//Revision 1.20  1993/04/08  23:40:47  atwood
//PR 2.0 release:
//1.  Moved NSAdr<5:0> circuits to u5BENSad in Std Cell Area.
//2.  Fixed timing problem with NSAdr logic (only affected ver 1.19)
//3.  Made refresh during powerdown work correctly.
//4.  Minor timing fixes.
//
//Revision 1.19  1993/04/07  22:50:05  atwood
//Minor changes to power-down refresh, speed improvements,
//Vext1..5 pins power pins added, ffEnB's added in u5BEInpt.
//This version corresponds to PR 1.9 (a.k.a. PR 2.0).
//
//Revision 1.18  1993/04/06  23:06:53  atwood
//Following fixes:
//1. Added circuit to inhibit Last bit for serial packets that overlap
//   AckWindow. (AR43)
//2. Fixed bug that caused error in long MPBNP (WseqBpb) transfers.
//3. Entering powerdown mode works. Exiting doesn't work.
//
//Revision 1.17  1993/04/02  22:53:00  atwood
//Mostly fixes for power-down mode (power-down is not
//all working yet). Some rsim-discovered speed fixes.
//Labelled PR1.8.3
//
//Revision 1.16  1993/03/27  23:06:08  atwood
//Many small speed enhancements, plus:
//1. Fixed NSWE bug introduced in PR1.8.
//2. RAS state machine redone to provide correct core timings. New
//   rasIntervals recommended:
//      rowPrecharge = 1
//      rowSense = 7
//      rowImpRestore = 14
//      rowExpRestore = 4
//3. Overlapping RAS cycles not queued. (AR24)
//4. AckWinDelay of 5 eliminated. (AR34)
//5. u5VeriClk replaced by u5Clk, using VeriClk as hdl model.
//
//Revision 1.15  1993/03/23  23:55:54  atwood
//Fixed last-minute bug with CAS cycle. Also added hdl models for
//u5InLat2, u5InLat3, u5InLat4. NSWE gated clock improved.
//
//Revision 1.14  1993/03/23  17:28:58  atwood
//PR 1.8 release. Changes:
// 1. Livelock circuits removed.
// 2. More big buffers added, misc. speedups resulting from rsim.
// 3. Leading edge of RSTR delayed by 1 clk on close and exp. restore
//    cycles.
// 4. Trailing edge of RASB to core delayed by 1 clk.
// 5. Fixedbug that caused REQ to stay active during ID misses.
//
//Revision 1.13  1993/03/20  19:39:53  atwood
//Larry's less pessimistic latch and ff hdl models used.
//No logic changes.
//
//Revision 1.12  1993/03/19  02:13:20  atwood
//Added more net names for state variables. No logic changes.
//
//Revision 1.11  1993/03/17  22:18:06  atwood
//PR 1.7 database. Major changes:
//1. Byte masking disabled for non-byte-masked NonSequential writes (AR42)
//2. ACError circuits removed
//3. Large (EE & FF) buffers added to control circuits. Other buffers
//   increased from CC to DD. Other rsim-discovered speed-ups added.
//4. New RAS state machine - runs Close cycles correctly, has better
//   core timings. Note: new RasInterval values needed, see AR39.
//5. u5DABuf changed (affects only test mode).
//6. Other minor fixes and documentation clean-ups.
//
//Revision 1.10  1993/02/25  23:25:15  atwood
//Only change: added netnames to Input Sampler outputs for snooping.
//
//Revision 1.9  1993/02/25  17:15:59  atwood
//Netlist used in PR 1.6. rsim netlist labelled *.224
//  Powerdown timing fixed per AR9.
//  RowImpRestore and RowExpRestore swapped.
//
//Revision 1.8  1993/02/23  00:16:18  atwood
//minor fixes in powerdown logic, u5tCkDly simplified for rsim.
//
//Revision 1.7  1993/02/19  22:43:27  atwood
//Updates in netlist.219, which include:
//1.  K. Ohno's improved RAScyc fixes
//2.  Consolidated RDL and WDL lines in RWDfthru
//3.  VBias removed from all input samplers
//4.  powerDownMode added to all input samplers
//5.  ChainOutOddD_b signals removed from u5Output cell
//6.  ictrl<5:0> routed through u5CCAna cell
//
//Revision 1.6  1993/02/17  03:25:17  atwood
//Removed IObuf hdl model (for rsim), fixed Close -> RAS & CAS, AR7 done,
//changed refresh to higher priority than Close, fixed bit1 ADR bug.
//
//Revision 1.5  1993/02/12  23:11:37  atwood
//Non-seq. mode working, fixed BE -> standby, fixed Last bit sampling.
//
//Revision 1.4  1993/02/04  18:25:09  atwood
//Changes to test mode logic by K. Ohno
//
//Revision 1.3  1993/01/31  21:43:53  atwood
//Shortened busy period by one clock, sped up paths related to earlyDone.
//
//Revision 1.2  1993/01/27  23:26:35  atwood
//schematics handed out for logic design review. Misc. changes.
//
//Revision 1.1  1993/01/25  19:00:01  lai
//Initial revision
//

// Verilog netlist of
//"/home/earth/usr2/u5/revD.0/chip/u5Top"
module NEC_18M_RDRAM(BusCtrl, BusData, BusEnable, SOut, SIn, TxClk, RxClk, VRef);

// This is an interposer module which wraps around the rdram model
// generated from the schematics and presents the standard rambus rdram
// interface to the user. The wrapper is needed for three reasons:
// 1. maps bus BusData[8:0] to scalar pins {BusData[8]..BusData[0]}
//    the netlister breaks up buses into individual scalar signals
// 2. changes name of rdram from device specific schematic name (e.g. u5top)
//    to generic name rdram.

// wire declarations for standard Rambus rdram interface
inout               BusCtrl;
inout [8:0]         BusData;
input               BusEnable;
output              SOut;
input               SIn;
input               TxClk;
input               RxClk;
input               VRef;

`protect
// u5Top is name of rdram in model created from device schematics
// this model has BusData[8:0] bus broken into individual pins.
u5Top top(
        .BusCtrl(BusCtrl),
        .BusData_8_(BusData[8]),
        .BusData_7_(BusData[7]),
        .BusData_6_(BusData[6]),
        .BusData_5_(BusData[5]),
        .BusData_4_(BusData[4]),
        .BusData_3_(BusData[3]),
        .BusData_2_(BusData[2]),
        .BusData_1_(BusData[1]),
        .BusData_0_(BusData[0]),
        .BusEnable(BusEnable),
        .SOut(SOut),
        .SIn(SIn),
        .TxClk(TxClk),
        .RxClk(RxClk),
        .VRef(VRef));

endmodule

// HDL models

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5CCAna/u5CCAna.v"
module u5CCAna (ictrl, done, control, resetCap, powerOn, VRef, gated_mclk);
    inout [5:0] ictrl;
    output done;
    input [5:0] control;
    input resetCap;
    input powerOn;
    input VRef;
    input gated_mclk;

    reg done;

always @(negedge resetCap)
        if (control == 6'b0)
           begin
           #40
           done = 1;
           end
        else
           begin
           # ((control + 1) * 40)
           done = 1;
           end

always @(posedge resetCap)
        #40 done = 0;

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5Sync/u5Sync.v"
// derived from u5Sync cell schematic dated 8/18/93
module u5Sync (q, clk_b, s_b, vref, Vbiasn);
output q;
input Vbiasn, clk_b, s_b, vref;

supply1 vddA;
supply0 gndA;

tranif0 #(8) P83(n5, vddA, clk_b);
tranif0 P100(n5, vddA, s_b);
tranif0 P4(hnl_0, vddA, hnl_1);
tranif0 P23(hnl_2, vddA, n3);
tranif0 P17(hnl_3, vddA, hnl_1);
tranif0 P20(n4, hnl_3, clkL_b);
tranif0 P10(n1, hnl_4, clkL);
tranif0 P3(n1, hnl_0, clkL_b);
tranif0 P18(n4, hnl_2, clkL);
tranif0 P12(hnl_4, vddA, n2);
not #(1) U122(q, hnl_5);
// make edge verilog-able
not #(0) U102(clkL_b, clkL);
not #(1) U91(hnl_6, hnl_7);
not #(1) U90(hnl_7, n5);
not #(1) U92(clkL, hnl_6);
not #(1) U8(n3, n2);
not #(1) U22(hnl_1, n4);
not #(1) U35(hnl_5, hnl_1);
nand #(1) U7(n2, s_b, n1);
tranif1 N115(hnl_8, gndA, s_b);
tranif1 #(8) N71(n5, hnl_8, clk_b);
tranif1 N24(n4, hnl_9, clkL_b);
tranif1 N21(n4, hnl_10, clkL);
tranif1 N16(hnl_9, gndA, n3);
tranif1 N9(hnl_11, gndA, n2);
tranif1 N2(n1, hnl_12, clkL);
tranif1 N13(n1, hnl_11, clkL_b);
tranif1 N26(hnl_10, gndA, hnl_1);
tranif1 N1(hnl_12, gndA, hnl_1);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5DLL/u5DLL.v"
// Verilog netlist of
//"/home/earth/usr2/u5/rev1.0/chip/pr4.0/u5DLL"

// HDL file -
// simple latch for u5PhaCmp functionality
primitive latClk (Q, EN, D);
    output Q; reg Q;
    input EN;
    input D;

table
//     EN    D:state:   output/next state
        0   ? :  ?  :     - ; // no change

        1   0 :  ?  :     0 ; // transparent data
        1   1 :  ?  :     1 ; // transparent data
        1   x :  ?  :     x ; // latch data

        x   0 :  1  :     1 ; // reducing pessimism
        x   1 :  0  :     0 ; // reducing pessimism
        p   ? :  ?  :     - ;

endtable
endprimitive

// HDL file - 
// /home/earth/usr2/u5/rev1.0/chip/pr4.0/u5ClkAmp/u5ClkAmp.v"
module u5ClkAmp (clkout, clkout_b, dccrfb_b, vref, pwrDn, dccrfb, clkin, Vbiasn);
    output clkout;
    output clkout_b;
    input dccrfb_b;
    input vref;
    input pwrDn;
    input dccrfb;
    input clkin;
    input Vbiasn;
latClk #(0) mg1(clkout_b, ~pwrDn, clkin);
not #(0) (clkout, clkout_b);

endmodule


// End HDL models


module u5TstCkD (tstclk_b, tstclk);
output tstclk_b;
input tstclk;
supply1 vdd;
supply0 gnd;
not #(0) U4(tstclk_b, hnl_0);
not #(0) U3(hnl_0, hnl_1);
not #(0) U1(hnl_1, tstclk);
endmodule

module u5TstCkA (tstclk, bypass_b, rxclk);
output tstclk;
input bypass_b, rxclk;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

not (weak0,weak1) #(1) U43(hnl_3, hnl_2);
nor #(0) U37(hnl_4, bypass_b, hnl_2);
not #(0) U36(tstclk, hnl_4);
not #(1) U35(hnl_5, bypass_b);
not #(1) U39(hnl_2, hnl_3);
tranif0 P32(hnl_6, vddA, rxclk);
tranif0 P34(hnl_3, hnl_6, bypass_b);
tranif1 N44(hnl_7, gndA, rxclk);
tranif1 N38(hnl_3, hnl_7, hnl_5);
endmodule

module u5TstClk (Vbiasn, slow, tstclk_b, DLLByPassMode_b, ckin, pwrDn, rxclk);
output Vbiasn, slow, tstclk_b;
input DLLByPassMode_b, ckin, pwrDn, rxclk;
supply1 vdd;
supply0 gnd;
u5TstCkD TstCkD(tstclk_b, hnl_8);
u5TstCkA TstCkA(hnl_8, DLLByPassMode_b, rxclk);
assign slow=0;
assign Vbiasn=0;
endmodule

module u5CkBufR (mclk, rclk_b, bypass_b, pwrDn, rckdrv, runclk_b, testCkL_b);
output mclk, rclk_b;
input bypass_b, pwrDn, rckdrv, runclk_b, testCkL_b;
supply1 vdd;
supply0 gnd;
cxfr U1020(m6, run_b, hnl_9, hnl_10);
cxfr U1028(m6, hnl_9, run_b, hnl_11);
cxfr U1003(m1, en_b, hnl_12, hnl_10);
cxfr U1036(m1, hnl_12, en_b, hnl_13);
nand #(1) U1004(run_b, hnl_14, bypass_b);
nand #(1) U1033(en_b, hnl_15, bypass_b);
not #(0) U1052(r6, m3);
not #(0) U1051(r5, m2);
not #(0) U1049(m5, m4);
not #(0) U1029(m4, m3);
not #(0) U1042(m3, m2);
not #(0) U1018(m2, m1);
// same as old model timing
not #(5) U1048(rclk_b, m9);
not #(0) U1047(m9, m8);
not #(0) U1015(m8, m7);
not #(0) U1011(m7, m6);
not #(0) U1046(hnl_9, run_b);
// same as old model timing
not #(6) U1050(mclk, m5);
not #(0) U1034(hnl_11, rckdrv);
not #(0) U1039(hnl_13, rckdrv);
not #(0) U1035(hnl_14, runclk_b);
not #(0) U1040(hnl_10, hnl_16);
not #(0) U1037(hnl_16, testCkL_b);
not #(0) U1043(hnl_15, pwrDn);
not #(1) U1008(hnl_12, en_b);
endmodule

module u5RDLL (mclk, rclk_b, rxclkL, Vbiasn, bypass_b, pwrDn, runclk_b, rxclk, testCkL_b, turboDLL_b, vref);
output mclk, rclk_b, rxclkL;
input Vbiasn, bypass_b, pwrDn, runclk_b, rxclk, testCkL_b, turboDLL_b, vref;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

u5CkBufR CkBufR(mclk, rclk_b, bypass_b, pwrDn, rxclk, runclk_b, testCkL_b);
u5ClkAmp RClkAmp(hnl_40, hnl_41, 1'b0, vref, pwrDn, 1'b0, rxclk, Vbiasn);
not #(0) U64(rxclkL, hnl_42);
not #(0) U63(hnl_42, hnl_43);
not #(0) U62(hnl_43, hnl_41);
not #(1) U65(rtp1, hnl_40);
not #(1) U47(turbo, turboDLL_b);
endmodule

module u5CkBufT (mtclk, tclk_b, tclkfb_b, bypass_b, pwrDn, runtclk, tckdrv, testCkL_b, DAmode_b);
output mtclk, tclk_b, tclkfb_b;
input bypass_b, pwrDn, runtclk, tckdrv, testCkL_b, DAmode_b;
supply1 vdd;
supply0 gnd;
nand #(1) U1145(hnl_44, gnd, vdd);
nand #(1) U1143(hnl_45, vdd, vdd);
nand #(1) U1139(run_b, bypass_b, runtclk);
nand #(1) U1055(en_b, hnl_46, bypass_b);
not #(0) U1022(m2, m1);
not #(0) U1147(hnl_47, en_b);
not #(0) U1115(hnl_48, hnl_49);
not #(0) U1146(t6, m3);
not #(1) U1134(tclk_b, m9);
not #(1) U1133(m9, m8);
not #(1) U1091(m8, m7);
not #(1) U1049(m7, m6);
// delay to match old model
not #(5) U1136(mtclk, m5);
not #(0) U1135(m5, m4);
not #(0) U1088(m4, m3);
not #(0) U1079(t5, m2);
not #(0) U1031(hnl_50, tckdrv);
not #(0) U1127(tclkfb_b, hnl_51);
not #(0) U1126(hnl_52, hnl_53);
not #(0) U1122(hnl_53, mtclk);
not #(0) U1123(hnl_54, mtclk);
not #(0) U1129(hnl_55, hnl_56);
not #(0) U1121(hnl_56, hnl_54);
not #(0) U1014(hnl_57, tckdrv);
not #(0) U1140(hnl_46, pwrDn);
not #(0) U1137(hnl_58, run_b);
not #(0) U1007(m3, m2);

// Hacked in to comply with ECO#149
xor #(0) U1169(AR123, testCkL_b, DAmode_b);

not #(0) U1118(hnl_49, AR123);
cxfr U1124(hnl_51, hnl_52, hnl_55, hnl_44);
cxfr U1125(hnl_51, hnl_55, hnl_52, hnl_45);
cxfr U1105(m6, run_b, hnl_58, hnl_48);
cxfr U1071(m6, hnl_58, run_b, hnl_57);
cxfr U1062(m1, en_b, hnl_47, hnl_48);
cxfr U1039(m1, hnl_47, en_b, hnl_50);
endmodule

module u5TDLL (mtclk, tclk_b, txclkL, Vbiasn, bypass_b, pwrDn, runtclk, testCkL_b, turboDLL_b, txclk, vref, DAmode_b);
output mtclk, tclk_b, txclkL;
input Vbiasn, bypass_b, pwrDn, runtclk, testCkL_b, turboDLL_b, txclk, vref, DAmode_b;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

not #(0) U69(txclkL, hnl_84);
not #(0) U68(hnl_84, hnl_85);
not #(1) U67(t1, hnl_82);
not #(0) U66(hnl_85, hnl_83);
not #(1) U47(turbo, turboDLL_b);
u5CkBufT U9(mtclk, tclk_b, clkfb, bypass_b, pwrDn, runtclk, ~txclk, testCkL_b, DAmode_b);
u5ClkAmp TClkAmp(hnl_82, hnl_83, 1'b0, vref, pwrDn, 1'b0, txclk, Vbiasn);

endmodule

module u5DLL (rclk_b, mtclk, tclk_b, mclk, Vbiasn, rxclkL, txclkL, slow, runclk_b, runtclk, RxClk, TxClk, VRef, powerDownMode, turboDLL_b, DLLByPassMode_b, DAmode_b);
output Vbiasn, mclk, mtclk, rclk_b, rxclkL, slow, tclk_b, txclkL;
input DLLByPassMode_b, RxClk, TxClk, VRef, powerDownMode, runclk_b, runtclk, turboDLL_b, DAmode_b;
supply1 vdd;
supply0 gnd;

supply0 gndA;
supply1 vddA;

u5TstClk TstClk(Vbiasn, slow, tstclk_b, DLLByPassMode_b, rxclkL, powerDownMode, RxClk);
u5RDLL RDLL(mclk, rclk_b, rxclkL, Vbiasn, DLLByPassMode_b, powerDownMode, runclk_b, RxClk, tstclk_b, turboDLL_b, VRef);
u5TDLL TDLL(mtclk, tclk_b, txclkL, Vbiasn, DLLByPassMode_b, powerDownMode, runtclk, tstclk_b, turboDLL_b, TxClk, VRef, DAmode_b);
endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5InLat1/u5InLat1.v"
module u5InLat1 (Q_b, EN, D, ENB);
    output Q_b;
    input EN;
    input D;
    input ENB;

  latBarB I0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5InLat2/u5InLat2.v"
module u5InLat2 (toLat4, pd, EN, D_b, ENB);
    output toLat4;
    output pd;
    input EN;
    input D_b;
    input ENB;

  wire   D, Q_b;
  assign D      = ~D_b;
  assign toLat4 = ~Q_b;
  assign pd     = ~Q_b;
  latBarB I0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5InLat3/u5InLat3.v"
module u5InLat3 (dataIn, toLat4, EN, D, ENB);
    output dataIn;
    output toLat4;
    input EN;
    input D;
    input ENB;

  wire   Q_b;
  assign dataIn = ~Q_b;
  assign toLat4 = ~Q_b;
  latBarB I0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5InLat4/u5InLat4.v"
module u5InLat4 (WD, D, EN, ENB);
    output WD; 
    input D;
    input EN;
    input ENB;

  wire   Q;
  assign WD = Q;

  latB I0 (Q, D, EN);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5pd2Lat/u5pd2Lat.v"
module u5pd2Lat (pd, EN, D_b, ENB);
    output pd;
    input EN;
    input D_b;
    input ENB;

  wire   D, Q_b;
  assign D      = ~D_b;
  assign pd     = ~Q_b;
  latBarB latBarB0 (Q_b, EN, D);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5InClk/u5InClk.v"
module u5InClk (InClk, InClkB, rclk);
    output InClk;
    output InClkB;
    input rclk;

supply1 vdd;
supply0 gnd;
not I5(outd, outc);
not #(1) I6(InClk, outa);
not #(1) U1(InClkB, outd);
not #(1) U4(outc, rclk);
not #(1) U3(outa, rclk);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5OutClk/u5OutClk.v"
module u5OutClk (tclkl, tclklB, tclk);
    output tclkl;
    output tclklB;
    input tclk;

supply1 vdd;
supply0 gnd;
not #(1) I6(tclkl, outa);
not I5(outd, outc);
not #(1) U3(outa, tclk);
not #(1) U1(tclklB, outd);
not #(1) U4(outc, tclk);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5SioMux/u5SioMux.v"
primitive u5SioMux (Y_B, C, B, A, SelC, SelA, SelB);
    output Y_B; reg Y_B;
    input C;
    input B;
    input A;
    input SelC;
    input SelA;
    input SelB;

table
//      C B A   SelC SelA SelB : state : Y_B/next state
        1 ? ?   1    0    0    :   ?   :   0 ;
        0 ? ?   1    0    0    :   ?   :   1 ;
        ? 1 ?   0    0    1    :   ?   :   0 ;
        ? 0 ?   0    0    1    :   ?   :   1 ;
        ? ? 1   0    1    0    :   ?   :   0 ;
        ? ? 0   0    1    0    :   ?   :   1 ;
        ? ? ?   0    0    0    :   ?   :   - ; //no change
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5SoDrv/u5SoDrv.v"
// a simple model of u5SoDrv. The charge pump oscillator is ignored.
module u5SoDrv (oscen, pad, InB, osc, PDenable);
    output oscen; reg oscen;
    output pad;
    input InB;
    input osc;
    input PDenable;

	supply1 vdd;
	supply0 gnd;

//	pullup (strong1)(oscen);

	nor #(1) U61(n5, n1, n3);
	nor #(1) U60(n4, n1, InB);
	tranif1 N59(pad, gnd, n5);
	tranif1 N58(vdd, pad, n4);
	not #(1) U79(n3, InB);
	not #(1) U62(n1, PDenable);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5OscMJ/u5OscMJ.v"
module u5OscMJ (osc, oscen);
    output osc; reg osc;
    input oscen;

	initial
	begin
	    osc = 1;
	end

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5OIRcvr/u5OIRcvr.v"
module u5OIRcvr (QB, Q, pwrdn, DB, CLK, D);
    output QB;
    output Q;
    input pwrdn;
    input DB;
    input CLK;
    input D;

	not #(0) I1300(CLK_b, CLK);
        ffSB #(1) I1301(QB, CLK_b, DB, pwrdn);
        not #(0) I1302(Q, QB);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5EIRcvr/u5EIRcvr.v"
module u5EIRcvr (Q, QB, pwrdn, D, DB, CLK);
    output Q;
    output QB;
    input pwrdn;
    input D;
    input DB;
    input CLK;

        ffSB #(1) I1200(QB, CLK, DB, pwrdn);
        not #(0) I1201(Q, QB);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5BEsnif/u5BEsnif.v"
module u5BEsnif (Out_b, VRef, In_b);
    output Out_b; reg Out_b;
    input VRef;
    input In_b;

always @ (In_b) begin
        Out_b = In_b;
    end

endmodule

// HDL file - 
// /home/earth/usr2/u5/rev1.0/cad/schema/P4res/P4res.v"
module P4res (PLUS, MINUS);
    inout PLUS;
    inout MINUS;

    tran (PLUS, MINUS);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5MemC/u5MemC.v"
// u5MemC.v - behavioural model for the U5 core
//
// Copyright 1992, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
// 
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
// 
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

// Revision 1.21  1993/11/04  18:51:52  harlan
// Add parens around specparam expressions as workaround for verilog 1.7 bug.
// Should not be necessary but allows turbo verilog to run.
//
// Revision 1.20  1993/08/29  04:44:45  davis
// Added workaround for Verilog bug, such that if a write is attempted to
// the cache or the core with any addressing bit as X, all elements will be
// written as X.  The Verilog bug is that it does not 'blend' the data for
// all potential addresses.
// Also, corrected the timing check for tCFR.
//
// Revision 1.19  1993/08/26  22:57:21  davis
// Changed tWH to 2 ns per Lai mail of 93/08/25, ref. Ishikawa-san's fax.
// Changed tPON representation to 80 ns, per Lai/Griffin request.
//
// Revision 1.18  1993/08/04  18:15:13  davis
// Added condition for timing check of WE to be done only when WRITE.
//
// Revision 1.17  1993/07/21  21:01:04  davis
// Removed conditional from width check for tRP.
//
// Revision 1.16  1993/07/17  00:18:05  davis
// Changed precharge criterium for CAS write to match CAS read.
//
// Revision 1.15  1993/07/16  20:19:17  davis
// Updated redundancy control signals to handle short RQL pulsed without
// supressing them.
// Added definition so that the selection of RQL4 is the default.
//
// Revision 1.14  1993/07/14  17:24:19  davis
// Added required switch for tRQLmin: RQL4 or RQL8, to allow speculative spec.
//
// Revision 1.13  1993/07/07  21:45:29  davis
// Corrected error in computation of array index for RAS reads and writes.
//
// Revision 1.12  1993/06/28  21:25:18  davis
// Updated tDH and tRQL parameters to newly agreed values.
//
// Revision 1.11  1993/06/23  01:16:34  davis
// Made X transition on PON behaviour conditional on definition of XPONXORE.
//
// Revision 1.10  1993/06/22  22:02:12  davis
// Altered PON signal timing to work around Verilog anomaly.
//
// Revision 1.9  1993/06/21  20:10:47  davis
// Corrected INFOCORE message for CAS write to show effect of latched WE.
//
// Revision 1.8  1993/06/15  21:37:57  davis
// Incorporated new timing specs tRSA, tRSB, tCSA and tRQL.
// Updated timing limits on other parameters to letter of Feb. 17/93.
// Updated PON behaviour to traverse from x to 0 to x to 1, as planned behavior.
//
// Revision 1.7  1993/06/03  20:49:30  davis
// Added condition to prevent spurious messages tRAH2 timing violations.
//
// Revision 1.6  1993/06/03  18:03:14  davis
// Added term to CAS write to make it work for enable=x.
//
// Revision 1.5  1993/06/02  23:40:00  davis
// Added informative messages for CAS Read/Write and RAS Read/Write gated by
// conditional compile with definition of INFOCORE.
//
// Revision 1.4  1993/06/02  21:43:42  davis
// Version for phase in of the core model into the u5 netlist.  This version
// has been hacked by Matt G. to work with the netlist.  Enhancements and
// corrections to the model are known to be outstanding.
//
// Revision 1.3  1993/03/27  00:46:30  davis
// Added #0 to code that clears caches in PDMD to ensure order of evaluation.
//
// Revision 1.2  1993/03/27  00:44:13  davis
// Added support for powerdown mode.
//
// Revision 1.1  1993/03/16  01:38:23  davis
// Initial revision
//

`ifdef NICE_PIN_ORDER
module u5MemC(
              WDL8,			 // write data
              WDL7,			 // write data
	      WDL6,			 // write data
	      WDL5,			 // write data
	      WDL4,			 // write data
	      WDL3,			 // write data
	      WDL2,			 // write data
	      WDL1,			 // write data
	      WDL0,			 // write data
              RDL8,			 // read data
              RDL7,			 // read data
	      RDL6,			 // read data
	      RDL5,			 // read data
	      RDL4,			 // read data
	      RDL3,			 // read data
	      RDL2,			 // read data
	      RDL1,			 // read data
	      RDL0,			 // read data
      	      WE,			 // write enable
    	      CAS,			 // column address strobe
    	      WRITE,			 // write, controls direction of RWD
    	      BSEL,			 // bank select
    	      REQ,			 // request, powers on CAS circuitry
    	      ADR,			 // row/column address
    	      RASB,			 // row address strobe, asserted low
    	      RSTR,			 // restore
    	      PON,			 // power on
    	      VREG,			 // voltage regulator reference
    	      WML,			 // write mask load
    	      WPBT,			 // write-per-bit
    	      MPBT,			 // mask-per-bit
    	      PDMD,			 // power down mode
    	      VCMNA,			 // test func: for VDD minimum test
	      VRST,			 // test func: Vinternal = Vexternal
	      ROLLC,			 // test func: roll call mode
	      SDST,			 // test func: subdetect stop
	      RCRED,			 // test func: roll call redundancy
	      HVST,			 // test func: half Vcc generator
	      BIMDI,			 // test func: burn in mode
	      AGEING,			 // test func: accelerate ageing pin
	      AGEGND);			 // test func: accelerate ageing pin
  
`else
module u5MemC( PON, VREG, RCRED, RDL0, RDL1, RDL2, RDL7, RDL4, RDL3, RDL5, RDL8, RDL6, 
BIMDI, WE, WML, REQ, WRITE, CAS, BSEL, ADR, RSTR, RASB, MPBT, WPBT, PDMD, HVST, AGEGND, 
AGEING, VRST, SDST, ROLLC, VCMNA, WDL3, WDL8, WDL5, WDL1, WDL6, WDL2, WDL4, WDL7, WDL0);
`endif
  
inout         WDL8;			 // write data
inout         WDL7;			 // write data
inout	      WDL6;			 // write data
inout	      WDL5;			 // write data
inout	      WDL4;			 // write data
inout	      WDL3;			 // write data
inout	      WDL2;			 // write data
inout	      WDL1;			 // write data
inout	      WDL0;			 // write data
inout         RDL8;			 // read data
inout         RDL7;			 // read data
inout	      RDL6;			 // read data
inout	      RDL5;			 // read data
inout	      RDL4;			 // read data
inout	      RDL3;			 // read data
inout	      RDL2;			 // read data
inout	      RDL1;			 // read data
inout	      RDL0;			 // read data
inout         WE;			 // write enable
inout         CAS;			 // column address strobe
inout         WRITE;			 // write, controls direction of RWD
inout         BSEL;			 // bank select
inout         REQ;			 // request, powers on CAS circuitry
inout         ADR;			 // row/column address
inout         RASB;			 // row address strobe, asserted low
inout         RSTR;			 // restore
inout         PON;			 // power on
inout         VREG;			 // voltage regulator reference
inout         WML;			 // write mask load
inout         WPBT;			 // write-per-bit
inout         MPBT;			 // mask-per-bit
inout         PDMD;			 // power down mode
inout         VCMNA;			 // test func: for VDD minimum test
inout         VRST;			 // test func: Vinternal = Vexternal
inout         ROLLC;			 // test func: roll call mode
inout         SDST;			 // test func: subdetect stop
inout         RCRED;			 // test func: roll call redundancy
inout         HVST;			 // test func: half Vcc generator
inout         BIMDI;			 // test func: burn in mode
inout         AGEING;			 // test func: accelerate ageing pin
inout         AGEGND;			 // test func: accelerate ageing pin

wire [7:0]    WDL8;			 // write data
wire [7:0]    WDL7;			 // write data
wire [7:0]    WDL6;			 // write data
wire [7:0]    WDL5;			 // write data
wire [7:0]    WDL4;			 // write data
wire [7:0]    WDL3;			 // write data
wire [7:0]    WDL2;			 // write data
wire [7:0]    WDL1;			 // write data
wire [7:0]    WDL0;			 // write data
wire [7:0]    RDL8;			 // read data
wire [7:0]    RDL7;			 // read data
wire [7:0]    RDL6;			 // read data
wire [7:0]    RDL5;			 // read data
wire [7:0]    RDL4;			 // read data
wire [7:0]    RDL3;			 // read data
wire [7:0]    RDL2;			 // read data
wire [7:0]    RDL1;			 // read data
wire [7:0]    RDL0;			 // read data
wire [7:0]    WE;			 // write enable
wire          CAS;			 // column address strobe
wire          WRITE;			 // write, controls direction of RWD
wire          BSEL;			 // bank select
wire          REQ;			 // request, powers on CAS circuitry
wire [8:0]    ADR;			 // row/column address
wire          RASB;			 // row address strobe, asserted low
wire          RSTR;			 // restore
wire          PON;			 // power on
wire          VREG;			 // voltage regulator reference
wire          WML;			 // write mask load
wire          WPBT;			 // write-per-bit
wire          MPBT;			 // mask-per-bit
wire          PDMD;			 // power down mode
wire          VCMNA;			 // test func: for VDD minimum test
wire          VRST;			 // test func: Vinternal = Vexternal
wire          ROLLC;			 // test func: roll call mode
wire          SDST;			 // test func: subdetect stop
wire          RCRED;			 // test func: roll call redundancy
wire          HVST;			 // test func: half Vcc generator
wire          BIMDI;			 // test func: burn in mode
wire          AGEING;			 // test func: accelerate ageing pin
wire          AGEGND;			 // test func: accelerate ageing pin

// declarations for semaphores used by timing checks
reg noisy_sense_if_defined;

// size parameters
parameter byte = 9;			 // number of bits per byte
parameter oct = 8;			 // column access done in groups of 8
parameter col_addr_bits = 8;		 // number of column address bits
parameter num_columns = 1<<col_addr_bits; // number of columns
parameter row_addr_bits = 9;		 // number of row address bits
parameter num_rows = 1<<row_addr_bits;	 // number of rows
parameter block_addr_bits = 1;		 // number of block address bits
parameter num_blocks = 1<<block_addr_bits; // number of banks

// short form to read all the WDL lines
wire [((oct*byte)-1):0] WDL = {WDL8, WDL7, WDL6, WDL5, WDL4,
			       WDL3, WDL2, WDL1, WDL0};

// timing parameters *** NB, must correspond to specify block ***
parameter ns = 10;			 // verilog ticks per nanosecond
parameter us = 10000;			 // verilog ticks per microsecond
parameter ctl_min_delta = -3;		 // time spec adjustment, verilog ticks
parameter ctl_max_delta = +3;		 // time spec adjustment, verilog ticks
parameter out_min_delta = +3;		 // time spec adjustment, verilog ticks
parameter out_max_delta = -3;		 // time spec adjustment, verilog ticks

// timing parameters for specify block
specify
  specparam ns_sp = 10;
  specparam us_sp = 10000;
  specparam ctl_min_delta_sp = -3;
  specparam ctl_max_delta_sp = +3;
  specparam out_min_delta_sp = +3;
  specparam out_max_delta_sp = -3;
endspecify

// timing parameters - column *** NB, must correspond to specify block ***
					 // not interface spec, but operative
parameter tASC =  ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tASC_sp =  (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tBH =   ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tBH_sp =   (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

					 // not interface spec, but operative
parameter tBS =   ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tBS_sp =   (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCAH =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tCAH_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCAS =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tCAS_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tCMD =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tCMD_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCMS =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tCMS_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tCP =   ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tCP_sp =   (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tCSA =   ((ctl_max_delta + 2*ns) > 0) ? ctl_max_delta + 2*ns : 0;
specify
  specparam tCSA_sp =  (((ctl_max_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_max_delta_sp + 2*ns_sp : 0);
endspecify

parameter tDAC =  ((out_max_delta + 12*ns) > 0) ? out_max_delta + 12*ns : 0;
specify
  specparam tDAC_sp =  (((out_max_delta_sp + 12*ns_sp) > 0) ?
      	      	      	  out_max_delta_sp + 12*ns_sp : 0);
endspecify

parameter tDH =   ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tDH_sp =   (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tDOH =  ((out_min_delta + 4*ns) > 0) ? out_min_delta + 4*ns : 0;
specify
  specparam tDOH_sp =  (((out_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  out_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tDOHW = ((out_min_delta + 0*ns) > 0) ? out_min_delta + 0*ns : 0;
specify
  specparam tDOHW_sp = (((out_min_delta_sp + 0*ns_sp) > 0) ?
      	      	      	  out_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tDS =   ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tDS_sp =   (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tMDH =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tMDH_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tMDS =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tMDS_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tMPH =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tMPH_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tMPS =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tMPS_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tPC =   ((ctl_min_delta + 16*ns) > 0) ? ctl_min_delta + 16*ns : 0;
specify
  specparam tPC_sp =   (((ctl_min_delta_sp + 16*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 16*ns_sp : 0);
endspecify

parameter tRCD =  ((ctl_min_delta + 48*ns) > 0) ? ctl_min_delta + 48*ns : 0;
specify
  specparam tRCD_sp =  (((ctl_min_delta_sp + 48*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 48*ns_sp : 0);
endspecify

parameter tRQH =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tRQH_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

`ifdef RQL8
  parameter tRQL =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
  specify
    specparam tRQL_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
			    ctl_min_delta_sp + 8*ns_sp : 0);
  endspecify
`else
  `define RQL4
  `ifdef RQL4
    parameter tRQL =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
    specify
      specparam tRQL_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
			      ctl_min_delta_sp + 4*ns_sp : 0);
    endspecify
  `else
    initial
      begin
        $display("%m ERROR: Must define \"RQL4\" or \"RQL8\" for tRQLmin");
	while (1) $stop;
      end
    parameter tRQL = 1000;
    specify
      specparam  tRQL_sp = 1000;
    endspecify
  `endif
`endif

parameter tRQS =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRQS_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRSA =   ((ctl_max_delta + 2*ns) > 0) ? ctl_max_delta + 2*ns : 0;
specify
  specparam tRSA_sp =  (((ctl_max_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_max_delta_sp + 2*ns_sp : 0);
endspecify

parameter tRSB =   ((ctl_max_delta + 2*ns) > 0) ? ctl_max_delta + 2*ns : 0;
specify
  specparam tRSB_sp =  (((ctl_max_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_max_delta_sp + 2*ns_sp : 0);
endspecify

parameter tWEH =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tWEH_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tWES =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tWES_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tWH =   ((ctl_min_delta + 2*ns) > 0) ? ctl_min_delta + 2*ns : 0;
specify
  specparam tWH_sp =   (((ctl_min_delta_sp + 2*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 2*ns_sp : 0);
endspecify

parameter tWML =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tWML_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tWPH =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tWPH_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tWPS =  ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tWPS_sp =  (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tWS =   ((ctl_min_delta + 10*ns) > 0) ? ctl_min_delta + 10*ns : 0;
specify
  specparam tWS_sp =   (((ctl_min_delta_sp + 10*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 10*ns_sp : 0);

endspecify

// column timing checks
specify
  $setup(ADR, posedge CAS, tASC_sp);
  $hold(negedge CAS, BSEL, tBH_sp); 
  $setup(BSEL, posedge CAS, tBS_sp);
  $hold(posedge CAS, ADR, tCAH_sp);
  $width(posedge CAS, tCAS_sp);
  $hold(negedge CAS, WML, tCMD_sp);
  $setup(WML, posedge CAS, tCMS_sp);
  $width(negedge CAS, tCP_sp);
  // no check required for response spec tDAC
  $hold(negedge CAS &&& (WRITE == 1), WDL, tDH_sp);
  // no check required for response spec tDOH
  // no check required for response spec tDOHW
  $setup(WDL, posedge CAS &&& (WRITE == 1), tDS_sp);
  $hold(negedge WML, WDL, tMDH_sp);
  $setup(WDL, posedge WML, tMDS_sp);
  $hold(negedge CAS, MPBT, tMPH_sp);
  $setup(MPBT, posedge CAS, tMPS_sp);
  $period(posedge CAS, tPC_sp);
  $setup(RASB, posedge CAS, tRCD_sp);
  $hold(negedge CAS, REQ, tRQH_sp);
  $width(negedge REQ, tRQL_sp);
  $setup(REQ, negedge CAS, tRQS_sp);
  $hold(posedge CAS &&& WRITE, WE, tWEH_sp);
  $setup(WE, posedge CAS &&& WRITE, tWES_sp);
  $hold(negedge CAS, WRITE, tWH_sp);
  $width(posedge WML, tWML_sp);
  $hold(negedge CAS, WPBT, tWPH_sp);
  $setup(WPBT, posedge CAS, tWPS_sp);
  $setup(WRITE, posedge CAS, tWS_sp);
endspecify

// timing parameters - row
parameter tASR1 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tASR1_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tASR2 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tASR2_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tBSR1 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tBSR1_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tBSR2 = ((ctl_min_delta + 4*ns) > 0) ? ctl_min_delta + 4*ns : 0;
specify
  specparam tBSR2_sp = (((ctl_min_delta_sp + 4*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 4*ns_sp : 0);
endspecify

parameter tCFR =  ((ctl_min_delta + 24*ns) > 0) ? ctl_min_delta + 24*ns : 0;
specify
  specparam tCFR_sp =  (((ctl_min_delta_sp + 24*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 24*ns_sp : 0);
endspecify

parameter tPDH =  ((ctl_min_delta + 32*ns) > 0) ? ctl_min_delta + 32*ns : 0;
specify
  specparam tPDH_sp =  (((ctl_min_delta_sp + 32*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 32*ns_sp : 0);
endspecify

parameter tPDS =  ((ctl_min_delta + 64*ns) > 0) ? ctl_min_delta + 64*ns : 0;
specify
  specparam tPDS_sp =  (((ctl_min_delta_sp + 64*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 64*ns_sp : 0);
endspecify

parameter tPRAS = ((ctl_min_delta + 200*ns) > 0) ? ctl_min_delta + 200*ns : 0;
specify
  specparam tPRAS_sp = (((ctl_min_delta_sp + 200*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 200*ns_sp : 0);
endspecify

parameter tPRC =  ((ctl_min_delta + 400*ns) > 0) ? ctl_min_delta + 400*ns : 0;
specify
  specparam tPRC_sp =  (((ctl_min_delta_sp + 400*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 400*ns_sp : 0);
endspecify

parameter tPRP =  ((ctl_min_delta + 200*ns) > 0) ? ctl_min_delta + 200*ns : 0;
specify
  specparam tPRP_sp =  (((ctl_min_delta_sp + 200*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 200*ns_sp : 0);
endspecify

parameter tPVD =  ((out_max_delta + 15*us) > 0) ? ctl_min_delta + 15*us : 0;
specify
  specparam tPVD_sp =  (((out_max_delta_sp + 15000*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 15000*ns_sp : 0);
endspecify

parameter tPVH =  ((out_max_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tPVH_sp =  (((out_max_delta_sp + 0*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tRAH1 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRAH1_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRAH2 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRAH2_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRAS =  ((ctl_min_delta + 112*ns) > 0) ? ctl_min_delta + 112*ns : 0;
specify
  specparam tRAS_sp =  (((ctl_min_delta_sp + 112*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 112*ns_sp : 0);
endspecify

parameter tRBH1 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRBH1_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRBH2 = ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRBH2_sp = (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRC =   ((ctl_min_delta + 140*ns) > 0) ? ctl_min_delta + 140*ns : 0;
specify
  specparam tRC_sp =   (((ctl_min_delta_sp + 140*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 140*ns_sp : 0);
endspecify

parameter tRP =   ((ctl_min_delta + 28*ns) > 0) ? ctl_min_delta + 28*ns : 0;
specify
  specparam tRP_sp =   (((ctl_min_delta_sp + 28*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 28*ns_sp : 0);
endspecify

parameter tRPR =  ((ctl_min_delta + 28*ns) > 0) ? ctl_min_delta + 28*ns : 0;
specify
  specparam tRPR_sp =  (((ctl_min_delta_sp + 28*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 28*ns_sp : 0);
endspecify

parameter tRRD =  ((ctl_min_delta + 92*ns) > 0) ? ctl_min_delta + 92*ns : 0;
specify
  specparam tRRD_sp =  (((ctl_min_delta_sp + 92*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 92*ns_sp : 0);
endspecify

parameter tRSH =  ((ctl_min_delta + 16*ns) > 0) ? ctl_min_delta + 16*ns : 0;
specify
  specparam tRSH_sp =  (((ctl_min_delta_sp + 16*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 16*ns_sp : 0);
endspecify

parameter tRSR =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRSR_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tRTH =  ((ctl_min_delta + 26*ns) > 0) ? ctl_min_delta + 26*ns : 0;
specify
  specparam tRTH_sp =  (((ctl_min_delta_sp + 26*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 26*ns_sp : 0);
endspecify

parameter tRTL =  ((ctl_min_delta + 20*ns) > 0) ? ctl_min_delta + 20*ns : 0;
specify
  specparam tRTL_sp =  (((ctl_min_delta_sp + 20*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 20*ns_sp : 0);
endspecify

parameter tRTO =  ((ctl_min_delta + 26*ns) > 0) ? ctl_min_delta + 26*ns : 0;
specify
  specparam tRTO_sp =  (((ctl_min_delta_sp + 26*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 26*ns_sp : 0);
endspecify

parameter tRTR =  ((ctl_min_delta + 6*ns) > 0) ? ctl_min_delta + 6*ns : 0;
specify
  specparam tRTR_sp =  (((ctl_min_delta_sp + 6*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 6*ns_sp : 0);
endspecify

parameter tRTS =  ((ctl_min_delta + 8*ns) > 0) ? ctl_min_delta + 8*ns : 0;
specify
  specparam tRTS_sp =  (((ctl_min_delta_sp + 8*ns_sp) > 0) ?
      	      	      	  ctl_min_delta_sp + 8*ns_sp : 0);
endspecify

parameter tQHP =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tQHP_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 0*ns_sp : 0);
endspecify

parameter tQSP =  ((ctl_min_delta + 0*ns) > 0) ? ctl_min_delta + 0*ns : 0;
specify
  specparam tQSP_sp =  (((ctl_min_delta_sp + 0*ns_sp) > 0) ? 
                          ctl_min_delta_sp + 0*ns_sp : 0);
endspecify


// row timing checks
specify
  $setup(ADR, negedge RASB, tASR1_sp);
  $setup(ADR, posedge RSTR &&& (RASB == 0), tASR2_sp);
  $setup(BSEL, posedge RASB &&& (RSTR == 0), tBSR1_sp);
  $setup(BSEL, posedge RSTR &&& (RASB == 0), tBSR2_sp);
  $hold(negedge CAS &&& (RSTR == 0), posedge RSTR, tCFR_sp);
  $hold(posedge RASB, PDMD,  tPDH_sp, noisy_sense_if_defined);
  $setup(PDMD, negedge RASB, tPDS_sp, noisy_sense_if_defined);
  $width(negedge RASB &&& (PDMD == 1), tPRAS_sp);
  $period(posedge RASB &&& (PDMD == 1), tPRC_sp);
  $width(posedge RASB &&& (PDMD == 1), tPRP_sp);
  // no check required for response spec  tPVD
  // no check required for response spec  tPVH
  $hold(negedge RASB, ADR, tRAH1_sp);
  $hold(posedge RSTR &&& (RASB == 0), ADR, tRAH2_sp);
  $width(negedge RASB, tRAS_sp);
  $hold(posedge RASB &&& (RSTR == 0), BSEL, tRBH1_sp);
  $hold(posedge RSTR &&& (RASB == 0), BSEL, tRBH2_sp);
  $period(posedge RASB, tRC_sp);
  $width(posedge RASB, tRP_sp);
  $width(posedge RASB &&& (RSTR == 1), tRPR_sp);
  $hold(negedge RASB, RSTR, tRRD_sp);
  $hold(negedge CAS, RASB, tRSH_sp);
  $hold(posedge RASB, RSTR, tRSR_sp);
  $width(posedge RSTR, tRTH_sp);
  $width(negedge RSTR &&& (~RASB), tRTL_sp);
  $hold(posedge RSTR &&& (RASB == 0), RASB, tRTO_sp);
  $hold(negedge RSTR, RASB, tRTR_sp);
  $hold(posedge RSTR &&& (RASB == 1), RASB, tRTS_sp);
  $setup(REQ, posedge PDMD, tQHP_sp);
  $hold (negedge PDMD, REQ, tQSP_sp);
endspecify


// timing parameters - other
parameter tPON = ctl_min_delta + 80*ns;

//////////////////////////////////////////////////////////////////////////////

// memory array
reg [(oct*byte-1):0] core [0:((num_blocks*num_rows*num_columns)-1)];

// cache lines, formed by the sense amplifiers
reg [(oct*byte-1):0] cache [0:((num_blocks*(num_columns))-1)];

// latch for write-per-bit and mask-per-bit
wire [((oct*byte)-1):0] write_mask;

// logic 0
supply0 Gnd;

// logic 1
supply1 Vdd;

//////////////////////////////////////////////////////////////////////////////

// CAS read
wire [((oct*byte)-1):0] rdl_drive;	 // derivative signal
wire [((oct*byte)-1):0] sa_read;
wire [(col_addr_bits-1):0] cr_col_addr;
wire read_prech;
reg  cr_rdcy_control;
wire [(col_addr_bits):0] cr_rdcy_BSEL_ADR;
wire [(col_addr_bits):0] cr_rdcy_select;
wire [(col_addr_bits):0] cr_rdcy_latched;
wire cr_rdcy_prech;
wire cr_rdcy_prech0;
reg  cr1REQ;
reg  cr_latch_addr;
reg  crCAS;				 // signals with timing uncertainties
wire crWRITE;
wire crREQ;
wire crBSEL;
reg  cr_control;
wire cr_control0;
wire cr_control1;
wire [((oct*byte)-1):0] cr_cache;
wire read_prech0;
reg  [(col_addr_bits-1):0] crADR;
wire [(col_addr_bits-1):0] cr0ADR;

`ifdef DEBUGCORE
  always @rdl_drive
    begin
      $display("%0d %m: update RDL: crBSEL=%b, cr_col_addr=%b", 
               $stime, crBSEL, cr_col_addr);
      $display("  %b", rdl_drive);
    end
`endif
      
`ifdef INFOCORE
  always @(posedge cr_control)
    if (cr_control === 1)
      $display("%0d %m: CAS Read of block=%h address=%h", 
               $stime, crBSEL, cr_col_addr);
`endif

always @(posedge cr_control)
  if ({crBSEL, cr_col_addr} !== cr_rdcy_latched)
    $display("%0d %m: WARNING, Timing violation of tRSA, tRSB, or tCSA.", 
             $stime);

assign #tDOHW rdl_drive = 
      	     WRITE ? {oct*byte{1'bz}}
	           : {RDL8, RDL7, RDL6, RDL5, RDL4, RDL3, RDL2, RDL1, RDL0};

assign {RDL8, RDL7, RDL6, RDL5, RDL4, RDL3, RDL2, RDL1, RDL0} =
           cr_control ? crREQ ? ({crBSEL, cr_col_addr} === cr_rdcy_latched) ?
	                         cr_cache : {oct*byte{1'bx}}
                              : {oct*byte{1'bx}}
                      : rdl_drive;

					 // cas read control
always @(cr_control1 or cr_control0) cr_control = cr_control1 & cr_control0;
assign #0    cr_control1 = cr_control0;        // with uncertain high period
assign #tCAS cr_control1 = cr_control0;
assign cr_control0 = (crCAS & ~crWRITE & ((read_prech === 1) ? 1 : 'bx));

					 // cas read data
assign #0    cr_cache = cache[{crBSEL, cr_col_addr}];
assign #tCAS cr_cache = cache[{crBSEL, cr_col_addr}];

assign cr_col_addr = cr_latch_addr ? cr_col_addr : crADR; // address latch

assign cr_rdcy_latched = crCAS ? cr_rdcy_latched : cr_rdcy_select;

assign read_prech = crCAS ? read_prech	 // precharge equalizes diff amp
                          : read_prech0;
assign #0   read_prech0 = crWRITE | ~crCAS;
assign #tCP read_prech0 = crWRITE | ~crCAS;


  //effective end of cas read
  //parameter end_cr = max(tRQH, tWH, tBH);
parameter end_cr1 = (tWH  > tBH)     ? tWH  : tBH;
parameter end_cr  = (tRQH > end_cr1) ? tRQH : end_cr1;

always @CAS  crCAS <= #end_cr CAS;	 // align reference pulse

initial check_equal(end_cr - ctl_min_delta, tDAC - tCAS,
                    "max(tRQH, tWH, tBH)", "tDAC-tCAS");

assign #(end_cr - tRQH) crREQ = REQ;	 // early
assign #(end_cr + tRQS) crREQ = REQ;	 // late

assign #(end_cr - tWH)  crWRITE = WRITE; // early
assign #(end_cr + tWS)  crWRITE = WRITE; // late

assign #(end_cr - tBH)  crBSEL = BSEL;	 // early
assign #(end_cr + tBS)  crBSEL = BSEL;	 // late

always @cr0ADR  crADR <= #((end_cr > tCAH) ? end_cr - tCAH : 0) cr0ADR; // align
assign #0             cr0ADR = ADR;	           // early
assign #(tCAH + tASC) cr0ADR = ADR;	           // late

always @CAS cr_latch_addr <= #((tCAH > end_cr) ? tCAH : end_cr) CAS;

					 // redundancy control
always @(REQ or CAS)    cr_rdcy_control <= #(end_cr + tCSA) REQ & ~CAS;
assign #end_cr          cr_rdcy_BSEL_ADR = {BSEL, ADR[(col_addr_bits-1):0]};
assign cr_rdcy_select = cr_rdcy_control ? cr_rdcy_select : cr_rdcy_BSEL_ADR;
assign cr_rdcy_select = cr_rdcy_prech ? cr_rdcy_BSEL_ADR : 'bx;

assign cr_rdcy_prech = (cr1REQ & ~crCAS) ? cr_rdcy_prech : cr_rdcy_prech0;
assign #0    cr_rdcy_prech0 = ~cr1REQ | crCAS;
assign #tRQL cr_rdcy_prech0 = ~cr1REQ | crCAS;

always @REQ  cr1REQ <= #end_cr REQ;

initial check_ge(tCAS, tRQL, "tCAS", "tRQL");
initial check_equal(tCSA, tRSA, "tCSA", "tRSA");
initial check_equal(tCSA, tRSB, "tCSA", "tRSB");

// CAS write, including WPBT and MPBT
wire [((oct*byte)-1):0] sa_drive;	 // derivative signals
wire [((oct*byte)-1):0] sa_data;
wire [((oct*byte)-1):0] sa_enable;
wire [((oct*byte)-1):0] bit_enable;
wire [(oct-1):0] byte_enable;
wire [(col_addr_bits-1):0] cw_col_addr;
wire [((oct*byte)-1):0] wm_drive;
reg  cw_rdcy_control;
wire [(col_addr_bits):0] cw_rdcy_BSEL_ADR;
wire [(col_addr_bits):0] cw_rdcy_select;
wire [(col_addr_bits):0] cw_rdcy_latched;
wire [(col_addr_bits):0] cw_eff_addr;
wire cw_rdcy_prech;
wire cw_rdcy_prech0;
reg  cw1REQ;
reg  cwCAS;				 // signals with timing uncertainties
reg  cw_control;
wire cw_control0;
wire cw0CAS;
wire cwREQ;
wire cwWRITE;
wire [((oct*byte)-1):0] cwWDL;
wire cwBSEL;
wire cwWPBT;
wire cwMPBT;
reg  [(oct-1):0] cwWE;
wire [(oct-1):0]cw0WE;
reg  wmWML;
wire [((oct*byte)-1):0] wmWDL;
reg  [(col_addr_bits-1):0] cwADR;
wire [(col_addr_bits-1):0] cw0ADR;
reg [(col_addr_bits):0] i_col;	 // index for column addresses + 1 bit

					 // update addressed portion of cache
always @(sa_drive or cw_eff_addr or sa_enable or posedge cwCAS)
  if (|sa_enable & cwCAS)
    begin
      if (check_x_bits(cw_eff_addr))
      	begin
      	  for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	    cache[i_col] = {oct*byte{1'bx}};
	  $display("%0d %m: WARNING All cache <- X (workaround Verilog bug)",
	           $stime);
	end
      else
        cache[cw_eff_addr] = sa_drive;
      if ({cwBSEL, cw_col_addr} !== cw_rdcy_latched)
        $display("%0d %m: WARNING Timing violation of tRSA, tRSB, tCSA: Write",
                 $stime);
      `ifdef INFOCORE
      	if (cw_control === 1)
	  $display("%0d %m: CAS Write of block=%h address=%h, byte_enable=%h",
                   $stime, cwBSEL, cw_col_addr, byte_enable);
      `endif
      `ifdef DEBUGCORE
        $display("%0d %m: updated cache: cwBSEL=%b, cw_col_addr=%b", 
                 $stime, cwBSEL, cw_col_addr);
        $display("  %b", sa_drive);
      `endif
    end

					 // cas write control
always @(cw_control0 or cwCAS) cw_control = cw_control0 & cwCAS;
assign #0    cw_control0 = cwCAS;	 // with uncertain high period
assign #tCAS cw_control0 = cwCAS;

assign sa_drive = (cw_control & ((cwREQ === 1) ? 1 : 'bx))
                                ? (sa_enable & sa_data)
                                  | (~sa_enable & cache[cw_eff_addr])
				  | ((sa_data ~^ cache[cw_eff_addr])
				     & sa_data & cache[cw_eff_addr])
			        : cache[cw_eff_addr];

assign sa_data =   sa_enable & (cwMPBT ? write_mask : cwWDL);

assign sa_enable =   bit_enable & {byte{byte_enable}};

assign byte_enable = cwCAS ? {oct{cwWRITE}} & byte_enable
                           : {oct{cwWRITE}} & cwWE;

assign bit_enable = cwWPBT ? (cwMPBT ? cwWDL 
				     : write_mask)
                           : {oct*byte{1'b1}};
			   
assign cw_eff_addr = ({cwBSEL, cw_col_addr} === cw_rdcy_latched)
                     ? {cwBSEL, cw_col_addr}
		     : 'bx;

assign cw_col_addr = cwCAS ? cw_col_addr : cwADR;

assign cw_rdcy_latched = cwCAS ? cw_rdcy_latched : cw_rdcy_select;

  //effective end of cas write
  //parameter end_cw = max(tRQH, tWH, tDH, tBH, tWPH, tMPH, tCMD, tWEH, tCAH);
parameter end_cw7 = (tWEH > tCAH)    ? tWEH : tCAH;
parameter end_cw6 = (tCMD > end_cw7) ? tCMD : end_cw7;
parameter end_cw5 = (tMPH > end_cw6) ? tMPH : end_cw6;
parameter end_cw4 = (tWPH > end_cw5) ? tWPH : end_cw5;
parameter end_cw3 = (tBH  > end_cw4) ? tBH  : end_cw4;
parameter end_cw2 = (tDH  > end_cw3) ? tDH  : end_cw3;
parameter end_cw1 = (tWH  > end_cw2) ? tWH  : end_cw2;
parameter end_cw  = (tRQH > end_cw1) ? tRQH : end_cw1;

always @CAS  cwCAS <= #end_cw CAS;	 // align reference pulse

assign #(end_cw - tRQH) cwREQ = REQ;	 // early
assign #(end_cw + tRQS) cwREQ = REQ;	 // late

assign #(end_cw - tWH)  cwWRITE = WRITE; // early
assign #(end_cw + tWS)  cwWRITE = WRITE; // late

assign #(end_cw - tDH)  cwWDL = WDL;	 // early
assign #(end_cw + tDS)  cwWDL = WDL;	 // late

assign #(end_cw - tBH)  cwBSEL = BSEL;	 // early
assign #(end_cw + tBS)  cwBSEL = BSEL;	 // late

assign #(end_cw - tWPH) cwWPBT = WPBT;	 // early
assign #(end_cw + tWPS) cwWPBT = WPBT;	 // late

assign #(end_cw - tMPH) cwMPBT = MPBT;	 // early
assign #(end_cw + tMPS) cwMPBT = MPBT;	 // late

always @cw0WE   cwWE <= #(end_cw - tWEH) cw0WE;	 // align
assign #0             cw0WE = WE;		 // early
assign #(tWEH + tWES) cw0WE = WE;		 // late

always @cw0ADR  cwADR <= #(end_cw - tCAH) cw0ADR;// align
assign #0             cw0ADR = ADR;	         // early
assign #(tCAH + tASC) cw0ADR = ADR;              // late

					 // redundancy control
always @(REQ or CAS)    cw_rdcy_control <= #(end_cw + tCSA) REQ & ~CAS;
assign #end_cw          cw_rdcy_BSEL_ADR = {BSEL, ADR[(col_addr_bits-1):0]};
assign cw_rdcy_select = cw_rdcy_control ? cw_rdcy_select : cw_rdcy_BSEL_ADR;
assign cw_rdcy_select = cw_rdcy_prech ? cw_rdcy_BSEL_ADR : 'bx;

assign cw_rdcy_prech = (cw1REQ & ~cwCAS) ? cw_rdcy_prech : cw_rdcy_prech0;
assign #0    cw_rdcy_prech0 = ~cw1REQ | cwCAS;
assign #tRQL cw_rdcy_prech0 = ~cw1REQ | cwCAS;

always @REQ  cw1REQ <= #end_cw REQ;


// latching the write mask

assign #0    write_mask = wm_drive;	 // mark time to properly latch
assign #tWML write_mask = wm_drive;

assign wm_drive = wmWML ? wmWDL : write_mask;	// latch action

  //effective end of write mask
  //parameter end_wm = max(tCMS, tMDH, 0, 0, 0, 0, 0, 0, 0);
parameter end_wm = (tCMS > tMDH) ? tCMS : tMDH;

always @WML  wmWML <= #end_wm WML;	 // align reference pulse

assign #(end_wm - tMDH) wmWDL = WDL;	 // early
assign #(end_wm + tMDS) wmWDL = WDL;	 // late

initial check_equal(tWML, tCMS, "tWML", "tCMS");


//////////////////////////////////////////////////////////////////////////////

// row read
reg [(oct*byte-1):0] core_row_temp [0:(num_columns-1)]; // scratch reg for core
reg [(block_addr_bits):0] i_blk;	 // index for block addresses + 1 bit
wire ras_prech;				 // latch bit for row precharged
wire RSTR1;				 // internal RSTR, from pin unless PDMD
reg  rrRASB;				 // delayed reference pulses
reg  rrRSTR1;
reg  [(row_addr_bits-1):0] rr_row_addr;	 // address for row read
reg  rr_block;				 // block for row read
wire rr_control;			 // signals with timing uncertainty
wire rr_control0;
wire rr_control1;
wire rr_control2;
wire [(row_addr_bits-1):0] rrw_row_addr; // address for row read and write
wire rrw_block;				 // block for row read and write
wire [(row_addr_bits-1):0] rrwADR;	 // address timing uncertainty
wire rrwBSEL;				 // block timing uncertainty
reg  rrwRASB;				 // address/block ref signals
reg  rrwRSTR1;
wire rrw_ras_rstr;			 // derived signal for address/block
reg  [(row_addr_bits+1):0] debug_ras;	 // debug: flag, block and addr at read

// add this after debug_ras in u5MemC

wire [71:0] harlan;
// monitor bank 1 row 1b6 column 0 in core
assign harlan = core[{1'b1,9'b110110110,8'b0}];
wire [71:0] harlan2;
// monitors bank 1 column 0 in cacheline
assign harlan2 = cache[{1'b1,8'b0}];

always @(posedge rr_control)
  begin
    if (rr_control === 1'bx)
      begin
	for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	  begin
	    core_row_temp[i_col] = 
	             core[{rr_block, rr_row_addr, i_col[(col_addr_bits-1):0]}];
	    core[{rr_block, rr_row_addr, i_col[(col_addr_bits-1):0]}] = 
	             {oct*byte{1'bx}};
	    cache[{rr_block, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
	  end
	debug_ras = {1'bx, rr_block, rr_row_addr};
	`ifdef DEBUGCORE
	  $display("%0d %m:  start  read core block=%b, addr=%b",
		   $stime, rr_block, rr_row_addr);
	`endif
      end
    else
      begin
	if (noisy_sense_if_defined === 1'bx)
	  begin
	    for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	      cache[{rr_block, i_col[(col_addr_bits-1):0]}] <= 
	                                          #end_cr core_row_temp[i_col];
	    debug_ras <= #end_cr {1'b0, rr_block, rr_row_addr};
	    `ifdef DEBUGCORE
	      $display("%0d %m: finish read core block=%b, addr=%b",
		       $stime, rr_block, rr_row_addr);
	    `endif
            `ifdef INFOCORE
              $display("%0d %m: RAS Read of block=%h address=%h", 
		       $stime, rr_block, rr_row_addr);
            `endif
	  end
	else
	  begin
	    noisy_sense_if_defined = 'bx;
	    `ifdef DEBUGCORE
	      $display("%0d %m: finish read core block=%b, addr=%b: noise->X",
		       $stime, rr_block, rr_row_addr);
	    `endif
	  end
      end
  end

always @(posedge ras_prech)		 // precharging wipes the sense amps
  begin
    for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
      cache[{rr_block, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
    `ifdef DEBUGCORE
      $display("%0d %m:  precharge clearing cache, block=%b", 
               $stime, rr_block);
    `endif
  end


					 //effective end of row read
					 //parameter end_rr = max(tRAH1,tRBH1);
parameter end_rr  = (tRAH1 > tRBH1) ? tRAH1 : tRBH1;

					 // row read control
assign rr_control = rr_control2 & rr_control0;
assign #0    rr_control2 = rr_control0;  // with uncertain read period
assign #tRP  rr_control2 = rr_control0;
assign #(tRCD - end_rr - tRP) rr_control2 = rr_control1;
assign #tRP                   rr_control1 = rr_control0;
assign rr_control0 = (~rrRASB & ((ras_prech === 1) ? 1 : 'bx));

always @RASB rrRASB <= #end_rr RASB;	 // align reference pulses
always @RSTR1 rrRSTR1 <= #end_rr RSTR1;

always @rrw_row_addr rr_row_addr <= #(end_rr - tRAH1) rrw_row_addr; // rd addr

always @rrw_block    rr_block    <= #(end_rr - tRAH1) rrw_block; // read block

initial check_ge(end_rr, tRAH1, "end_rr", "tRAH1");

// row precharge
wire prechRASB;				 // signals with timing uncertainty
wire sa_isolate;

assign ras_prech = (rrRSTR1 & ~rrRASB)
                              ? ras_prech : prechRASB; // precharge sense amps
assign #0            prechRASB = rrRASB;	       // early effect
assign #tRP          prechRASB = sa_isolate & rrRASB;  // late effect
assign #(tRPR - tRP) sa_isolate = ~(rrRSTR1 & ~rrRASB); // add'l delay factor


// row restore
wire rw_rstr;				 // derivative restore signal
wire rstr_prech;			 // latch bit for restore recovery
reg  rwRSTR1;				 // delayed reference pulse
reg  [(row_addr_bits-1):0] rw_row_addr;	 // address for row read
reg  rw_block;				 // block for row read
wire rw_control;			 // signals with timing uncertainty
wire rw_control0;
wire rw_control1;
wire rw_control2;
reg  rwRASB;
wire rw0RASB;
reg  extendRASB;
reg  [(row_addr_bits+1):0] debug_rstr;	 // debug: flag, block and addr: write
integer i_core;				 // index for wiping out the core

always @(posedge rw_control)
  begin
    if (rw_control === 1'bx)
      begin
	for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	  core[{rw_block, rw_row_addr, i_col[(col_addr_bits-1):0]}] = 
	                                                      {oct*byte{1'bx}};
	debug_rstr = {1'bx, rw_block, rw_row_addr};
      	if (check_x_bits({rw_block, rw_row_addr}))
      	  begin
	    for (i_core = 0; i_core < (num_blocks*num_rows*num_columns);
	         i_core = i_core + 1)
	      core[i_core] = 72'bx; //{oct*byte{1'bx}};
	    $display("%0d %m: WARNING All core <- X (workaround Verilog bug)",
	             $stime);
	  end
	`ifdef DEBUGCORE
	  $display("%0d %m: start  write core block=%b, addr=%b",
		   $stime, rw_block, rw_row_addr);
	`endif
      end
    else
      begin
      	if (check_x_bits({rw_block, rw_row_addr}))
	  $display("%0d %m: WARNING Core left as X (workaround Verilog bug)",
	            $stime);
	else
	  begin
  	    for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
	      core[{rw_block, rw_row_addr, i_col[(col_addr_bits-1):0]}] = 
	                         cache[{rw_block, i_col[(col_addr_bits-1):0]}];
	    debug_rstr = {1'b0, rw_block, rw_row_addr};
	  end
	`ifdef DEBUGCORE
	  $display("%0d %m: finish write core block=%b, addr=%b",
		   $stime, rw_block, rw_row_addr);
	`endif
        `ifdef INFOCORE
          $display("%0d %m: RAS Write of block=%h address=%h", 
		   $stime, rw_block, rw_row_addr);
        `endif
      end
  end
      
					 // row write control
assign rw_control = rw_control2 & rw_control0;
assign #0    rw_control2 = rw_control0;  // with uncertain write period
assign #tRTL rw_control2 = rw_control0;
assign #(tRTO - tRTL) rw_control2 = rw_control1;
assign #tRTL          rw_control1 = rw_control0;
assign rw_control0 = (rw_rstr & ((rstr_prech === 1) ? 1 : 'bx));

					 //effective end of row write
					 //parameter end_rw = max(tRAH2,tRBH2);
parameter end_rw  = (tRAH2 > tRBH2) ? tRAH2 : tRBH2;
//parameter end_rw = tRTO;		 // effective end of row write

always @RSTR1 rwRSTR1 <= #end_rw RSTR1;	 // align reference pulse

always @rw0RASB rwRASB <= #end_rw rw0RASB;
assign #0       rw0RASB = RASB;
assign #tRSR    rw0RASB = RASB;

assign rw_rstr = rwRSTR1 & ~extendRASB;	 // combinational logic for restore

always @(posedge RASB) extendRASB <= #end_rw RASB;
always @(negedge RASB) extendRASB <= #(end_rw + tRRD - tRTO) RASB;

initial check_equal(tRTO, tRTH, "tRTO", "tRTH");

always @rrw_row_addr rw_row_addr <= #(end_rw - tRAH1) rrw_row_addr; // rd addr

always @rrw_block    rw_block    <= #(end_rw - tRAH1) rrw_block; // read block

initial check_ge(end_rw, tRAH1, "end_rw", "tRAH1");

// restore recovery
wire rstr_prech0;			 // signals with timing uncertainty
wire rstr_prech1;

assign rstr_prech = rstr_prech0 ? rstr_prech1 : rstr_prech;

assign #0    rstr_prech1 = rstr_prech0; // early effect
assign #tRTL rstr_prech1 = rstr_prech0; // late effect
assign rstr_prech0 = ~rwRSTR1 | extendRASB;


// row read and write address and block
assign rrw_row_addr = (rrwRSTR1 & ~rrwRASB)
                               ? rrw_row_addr : rrwADR; // row read addr latch

assign rrw_block    = (rrwRASB | rrwRSTR1 | rrw_ras_rstr) 
                               ? rrw_block : rrwBSEL; // row read block

always @RASB rrwRASB <= #tRAH1 RASB;	 // align reference signals
always @RSTR1 rrwRSTR1 <= #tRAH1 RSTR1;

assign #0               rrwADR = ADR;	 // early
assign #(tASR1 + tRAH1) rrwADR = ADR;	 // late

assign #0               rrwBSEL = BSEL;	 // early
assign #(tBSR1 + tRBH1) rrwBSEL = BSEL;	 // late

assign #(tRTR - tBSR1) rrw_ras_rstr = ~rrwRASB & rrwRSTR1; // delayed ctl pair

initial check_equal(tRAH1, tRAH2, "tRAH1", "tRAH2");
initial check_equal(tRAH1, tRBH1, "tRAH1", "tRBH1");
initial check_equal(tRAH1, tRBH2, "tRAH1", "tRBH2");
initial check_equal(tASR1, tASR2, "tASR1", "tASR2");
initial check_equal(tBSR1, tBSR2, "tBSR1", "tBSR2");


// power down mode
wire internal_rstr;			 // defines RSTR1 during PDMD
reg  stretchRASB;			 // time altered signals
reg  dly_stretchRASB;

					 // select external or internal restore
assign RSTR1 = PDMD ? internal_rstr : RSTR;

assign internal_rstr = stretchRASB | dly_stretchRASB;

always @(posedge RASB) stretchRASB <= #tRSR RASB;
always @(negedge RASB) stretchRASB <= #tRCD RASB;

always @(stretchRASB or PDMD) 
                       dly_stretchRASB <= #(tRRD - tRCD) stretchRASB | ~PDMD;

always @(posedge PDMD)			 // entering PDMD affects all caches
  begin
    for (i_blk = 0; i_blk < num_blocks; i_blk = i_blk +1)
      for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
        cache[{i_blk, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
    `ifdef DEBUGCORE
      $display("%0d %m:  entering powerdown, clearing all caches", $stime);
    `endif
  end

always @(negedge (rw_control & PDMD))	 // caches precharge after PDMD restore
  #0 begin
       for (i_blk = 0; i_blk < num_blocks; i_blk = i_blk +1)
         for (i_col = 0; i_col < num_columns; i_col = i_col + 1)
           cache[{i_blk, i_col[(col_addr_bits-1):0]}] = {oct*byte{1'bx}};
       `ifdef DEBUGCORE
         $display("%0d %m: end internal restore, clearing all caches", $stime);
       `endif
     end

// derivative parameter checks
initial check_ge(tCFR, end_cw, "tCFR", "internal:end_cw");
initial check_ge(tRSH, end_cw, "tRSH", "internal:end_cw");

//////////////////////////////////////////////////////////////////////////////

// power on
reg drvPON;
assign PON = drvPON;
initial
  fork
    #1        drvPON = Gnd;
    `ifdef XPONCORE
      #(tPON/2) drvPON = 1'bx;
    `endif
    #tPON     drvPON = Vdd;
  join

// voltage regulator reference
reg drvVREG;
assign VREG = drvVREG;
always @(posedge PON or negedge PDMD) drvVREG <= #tPVD PON & ~PDMD;
always @(negedge PON or posedge PDMD) drvVREG <= #tPVH 'bx;

// tie off test signals
assign BIMDI = Gnd;
assign RCRED = Gnd;


//////////////////////////////////////////////////////////////////////////////

// Functions

function [31:0] max;			 // returns maximum of parameter values
  input v0, v1, v2, v3, v4, v5, v6, v7, v8;
  integer v0, v1, v2, v3, v4, v5, v6, v7, v8;
  begin
    max = v0;
    if (v1 > max) max = v1;
    if (v2 > max) max = v2;
    if (v3 > max) max = v3;
    if (v4 > max) max = v4;
    if (v5 > max) max = v5;
    if (v6 > max) max = v6;
    if (v7 > max) max = v7;
    if (v8 > max) max = v8;
  end
endfunction


// Tasks

task check_equal;			 // checks for equal values, else stops
  input value1;
  input value2;
  input string1;
  input string2;
  integer value1;
  integer value2;
  reg [0:(32*8)-1] string1;
  reg [0:(132*8)-1] string2;
  begin
    if (value1 !== value2)
      begin
        $display("%0d %m ERROR: values not equal. %0s=%0d, %0s=%0d.",
                 $stime, string1, value1, string2, value2);
        #0 $stop;
      end
  end
endtask

task check_ge;			 // checks for ge values, else stops
  input value1;
  input value2;
  input string1;
  input string2;
  integer value1;
  integer value2;
  reg [0:(32*8)-1] string1;
  reg [0:(32*8)-1] string2;
  begin
    if (!(value1 >= value2))
      begin
        $display("%0d %m ERROR: values not >=. %0s=%0d, %0s=%0d.",
                 $stime, string1, value1, string2, value2);
        #0 $stop;
      end
  end
endtask

// check_x_bits - checks for any x bits
function [0:0] check_x_bits;
  input value;
  reg [31:0] value;
  begin
   check_x_bits = ((| (value & ~value)) === 1'bx) ? 1 : 0;
  end
endfunction

// not yet handled
// . init RASes
// . bit rot
// . effect of tRSH


endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latSA/latSA.v"
primitive latSA (Q, D, EN, S);
output Q; reg Q;
input  D,EN,S;

table
//	D  EN   S  :state:	output/next state
        ?   0   0  : ? :        - ; // no change
        ?   0   1  : ? :        1 ; // set output
        1   1   1  : ? :        1 ; // set output
        0   1   1  : ? :        x ; // x if conflict

        0   1   0  : ? :        0 ; // latch data
        1   1   0  : ? :        1 ; // latch data
        x   1   0  : ? :        x ; // latch data

        0   x   0  : 0 :        0 ; // reducing pessimism
        1   x   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latNBarA/latNBarA.v"
primitive latNBarA (Q, D_B, EN_B);
output Q; reg Q;
input  D_B,EN_B;

table
//	D_B  EN_B :state:	output/next state
        ?     1   : ? : - ; // no change

        0     0   : ? : 1 ; // latch data
        1     0   : ? : 0 ; // latch data
        x     0   : ? : x ; // latch data

        0     x   : 1 : 1 ; // reducing pessimism
        1     x   : 0 : 0 ; // reducing pessimism
        ?     n   : ? : - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latSB/latSB.v"
primitive latSB (Q, D, EN, S);
output Q; reg Q;
input  D,EN,S;

table
//	D  EN   S  :state:	output/next state
        ?   0   0  : ? :        - ; // no change
        ?   0   1  : ? :        1 ; // set output
        1   1   1  : ? :        1 ; // set output
        0   1   1  : ? :        x ; // x if conflict

        0   1   0  : ? :        0 ; // latch data
        1   1   0  : ? :        1 ; // latch data
        x   1   0  : ? :        x ; // latch data

        0   x   0  : 0 :        0 ; // reducing pessimism
        1   x   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffSync/ffSync.v"
primitive ffSync (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D_B:state: output/nextState
          n      1 : ? :   0;
          n      0 : ? :   1;
        // ignore positive edge of clock
          p      ? : ? :   -;
        // ignore data changes on steady clock
          ?      * : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ltxBarSB/ltxBarSB.v"
module ltxBarSB (Q, EN, D_B, S);
output Q;
input  D_B,EN,S;

  latBarSB #(1) latBarSB0 (Q, D_B, EN, S);

endmodule


// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ltxSB/ltxSB.v"
primitive ltxSB (Q, D, EN, S);
output Q; reg Q;
input  D,EN,S;

table
//      D  EN   S  :state:      output/next state
        ?   0   0  : ? :        - ; // no change
        ?   0   1  : ? :        1 ; // set output
        1   1   1  : ? :        1 ; // set output
        0   1   1  : ? :        x ; // x if conflict

        0   1   0  : ? :        0 ; // latch data
        1   1   0  : ? :        1 ; // latch data
        x   1   0  : ? :        x ; // latch data

        0   x   0  : 0 :        0 ; // reducing pessimism
        1   x   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffSB/ffSB.v"
primitive ffSB (Q, CLK, D, S);
    output Q; reg Q;
    input CLK;
    input D;
    input S;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D  S  :state: output/nextState
        n       0  0  : ? :   0;
        n       1  ?  : ? :   1;
        // ignore positive edge of clock
        p       ?  ?  : ? :   -;
        // ignore data changes on steady clock
        ?       *  ?  : ? :   -;
        // set output to 1
        ?       ?  1  : ? :   1;
        ?       ?  *  : 1 :   -;
 
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBarD/ffBarD.v"
primitive ffBarD (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes
//      neg logic output

//      CLKedge D :state: output/nextState
        n       0 : ? :   1;
        n       1 : ? :   0;
        // ignore positive edge of clock
        p       ? : ? :   -;
        // ignore data changes on steady clock
        ?       * : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latWA/latWA.v"
module latWA (A, Y);
    inout A;
    output Y;

  not #1(Y, A);
  not (weak1, weak0) (A, Y);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latRBNcA/latRBNcA.v"
primitive latRBNcA (Q_B, D, EN, R_B);
output Q_B; reg Q_B;
input  D,EN,R_B;

table
//	D  EN  R_B :state:	output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        1   1   0  : ? :        0 ; // clear output
        0   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        1 ; // latch data
        1   1   1  : ? :        0 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 1 :        1 ; // reducing pessimism
        1   x   1  : 0 :        0 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/DAff/DAff.v"
module DAff (Q_B, CLK, DAdata, D_B, DA_B);
    output Q_B;
    input CLK;
    input DAdata;
    input D_B;
    input DA_B;
    supply1 vdd;
    supply0 gnd;

    buf #(1) I1000(hnl_1000, DAdata);
    buf #(1) I1001(hnl_1001, D_B);
    buf #(1) I1002(hnl_1002, d_bs1);
    nand nandd(outd, outc, DA_B);
    nand nandb(lclk, outa, DA_B);
    not (weak0,weak1) #(1) U68(q_bs2, x);
    cxfr U76(q_bs2, hnl_222, DA_B, hnl_1000);
    cxfr U70(q_bs2, lclkb, lclk, hnl_1002);
    cxfr U64(ds1, lclk, lclkb, hnl_1001);
    not #(1) I77(hnl_222, DA_B);
    not #(1) I63(x, q_bs2);
    not #(1) I62(Q_B, q_bs2);
    not inc(outc, CLK);
    not ina(outa, CLK);
    not ine(lclkb, outd);
    not #(1) U65(d_bs1, ds1);
    not (weak0,weak1) #(1) I59(ds1, d_bs1);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latBarSB/latBarSB.v"
primitive latBarSB (Q, D_B, EN, S);
output Q; reg Q;
input  D_B,EN,S;

table
//	D_B  EN   S  :state:	output/next state
        ?     0   0  : ? :      - ; // no change
        ?     0   1  : ? :      1 ; // set output
        0     1   1  : ? :      1 ; // set output
        1     1   1  : ? :      x ; // conflict

        0     1   0  : ? :      1 ; // latch data
        1     1   0  : ? :      0 ; // latch data
        x     1   0  : ? :      x ; // latch data

        0     x   0  : 1 :      1 ; // reducing pessimism
        1     x   0  : 0 :      0 ; // reducing pessimism
        ?     p   ?  : ? :      - ;
        ?     0   ?  : 1 :      - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBNcD/ffBNcD.v"
primitive ffBNcD (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes
//      neg logic output

//      CLKedge D :state: output/nextState
        n       0 : ? :   1;
        n       1 : ? :   0;
        // ignore positive edge of clock
        p       ? : ? :   -;
        // ignore data changes on steady clock
        ?       * : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffD/ffD.v"
primitive ffD (Q, D, CLK);
    output Q; reg Q;
    input CLK;
    input D;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      D  CLKedge  :state: output/nextState
        0    n      : ? :   0;
        1    n      : ? :   1;
        // ignore positive edge of clock
        ?    p      : ? :   -;
        // ignore data changes on steady clock
        *    ?      : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latBNcC/latBNcC.v"
primitive latBNcC (Q, EN, D_B);
    output Q; reg Q;
    input EN;
    input D_B;

table
//     EN  D_B:state:   output/next state
        0   ? :  ?  :     - ; // no change

        1   0 :  ?  :     1 ; // transparent data
        1   1 :  ?  :     0 ; // transparent data
        1   x :  ?  :     x ; // latch data
 
        x   0 :  1  :     1 ; // reducing pessimism
        x   1 :  0  :     0 ; // reducing pessimism
        p   ? :  ?  :     - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBNcB/ffBNcB.v"
primitive ffBNcB (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//         CLKedge  D_B :state: output/nextState
             n      0   : ? :   1;
             n      1   : ? :   0;
        // ignore positive edge of clock
             p      ?   : ? :   -;
        // ignore data changes on steady clock
             ?      *   : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/hitSel/hitSel.v"
primitive mux211 (Y_B, A, B, SEL, EN);
output Y_B; reg Y_B;
input A, B, SEL, EN;

table
//  A B SEL EN : state : Y_B/next_state
    0 ?  0  1  :  ?    : 1;     // select from A
    1 ?  0  1  :  ?    : 0;     // select from A
    ? 0  1  1  :  ?    : 1;     // select from B
    ? 1  1  1  :  ?    : 0;     // select from B
    0 0  ?  1  :  ?    : 1;     // reduce pessimism
    1 1  ?  1  :  ?    : 0;     // reduce pessimism
    ? ?  ?  0  :  ?    : -;     // no change
endtable

endprimitive

module hitSel (packetRASaddr_b, partialId_b, pd2, pd1, sel, writeA0123);
    output packetRASaddr_b;
    output partialId_b;
    input pd2;
    input pd1;
    input sel;
    input writeA0123;

  mux211 #(1) mux0 (partialId_b,     pd2, pd1, sel, writeA0123);
  mux211 #(1) mux1 (packetRASaddr_b, pd1, pd2, sel, writeA0123);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/mux21s/mux21s.v"
// Description of an mux21s
primitive mux21s(Y, A, B, SelB, SelB_B);
output Y;
input A, B, SelB, SelB_B;

table
//	A  B  SelB SelB_B: Y
	?  1  1    0     : 1;
	?  0  1    0     : 0;
	1  ?  0    1     : 1;
	0  ?  0    1     : 0;
	0  0  ?    ?     : 0;
	1  1  ?    ?     : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latRB/latRB.v"
primitive latRB (Q, D, EN, R_B);
output Q; reg Q;
input  D,EN,R_B;

table
//	D  EN  R_B :state:	output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        0   1   0  : ? :        0 ; // clear output
        1   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        0 ; // latch data
        1   1   1  : ? :        1 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 0 :        0 ; // reducing pessimism
        1   x   1  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/xnandpc2/xnandpc2.v"
module xnandpc2 (Y, A, PC, B);
    inout Y;
    input A;
    input PC;
    input B;

supply1 vdd;
supply0 gnd;
tranif0 P1(Y, vdd, PC);
not #(1) U15(A_b, A1);
not #(1) U12(B_b, B);
buf I1010(A1, A);
cxfr U11(xnorAB, B_b, B, A_b);
cxfr U10(xnorAB, B, B_b, A1);
tranif1 N4(hnl_336, gnd, xnorAB);
tranif1 N8(Y, hnl_336, PC);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latRA/latRA.v"
primitive latRA (Q, D, EN, R_B);
output Q; reg Q;
input  D,EN,R_B;

table
//	D  EN  R_B :state:	output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        0   1   0  : ? :        0 ; // clear output
        1   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        0 ; // latch data
        1   1   1  : ? :        1 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 0 :        0 ; // reducing pessimism
        1   x   1  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/countup/countup.v"
module countup (cout_b, q_b, cnt_b, cin_b, ldCount, data);
    output cout_b;
    output q_b;
    input cnt_b;
    input cin_b;
    input ldCount;
    input data;

	supply1 vdd;
	supply0 gnd;
	not (weak0,weak1) #(1) I5013(n5, hnl_96);
	nor #(1) I5007(n7, cin_b, q_b);
	not (weak0,weak1) #(1) I7(n3, n4);
	buf (buf_data, data);
	tranif1 I5005(buf_data, n5, ldCount);
	tranif1 I5000(n3, hnl_97, cnt_b);
	not #(1) I5004(q_b, n5);
	not #(1) I5067(hnl_96, n5);
	cxfr I5012(n2, cin_b, n8, n1);
	cxfr I5010(n2, n8, cin_b, n6);
	buf (buf_n4, n4);
	cxfr I5003(n5, n9, cnt_b, buf_n4);
	not #(1) I5011(n8, cin_b);
	not #(1) I5009(n6, n1);
	not #(1) I5008(cout_b, n7);
	not #(1) I5006(n1, q_b);
	not #(1) I5002(n4, n3);
	not #(1) I5001(n9, cnt_b);
	not #(1) U5066(hnl_97, n2);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/countdn/countdn.v"
module countdn (cout_b, q_b, cnt_b, cin_b, ldCount, data);
    output cout_b;
    output q_b;
    input cnt_b;
    input cin_b;
    input ldCount;
    input data;

	supply1 vdd;
	supply0 gnd;
	not (weak0,weak1) #(1) I7000(n3, n4);
	not (weak0,weak1) #(1) I7001(n5, hnl_96);
	buf I7002(buf_data, data);
	tranif1 I7003(buf_data, n5, ldCount);
	tranif1 I7004(n3, hnl_97, cnt_b);
	nor #(1) I7005(n7, cin_b, n1);
	not #(1) I7006(hnl_96, n5);
	not #(1) I7007(q_b, n5);
	buf I7022(buf_n4, n4);
	cxfr I7008(n5, n9, cnt_b, buf_n4);
	cxfr I7009(n2, cin_b, n8, n1);
	cxfr I7010(n2, n8, cin_b, n6);
	not #(1) I7011(n9, cnt_b);
	not #(1) I7012(n4, n3);
	not #(1) I7013(n1, q_b);
	not #(1) I7014(n6, n1);
	not #(1) I7015(n8, cin_b);
	not #(1) I7016(cout_b, n7);
	not #(1) U7017(hnl_97, n2);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ltxBarB/ltxBarB.v"
module ltxBarB (Q, EN, D_B);
    output Q;
    input EN;
    input D_B;

        latBNcA #(2) latBNcA0(Q, EN, D_B);

endmodule


// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latSRB/latSRB.v"
primitive latSRB (Q, D, EN, R_B, S);
    output Q; reg Q;
    input D;
    input EN;
    input R_B;
    input S;

table
//      D  EN  R_B  S  :state:      output/next state
        ?   0   1   0  : ? :        - ; // no change
        ?   0   0   0  : ? :        0 ; // clear output
        0   1   0   0  : ? :        0 ; // clear output
        1   1   0   0  : ? :        x ; // conflict

        ?   0   1   1  : ? :        1 ; // set output
        0   1   1   1  : ? :        1 ; // set output
        1   1   1   1  : ? :        x ; // conflict
        ?   ?   0   1  : ? :        x ; // conflict

        0   1   1   0  : ? :        0 ; // latch data
        1   1   1   0  : ? :        1 ; // latch data
        x   1   1   0  : ? :        x ; // latch data

        0   x   1   0  : 0 :        0 ; // reducing pessimism
        1   x   1   0  : 1 :        1 ; // reducing pessimism
        ?   p   ?   ?  : ? :        - ;
        ?   0   ?   0  : 0 :        - ; // reducing pessimism
        ?   0   1   ?  : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/aoi211A/aoi211A.v"
// Description of an AND-OR-INVERT gate
// y = not ((A1 & A2) | B | C)
primitive aoi211A(Y, A1, A2, B, C);
output Y;
input A1, A2, B, C;

table
//	A1 A2 B  C : Y
	1  1  ?  ? : 0;
	?  ?  1  ? : 0;
	?  ?  ?  1 : 0;
	0  ?  0  0 : 1;
	?  0  0  0 : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffQBB/ffQBB.v"
module ffQBB (Q, QB, D, CLK);
    output Q;
    output QB;
    input D;
    input CLK;

        supply1 vdd;
        supply0 gnd;
        ffA I1100(Q, D, CLK);
        not I1101(QB, Q);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffQBC/ffQBC.v"
module ffQBC (Q, QB, D, CLK);
    output Q;
    output QB;
    input D;
    input CLK;

        supply1 vdd;
        supply0 gnd;
        ffA I1100(Q, D, CLK);
        not I1101(QB, Q);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBarA/ffBarA.v"
primitive ffBarA (Q, CLK, D_B);
output Q; reg Q;
input  CLK, D_B;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes
//	neg logic output

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   1;
	n 	1 : ? :   0;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latEnbSB/latEnbSB.v"
primitive latEnbSB (Q, D, S, ENB);
output Q; reg Q;
input  D,S,ENB;

table
//	D   S  ENB  :state:	output/next state
        ?   0   1   : ? :        - ; // no change
        ?   1   1   : ? :        1 ; // set output
        1   1   0   : ? :        1 ; // set output
        0   1   0   : ? :        x ; // x if conflict

        0   0   0   : ? :        0 ; // latch data
        1   0   0   : ? :        1 ; // latch data
        x   0   0   : ? :        x ; // latch data

        0   0   x   : 0 :        0 ; // reducing pessimism
        1   0   x   : 1 :        1 ; // reducing pessimism
        ?   ?   p   : ? :        - ;
        ?   ?   1   : 1 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latBNcA/latBNcA.v"
primitive latBNcA (Q, EN, D_B);
    output Q; reg Q;
    input EN;
    input D_B;

table
//     EN  D_B:state:   output/next state
        0   ? :  ?  :     - ; // no change

        1   0 :  ?  :     1 ; // transparent data
        1   1 :  ?  :     0 ; // transparent data
        1   x :  ?  :     x ; // latch data
 
        x   0 :  1  :     1 ; // reducing pessimism
        x   1 :  0  :     0 ; // reducing pessimism
        p   ? :  ?  :     - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latBarB/latBarB.v"
module latBarB (Q, EN, D_B);
    output Q;
    input EN;
    input D_B;

	latBNcA #(2) latBNcA0(Q, EN, D_B);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBarC/ffBarC.v"
primitive ffBarC (Q_B, CLK, D);
output Q_B; reg Q_B;
input  CLK, D;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes
//	neg logic output

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   1;
	n 	1 : ? :   0;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffA/ffA.v"
primitive ffA (Q, D, CLK);
    output Q; reg Q;
    input D;
    input CLK;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      D  CLKedge :state: output/nextState
        0    n     : ? :   0;
        1    n     : ? :   1;
        // ignore positive edge of clock
        ?    p     : ? :   -;
        // ignore data changes on steady clock
        *    ?     : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBarB/ffBarB.v"
primitive ffBarB (Q, CLK, D_B);
output Q; reg Q;
input  CLK, D_B;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes
//	neg logic output

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   1;
	n 	1 : ? :   0;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffRA/ffRA.v"
primitive ffRA (Q, CLK, R_B, D);
    output Q; reg Q;
    input CLK;
    input R_B;
    input D;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge R_B D   :state: output/nextState
        n       ?   0   : ? :   0;
        n       1   1   : ? :   1;
        // ignore positive edge of clock
        p       ?   ?   : ? :   -;
        // ignore data changes on steady clock
        ?       1   *   : ? :   -;
        // set output to 0
        ?       0   ?   : ? :   0;
        ?       *   ?   : 0 :   -;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/srff/srff.v"
primitive srff (Q, S_B, R_B);
    output Q;reg Q;
    input S_B;
    input R_B;

table
//  S_B R_B : state : output/next state
     1   1  :  ?    :    -    ;
     1   0  :  ?    :    0    ;
     0   1  :  ?    :    1    ;
     0   0  :  ?    :    1    ;
     0   x  :  ?    :    1    ;
     1   x  :  0    :    -    ;
     x   1  :  1    :    -    ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBNcRA/ffBNcRA.v"
primitive ffBNcRA (Q, CLK, D_B, R_B);
    output Q; reg Q;
    input CLK;
    input D_B;
    input R_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D_B R_B  :state: output/nextState
        n        0  1    : ? :   1;
        n        1  ?    : ? :   0;
        // ignore positive edge of clock
        p        ?  ?    : ? :   -;
        // ignore data changes on steady clock
        ?        *  1    : ? :   -;
        // set output to 0
        ?        ?  0    : ? :   0;
        ?        ?  *    : 0 :   -;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/mux31/mux31.v"
// Description of an mux31
primitive mux31(Y_B, A, B, C, SelA, SelB, SelC);
output Y_B;reg Y_B;
input A, B, C, SelA, SelB, SelC;

table
//	A B C   SelA SelB SelC : state : Y_B/next state
	1 ? ?   1    0    0    :   ?   :   0 ;
	0 ? ?   1    0    0    :   ?   :   1 ;
	? 1 ?   0    1    0    :   ?   :   0 ;
	? 0 ?   0    1    0    :   ?   :   1 ;
	? ? 1   0    0    1    :   ?   :   0 ;
	? ? 0   0    0    1    :   ?   :   1 ;
	? ? ?   0    0    0    :   ?   :   - ; //no change
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffB/ffB.v"
primitive ffB (Q, CLK, D);
output Q; reg Q;
input  CLK, D;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   0;
	n 	1 : ? :   1;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffRC/ffRC.v"
primitive ffRC (Q, CLK, R_B, D);
    output Q; reg Q;
    input CLK;
    input R_B, D;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge R_B D   :state: output/nextState
        n       1   0   : ? :   0;
        n       1   1   : ? :   1;
        // ignore positive edge of clock
        p       ?   ?   : ? :   -;
        // ignore data changes on steady clock
        ?       1   *   : ? :   -;
        // set output to 1
        ?       0   ?   : ? :   0;
        ?       *   ?   : ? :   0;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/oai21A/oai21A.v"
// Description of an OR-AND-INVERT gate
// y = not ((A1 | A2) & B)
primitive oai21A(Y, A1, A2, B);
output Y;
input A1, A2, B;

table
//	A1 A2 B	: Y
	1  ?  1 : 0;
	?  1  1 : 0;
	0  0  ? : 1;
	?  ?  0 : 1;
endtable

endprimitive

// Description of new_mux41.  A four to one mux
// with 2 select lines.  One line have to be
// selected all the time.
primitive new_mux41 (Y_B, A, B, C, D, Sel1, Sel0);
output Y_B;reg Y_B;
input A,B,C,D,Sel1,Sel0;

table
//      A  B  C  D Sel1 Sel0 : state: Y_B/next state
        0  ?  ?  ?  0    0   :   ?  :    1;     // sel 00
        1  ?  ?  ?  0    0   :   ?  :    0;

        ?  0  ?  ?  0    1   :   ?  :    1;     // sel 01
        ?  1  ?  ?  0    1   :   ?  :    0;

        ?  ?  0  ?  1    0   :   ?  :    1;     // sel 10
        ?  ?  1  ?  1    0   :   ?  :    0;

        ?  ?  ?  0  1    1   :   ?  :    1;     // sel 11
        ?  ?  ?  1  1    1   :   ?  :    0;

        0  0  ?  ?  0    ?   :   ?  :    1;     // sel 0x
        1  1  ?  ?  0    ?   :   ?  :    0;

        ?  ?  0  0  1    ?   :   ?  :    1;     // sel 1x
        ?  ?  1  1  1    ?   :   ?  :    0;

        0  ?  0  ?  ?    0   :   ?  :    1;     // sel x0
        1  ?  1  ?  ?    0   :   ?  :    0;

        ?  0  ?  0  ?    1   :   ?  :    1;     // sel x1
        ?  1  ?  1  ?    1   :   ?  :    0;

        0  0  0  0  ?    ?   :   ?  :    1;     // sel xx
        1  1  1  1  ?    ?   :   ?  :    0;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/mux41/mux41.v"
// Description of an mux41
primitive mux41 (Y_B, A, B, C, D, SelA, SelB, SelC, SelD);
output Y_B;reg Y_B;
input A,B,C,D,SelA,SelB,SelC,SelD;

table
//	A  B  C  D SelA SelB SelC SelD : state: Y_B/next state
        1  ?  ?  ?  1    0    0    0   :   ?  :    0;
        0  ?  ?  ?  1    0    0    0   :   ?  :    1;
        ?  1  ?  ?  0    1    0    0   :   ?  :    0;
        ?  0  ?  ?  0    1    0    0   :   ?  :    1;
        ?  ?  1  ?  0    0    1    0   :   ?  :    0;
        ?  ?  0  ?  0    0    1    0   :   ?  :    1;
        ?  ?  ?  1  0    0    0    1   :   ?  :    0;
        ?  ?  ?  0  0    0    0    1   :   ?  :    1;
        ?  ?  ?  ?  0    0    0    0   :   ?  :    -; // no change
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latB/latB.v"
module latB (Q, D, EN);
    output Q;
    input D;
    input EN;

	latBNcA #(2) latBNcA0(Q_b, EN, D);
	not not0(Q, Q_b);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBNcA/ffBNcA.v"
primitive ffBNcA (Q, CLK, D_B);
    output Q; reg Q;
    input CLK;
    input D_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//         CLKedge  D_B :state: output/nextState
             n      0   : ? :   1;
             n      1   : ? :   0;
        // ignore positive edge of clock
             p      ?   : ? :   -;
        // ignore data changes on steady clock
             ?      *   : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latBEnbA/latBEnbA.v"
primitive latBEnbA (Q, D_B, ENB);
    output Q; reg Q;
    input D_B;
    input ENB;

table
//     D_B ENB:state:   output/next state
        ?   1 :  ?  :     - ; // no change

        0   0 :  ?  :     1 ; // transparent data
        1   0 :  ?  :     0 ; // transparent data
        x   0 :  ?  :     x ; // latch data

        0   x :  1  :     1 ; // reducing pessimism
        1   x :  0  :     0 ; // reducing pessimism
        ?   n :  ?  :     - ;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/latBarA/latBarA.v"
module latBarA (Q, EN, D_B);
    output Q;
    input EN;
    input D_B;

	latBNcA #(2) latBNcA0(Q, EN, D_B);

endmodule

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/mux21/mux21.v"
// Description of an mux21
primitive mux21(Y, A, B, SelB);
output Y;
input A, B, SelB;

table
//	A  B  SelB : Y
        ?  1  1    : 1;
        ?  0  1    : 0;
        1  ?  0    : 1;
        0  ?  0    : 0;
        0  0  ?    : 0;
        1  1  ?    : 1;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffNcA/ffNcA.v"
primitive ffNcA (Q, D, CLK);
    output Q; reg Q;
    input D;
    input CLK;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      D  CLKedge :state: output/nextState
        0    n     : ? :   0;
        1    n     : ? :   1;
        // ignore positive edge of clock
        ?    p     : ? :   -;
        // ignore data changes on steady clock
        *    ?     : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffC/ffC.v"
primitive ffC (Q, CLK, D);
output Q; reg Q;
input  CLK, D;

table
// 	Flipflop which changes its output on falling edge
//	Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//		as long as data is constant at input while CLK changes

//	CLKedge	D :state: output/nextState
	n 	0 : ? :   0;
	n 	1 : ? :   1;
	// ignore positive edge of clock
	p 	? : ? :   -;
	// ignore data changes on steady clock
	? 	* : ? :   -;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/aoi21A/aoi21A.v"
// Description of an AND-OR-INVERT gate
// y = not ((A1 & A2) | B)
primitive aoi21A(Y, A1, A2, B);
output Y;
input A1, A2, B;

table
//	A1 A2 B	: Y
	1  1  ? : 0;
	?  ?  1 : 0;
	0  ?  0 : 1;
	?  0  0 : 1;
endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ltxRB/ltxRB.v"
primitive ltxRB (Q, D, EN, R_B);
output Q; reg Q;
input  D,EN,R_B;

table
//      D  EN  R_B :state:      output/next state
        ?   0   1  : ? :        - ; // no change
        ?   0   0  : ? :        0 ; // clear output
        0   1   0  : ? :        0 ; // clear output
        1   1   0  : ? :        x ; // conflict

        0   1   1  : ? :        0 ; // latch data
        1   1   1  : ? :        1 ; // latch data
        x   1   1  : ? :        x ; // latch data

        0   x   1  : 0 :        0 ; // reducing pessimism
        1   x   1  : 1 :        1 ; // reducing pessimism
        ?   p   ?  : ? :        - ;
        ?   0   ?  : 0 :        - ; // reducing pessimism

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/ffBarRA/ffBarRA.v"
primitive ffBarRA (Q, CLK, D_B, R_B);
    output Q; reg Q;
    input CLK;
    input D_B;
    input R_B;

table
//      Flipflop which changes its output on falling edge
//      Assume ff is insensitive to edge rate of CLK (1-x-0 or 0-x-1)
//              as long as data is constant at input while CLK changes

//      CLKedge D_B R_B  :state: output/nextState
        n        0  1    : ? :   1;
        n        1  ?    : ? :   0;
        // ignore positive edge of clock
        p        ?  ?    : ? :   -;
        // ignore data changes on steady clock
        ?        *  1    : ? :   -;
        // set output to 0
        ?        ?  0    : ? :   0;
        ?        ?  *    : 0 :   -;

endtable

endprimitive

// HDL file - 
// /home/earth/usr2/u5/revD.0/chip/u5CMPV/u5CMPV.v"
module u5CMPV (CMPF, CMPV, Vext, VRef, VREG);
    output CMPF;
    input CMPV;
    input Vext;
    input VRef;
    input VREG;

supply1 vdd;
supply0 gnd;
not #(1) U137(hnl_151, hnl_152);
tranif0 P134(hnl_153, vdd, hnl_154);
tranif0 N133(hnl_154, vdd, hnl_154);
tranif1 N132(hnl_153, hnl_157, VREG);
tranif1 N131(hnl_154, hnl_157, VRef);
tranif1 N130(hnl_157, gnd, hnl_151);
not #(1) U141(CMPF, hnl_153);
not #(1) U136(hnl_152, CMPV);

endmodule


// End HDL models


module lvtncap (MINUS, PLUS);
inout MINUS, PLUS;
supply1 vdd;
supply0 gnd;
endmodule

module u5BENSad (NSAdr_7_, NSAdr_6_, NSAdr_5_, NSAdr_4_, NSAdr_3_, NSAdr_2_, NSAdr_1_, NSAdr_0_, BEevenD, BEoddD, loadNSAdr, rclk, writeOp_b);
output NSAdr_7_, NSAdr_6_, NSAdr_5_, NSAdr_4_, NSAdr_3_, NSAdr_2_, NSAdr_1_, NSAdr_0_;
input BEevenD, BEoddD, loadNSAdr, rclk, writeOp_b;
supply1 vdd;
supply0 gnd;
ffBarRA F94BO(hnl_0, gnd, gnd, vdd);
ltxRB F94BN(hnl_1, gnd, gnd, vdd);
aoi21A #(1) F94BM(hnl_2, gnd, gnd, gnd);
ffC #(1) F94BL(hnl_3, gnd, gnd);
nand #(0) F94BI(hnl_4, gnd, gnd, gnd, gnd);
nor #(1) F94BK(hnl_5, gnd, gnd);
nor #(1) F94BJ(hnl_6, gnd, gnd);
nand #(1) F94BH(hnl_7, gnd, gnd);
nand #(1) F94BG(hnl_8, gnd, gnd);
not #(1) F94BF(hnl_9, gnd);
not #(1) F94BE(hnl_10, gnd);
ffNcA I160(hnl_11, BEoddD, rclk);
ffNcA I159(hnl_12, hnl_11, rclk);
ffNcA I158(hnl_13, hnl_12, rclk);
ffNcA I155(hnl_14, hnl_15, rclk);
ffNcA I154(hnl_15, hnl_16, rclk);
ffNcA I153(hnl_16, BEevenD, rclk);
mux21 #(1) I152(hnl_17, hnl_14, BEevenD, writeOp_b);
mux21 #(1) I146(hnl_18, hnl_13, BEoddD, writeOp_b);
latBarA I140(pre3, rclk, hnl_19);
latBarA I139(pre1, rclk, hnl_20);
latBarA I137(pre5, rclk, hnl_21);
latBarA I135(pre7, rclk, hnl_18);
latBarA I134(pre0, rclk, hnl_22);
latBarA I126(pre6, rclk, hnl_17);
latBarA I124(pre4, rclk, hnl_23);
latBarA I121(pre2, rclk, hnl_24);
latBEnbA I141(hnl_20, pre3, rclk);
latBEnbA I138(hnl_19, pre5, rclk);
latBEnbA I136(hnl_21, pre7, rclk);
latBEnbA I122(hnl_24, pre4, rclk);
latBEnbA I123(hnl_23, pre6, rclk);
latBEnbA I120(hnl_22, pre2, rclk);
ffBNcA I119(hnl_25, loadNSAdr, pre7);
ffBNcA I118(hnl_26, loadNSAdr, pre5);
ffBNcA I117(hnl_27, loadNSAdr, pre3);
ffBNcA I116(hnl_28, loadNSAdr, pre1);
ffBNcA I115(hnl_29, loadNSAdr, pre6);
ffBNcA I114(hnl_30, loadNSAdr, pre4);
ffBNcA I113(hnl_31, loadNSAdr, pre2);
ffBNcA I112(hnl_32, loadNSAdr, pre0);
not #(1) I110(NSAdr_3_, hnl_27);
not #(1) I109(NSAdr_5_, hnl_26);
not #(1) I86(NSAdr_7_, hnl_25);
not #(1) I85(NSAdr_6_, hnl_29);
not #(1) I84(NSAdr_1_, hnl_28);
not #(1) I80(NSAdr_2_, hnl_31);
not #(1) I77(NSAdr_0_, hnl_32);
not #(1) I74(NSAdr_4_, hnl_30);
endmodule

module invEEbuf (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) I17(hnl_33, hnl_34);
not #(1) U9(Y, hnl_33);
not #(1) U16(hnl_34, A);
endmodule

module u5OpDeco (MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, writeMaskedNSOp_b, writeOp_b, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, op_3_, op_0_,
op_b_2_, op_b_1_, preCycState4, reset_b);
output MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, writeMaskedNSOp_b, writeOp_b;
input DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, op_3_, op_0_, op_b_2_, op_b_1_, preCycState4, reset_b;
supply1 vdd;
supply0 gnd;
ltxRB I356(hnl_35, hnl_36, preCycState4, reset_b);
ltxRB I355(hnl_37, hnl_38, preCycState4, reset_b);
ltxRB I354(REQinhibiten, hnl_39, preCycState4, reset_b);
not #(1) U345(writeOp_b, hnl_40);
not #(1) U254(op_1_, op_b_1_);
nor #(1) I333(abortOperation_b, illegalOpCode, initAbort);
aoi21A #(1) U332(colD, op_b_2_, op_b_3_, op_1_);
nor #(1) U331(colC, op_1_, hnl_41, hnl_42);
nor #(1) U340(hnl_43, op_b_1_, op_2_);
nor #(1) U330(hnl_41, op_2_, op_3_);
nor #(1) U329(hnl_42, op_b_2_, op_b_3_);
nor #(1) U328(selD, OpX_b_1_, OpX_b_0_);
nor #(1) U327(selC, OpX_b_1_, OpX_0_);
nor #(1) U326(selB, OpX_1_, OpX_b_0_);
nor #(1) U325(selA, OpX_1_, OpX_0_);

////////////////////////////////////////////////////////////////////////////////

// hack

//mux41 #(1) I320(illegalOpCode, colA, op_b_1_, colC, colD, selA, selB, selC, selD);

new_mux41 #(1) I320(illegalOpCode, colA, op_b_1_, colC, colD, OpX_1_, OpX_0_);

////////////////////////////////////////////////////////////////////////////////

not #(1) U305(WPBNP, hnl_44);
invEEbuf U300(MPBT, hnl_45);
invEEbuf U299(WPBT, hnl_46);
nor #(1) U342(colA, hnl_43, hnl_47);
nor #(1) U292(initAbort, hnl_48, deviceEnableMode);
nor #(1) U289(hnl_38, OpX_1_, OpX_0_);
nor #(1) U343(hnl_47, op_b_3_, op_b_1_, op_0_);
nor #(1) U281(hnl_49, op_b_3_, op_b_2_, op_1_);
not #(1) U256(writeMaskedNSOp_b, hnl_49);
mux21 #(1) I347(hnl_50, op_b_0_, op_b_2_, op_b_1_);
mux21 #(1) I219(hnl_45, hnl_51, hnl_35, DAmode_b);
mux21 #(1) I212(hnl_46, hnl_52, hnl_37, DAmode_b);
nand #(1) U346(hnl_40, hnl_50, op_b_3_);
nand #(1) I243(NSOp, hnl_53, hnl_54);
nand #(1) U317(hnl_39, hnl_55, writeMaskedNSOp_b);
oai21A U291(hnl_48, regWrite_b, SInRaw_b, bcastWrite_b);
nand #(1) U319(hnl_53, op_b_2_, OpX_0_);
nand #(1) U275(hnl_54, op_3_, op_b_1_);
nand #(1) U313(hnl_55, op_3_, WPBNP);
nand #(1) U285(hnl_36, OpX_1_, OpX_0_);
nand #(1) U284(hnl_44, colC, selC);
nand #(1) U271(regWrite_b, op_1_, op_0_);
nand #(1) U270(bcastWrite_b, op_3_, op_1_);
not #(1) U349(op_b_0_, op_0_);
not #(1) U236(hnl_51, TestMPBT);
not #(1) U224(hnl_52, TestWPBT);
not #(1) U320(op_2_, op_b_2_);
not #(1) U253(op_b_3_, op_3_);
not #(1) U233(OpX_b_1_, OpX_1_);
not #(1) U232(OpX_b_0_, OpX_0_);
endmodule

module u5CdlyCt (preCycState4, preCycState5, startCycle_b, CASenable, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, reset_b, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_,
writeOp_b);
output preCycState4, preCycState5, startCycle_b;
input CASenable, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, reset_b, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_, writeOp_b;
supply1 vdd;
supply0 gnd;
nor #(1) U576(hnl_56, reset, hnl_57);
ffRC I488(preCycState4, rclk, reset_b, writeA45);
nor #(1) U568(hnl_58, Q2, Q1, Q0_b);
ffC #(1) I443(preCycState5, rclk, preCycState4);
mux21 #(1) I582(hnl_59, delayStart_b, preCycState4, delay0);
mux21 #(1) I579(hnl_60, hnl_58, preCycState4, delay1);
mux21 #(1) I489(hnl_59, delayStart_b, preCycState4, delay0);
nand #(0) U572(hnl_61, readDelay_2_, readDelay_1_, readDelay_0_, writeOp_b);
nand #(0) U571(hnl_62, writeDelay_b_2_, writeDelay_b_1_, writeDelay_0_, writeOp);
nand #(0) U570(hnl_63, readDelay_b_2_, readDelay_b_1_, readDelay_b_0_, writeOp_b);
nand #(0) U569(hnl_64, writeDelay_b_2_, writeDelay_1_, writeDelay_b_0_, writeOp);
not #(1) U581(preCycState4_b, preCycState4);
not #(1) U529(writeOp, writeOp_b);
nand #(1) U566(hnl_65, hnl_66, hnl_67, hnl_68);
ffBarRA I557(Q0, rclk, hnl_69, hnl_56);
ffBarRA I556(Q1, rclk, hnl_70, hnl_56);
ffBarRA I554(Q2, rclk, hnl_71, hnl_56);
aoi21A #(1) U538(hnl_72, writeDelay_b_1_, writeDelay_b_0_, writeDelay_b_2_);
nand #(1) U574(delay0, hnl_62, hnl_61);
nand #(1) U573(delay1, hnl_64, hnl_63);
nand #(1) I551(hnl_73, hnl_74, hnl_75);
nand #(1) I550(hnl_76, hnl_77, hnl_74);
nand #(1) U546(hnl_78, hnl_79, hnl_80);
nand #(1) U541(hnl_81, hnl_68, hnl_82);
nand #(1) U535(Y2, hnl_83, hnl_84);
nand #(1) U565(hnl_66, writeDelay_b_1_, writeDelay_b_0_);
nand #(1) U564(hnl_67, writeDelay_2_, writeDelay_b_0_);
nand #(1) U548(hnl_75, readDelay_b_1_, readDelay_0_);
nand #(1) U545(hnl_74, readDelay_b_2_, readDelay_1_);
nand #(1) U544(hnl_77, readDelay_2_, readDelay_b_0_);
nand #(1) U543(hnl_80, readDelay_2_, readDelay_b_1_);
nand #(1) U540(hnl_82, writeDelay_1_, writeDelay_0_);
nand #(1) U539(hnl_68, writeDelay_2_, writeDelay_b_1_);
nand #(1) U533(hnl_83, Q1, Q0_b);
nor #(1) U575(hnl_57, CASenable, preCycState5_b);
nor #(1) U528(loadRead, preCycState4_b, writeOp);
nor #(1) U527(loadWrite, preCycState4_b, writeOp_b);
nand #(1) U542(hnl_79, readDelay_b_2_, readDelay_1_, readDelay_0_);
nand #(1) U534(hnl_84, Q2, Q1_b, Q0);
ffB #(1) I492(delayStart_b, rclk, hnl_60);
mux31 #(1) I507(hnl_71, Y2, hnl_72, hnl_78, preCycState4_b, loadWrite, loadRead);
mux31 #(1) I509(hnl_69, Q1, hnl_81, hnl_73, preCycState4_b, loadWrite, loadRead);
mux31 #(1) I508(hnl_70, Q2, hnl_65, hnl_76, preCycState4_b, loadWrite, loadRead);
not #(1) U486(startCycle_b, hnl_59);
not #(1) U580(preCycState5_b, preCycState5);
not #(1) U559(Q0_b, Q0);
not #(1) U558(Q1_b, Q1);
not #(1) U525(writeDelay_b_2_, writeDelay_2_);
not #(1) U524(writeDelay_b_1_, writeDelay_1_);
not #(1) U523(readDelay_b_2_, readDelay_2_);
not #(1) U522(readDelay_b_1_, readDelay_1_);
not #(1) U461(readDelay_b_0_, readDelay_0_);
not #(1) U387(writeDelay_b_0_, writeDelay_0_);
endmodule

module u5CDOpCk (MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, preCycState5, readOpDelay, regOp, startCycle_b, writeMaskedNSOp_b, writeOp_b, CASenable, DAmode_b, OpX_1_, OpX_0_, SInRaw_b,
TestMPBT, TestWPBT, deviceEnableMode, opcode_3_, opcode_0_, opcode_b_2_, opcode_b_1_, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_);
output MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, preCycState5, readOpDelay, regOp, startCycle_b, writeMaskedNSOp_b, writeOp_b;
input CASenable, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, opcode_3_, opcode_0_, opcode_b_2_, opcode_b_1_, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset,
writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_;
supply1 vdd;
supply0 gnd;
latB I309(readOpDelay, writeOp_b, preCycState5);
not #(1) I291(regOp, opcode_b_1_);
not #(1) U308(reset_b, reset);
u5OpDeco OpDeco(MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, writeMaskedNSOp_b, writeOp_b, DAmode_b, OpX_1_, OpX_0_, SInRaw_b, TestMPBT, TestWPBT, deviceEnableMode, opcode_3_, opcode_0_,
opcode_b_2_, opcode_b_1_, preCycState4, reset_b);
u5CdlyCt CdlyCt(preCycState4, preCycState5, startCycle_b, CASenable, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, reset_b, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_, writeOp_b);
endmodule

module u5RdTclk (rdPipeBusy_b, tclkDisable_b, CASstate3, earlyDone, rclk, readOpDelay, reset_b);
output rdPipeBusy_b, tclkDisable_b;
input CASstate3, earlyDone, rclk, readOpDelay, reset_b;
supply1 vdd;
supply0 gnd;
ffB #(1) I34(tclkDisable_b, rclk, stopCounterP_b);
not #(1) U32(rdPipeBusy_b, haltCount_b);
srff I31(haltCount_b, hnl_85, stopCounterP_b);
ffRA I30(stopCounterP_b, rclk, reset_b, hnl_86);
ffBarB #(1) I29(RdTCk3, rclk, RdTCk2);
ffA I27(RdTck1, hnl_87, rclk);
ffA I26(RdTCk2, RdTck1, rclk);
nand #(1) U35(hnl_85, CASstate3, earlyDone, readOpDelay);
nand #(1) U218(hnl_86, RdTCk3, RdTCk2, RdTck1);
nand #(1) U214(hnl_87, hnl_88, haltCount_b);
xor #(1) U220(hnl_88, RdTCk3, RdTCk2);
endmodule

module u5XS (gated_mclk, mclk_div16, rdPipeBusy_b, tclkDisable_b, CASstate3_buf, earlyDone, mclk, mclkOn, rclk, readOpDelay, reset);
output gated_mclk, mclk_div16, rdPipeBusy_b, tclkDisable_b;
input CASstate3_buf, earlyDone, mclk, mclkOn, rclk, readOpDelay, reset;
supply1 vdd;
supply0 gnd;
not #(1) U60(gated_mclk, hnl_89);
nand #(1) U55(hnl_90, mclkOn, mclk);
not #(1) U56(hnl_89, hnl_91);
not #(1) U51(mclk_div16, hnl_92);
ffBNcRA I53(hnl_93, mclk, hnl_93, reset_b);
ffBNcRA I50(hnl_92, hnl_94, hnl_92, reset_b);
ffBNcRA I49(hnl_94, hnl_95, hnl_94, reset_b);
ffBNcRA I41(hnl_95, hnl_93, hnl_95, reset_b);
not #(1) U59(hnl_91, hnl_90);
not #(1) U3(reset_b, reset);
u5RdTclk RdTclk(rdPipeBusy_b, tclkDisable_b, CASstate3_buf, earlyDone, rclk, readOpDelay, reset_b);
endmodule

module invEE (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) U9(Y, A);
endmodule

module u5GoFish (Out_T, In_R, mtclk, rclk, skip);
output Out_T;
input In_R, mtclk, rclk, skip;
supply1 vdd;
supply0 gnd;
mux21 #(1) I43(mg4, n03, n13, skip);
not #(1) I52(Out_T, mg6);
not #(1) U46(mg3, mg2);
not #(1) U54(hnl_96, gnd);
not #(1) U53(hnl_97, gnd);
not #(1) U55(hnl_90, gnd);
not #(1) I31(mg5, mg4);
not #(1) U44(mg1, mtclk);
ffA I25(n03, n01, txdly);
ffA I51(mg6, mg5, mtclk);
ffA I28(n01, In_R, rclk);
ffA I34(n13, n11, txdly);
latB I36(n11, In_R, rclk);
not #(5) U47(txdly, mg3);
not #(1) U45(mg2, mg1);
endmodule

module u5BSNack (BCOeven_b, BCOodd_b, RASaddrEnable, sytload_b, BusCtrlEn_b, LoadShiftRegister_b, ackLatch, bcastWrite, idHitA, idHitB, latchAbort_b, mtclk, nack, rclk, reset, skip, writeA45);
output BCOeven_b, BCOodd_b, RASaddrEnable, sytload_b;
input BusCtrlEn_b, LoadShiftRegister_b, ackLatch, bcastWrite, idHitA, idHitB, latchAbort_b, mtclk, nack, rclk, reset, skip, writeA45;
supply1 vdd;
supply0 gnd;
ffBarC #(1) I634(hnl_98, rclk, writeA45);
aoi21A #(1) U612(idBcw, idHitA, idHitB, bcastWrite);
not #(1) U626(T12, hnl_99);
invEE U635(RASaddrEnable, hnl_98);
invEE U625(sytload_b, hnl_100);
not #(1) U624(hnl_100, hnl_101);
u5GoFish BDsync(hnl_101, LoadShiftRegister_b, mtclk, rclk, skip);
u5GoFish BCsync(hnl_99, BusCtrlEn_b, mtclk, rclk, skip);
latBarB I620(T13, mtclk, hnl_99);
nand #(1) U606(BCOodd_b, T13, nk);
nand #(1) U607(BCOeven_b, T12, ok);
nor #(1) U615(okp, idNbcw, go_b, nack);
nor #(1) U613(nkp, nack_b, go_b, idBcw);
nand #(1) U608(idNbcw, idHitA, idHitB, bcastWrite_b);
nand #(1) U605(go_b, latchAbort_b, reset_b);
latBNcA I580(nk, ackLatch, hnl_102);
latBNcA I579(ok, ackLatch, hnl_103);
not #(1) U633(bcastWrite_b, bcastWrite);
not #(1) U614(nack_b, nack);
not #(1) U611(reset_b, reset);
not #(1) U581(hnl_102, nkp);
not #(1) U578(hnl_103, okp);
endmodule

module u5RshCtl (AUXRASreq, AUXorPDcycle, AUXpending_b, PDreq2, RASrfshRetD, RefreshReturn_b, closeCycle, closeCycle_b, closeReq_b, doAUXcycle, driveRfshAddr_b, endCycleD_buf, restoreBank0,
restoreBank1, PD64after, RASAUXRet_b, RASidle_b, clearPDreq2, close0Pending_b, close0Selected, close1Pending_b, close1Selected, decXferCnt_b, explicitRestore, idle, packetBSELx, powerDownReq_b, rclk,
reFetchCycle, reset, setRR_b, writeA45, writeA0123x);
output AUXRASreq, AUXorPDcycle, AUXpending_b, PDreq2, RASrfshRetD, RefreshReturn_b, closeCycle, closeCycle_b, closeReq_b, doAUXcycle, driveRfshAddr_b, endCycleD_buf, restoreBank0, restoreBank1;
input PD64after, RASAUXRet_b, RASidle_b, clearPDreq2, close0Pending_b, close0Selected, close1Pending_b, close1Selected, decXferCnt_b, explicitRestore, idle, packetBSELx, powerDownReq_b, rclk,
reFetchCycle, reset, setRR_b, writeA45, writeA0123x;
supply1 vdd;
supply0 gnd;
latEnbSB I431(hnl_104, powerDownReq_b, hnl_105, decXferCnt_b);
nand #(1) U501(AUXorPDcycle, doAUXcycle_b, hnl_106, PDreq2_b);
nor #(1) U493(hnl_107, idle_b, writeA0123x, writeA45);
ffBarA #(1) I497(hnl_108, rclk, hnl_109);
ffBarC #(1) I485(closeReq_b, rclk, PDclose);
nand #(1) U428(hnl_110, refreshCycle_b, PDreq2_b);
not #(1) U429(driveRfshAddr_b, hnl_110);
not #(1) U434(hnl_105, resetPD_b);
mux21 #(1) I500(preRB0, hnl_111, packetBSELx, explicitRestore);
mux21 #(1) I499(preRB1, hnl_112, hnl_113, explicitRestore);
mux21 #(1) I411(preRB1, hnl_112, hnl_113, explicitRestore);
mux21 #(1) I405(preRB0, hnl_111, packetBSELx, explicitRestore);
not #(1) U410(hnl_113, packetBSELx);
ffQBC I401(rfshSelected_b, rfshSelected, hnl_114, rclk);
ffB #(1) I479(PDreq2_b, rclk, hnl_115);
ffB #(1) I387(hnl_116, rclk, PD64after);
ffB #(1) I384(AUXRASreq, rclk, hnl_117);
not #(1) U365(RASrfshRetD, hnl_118);
nor #(1) I399(doAUXcycleLocal, A_0_, AUXpending_b);
nor #(1) F94DE(hnl_119, gnd, gnd);
nor #(1) I346(endCycle_b, hnl_120, reset);
not #(1) I448(endCycleD_buf, endCycleD_b);
not #(1) U322(doAUXcycle, doAUXcycle_b);
nor #(1) U314(cyclePending_b, rfshSelected, close0Selected, close1Selected);
nor #(1) U498(hnl_109, hnl_121, RASidle_b);
nor #(1) I352(hnl_120, hnl_49, A_0_);
nor #(1) U416(hnl_122, hnl_118, reFetchCycle);
nor #(1) U305(PDclose, powerDownReq_b, decXferCnt_b);
ffBarB #(1) I419(RASAUXRetD, rclk, RASAUXRet_b);
oai21A U487(hnl_123, hnl_107, hnl_124, A_b_1_);
oai21A U279(hnl_125, hnl_108, writeA0123x, A_0_);
oai21A U281(hnl_49, reFetchCycle, rfshSelected_b, RASAUXRetD);
nand #(1) I421(hnl_126, endCycle_b, endCycleD_b, hnl_127);
nand #(1) U377(hnl_117, hnl_128, startAUX_b, startPDRAScyc_b);
nand #(1) U276(hnl_129, endCycle_b, hnl_125, A_b_1_);
ffQBB I495(hnl_121, hnl_124, hnl_123, rclk);
ffQBB I403(endCycleD_b, endCycleD, endCycle_b, rclk);
ffQBB I396(closeCycle_b, closeCycle, hnl_130, rclk);
ffQBB I275(A_0_, A_b_0_, hnl_129, rclk);
ffQBB I273(AUXpending_b, A_b_1_, hnl_126, rclk);
nand #(1) U469(hnl_131, reset_b, powerDownReq_b);
nand #(1) F94DD(hnl_132, gnd, gnd);
nand #(1) U414(hnl_111, close0Selected, doAUXcycle);
nand #(1) U415(hnl_112, close1Selected, doAUXcycle);
nand #(1) U460(RefreshReturn_b, endCycleD, rfshSelected);
nand #(1) U417(hnl_118, rfshSelected, RASAUXRetD);
nand #(1) U292(doAUXcycle_b, A_b_1_, A_b_0_);
not #(1) U362(PDreq2, PDreq2_b);
not #(1) U229(restoreBank0, preRB0);
not #(1) U230(restoreBank1, preRB1);
aoi21A #(1) U245(hnl_133, endCycleD, rfshSelected, hnl_131);
ffBarA #(1) I332(rfshReq_b, rclk, hnl_134);
ffBarA #(1) I400(hnl_135, rclk, doAUXcycleLocal);
ffBarA #(1) I382(hnl_136, rclk, hnl_116);
nor #(1) U515(hnl_134, setRR_b, decXferCnt_b);
nor #(1) U502(hnl_106, close0Selected, close1Selected);
nor #(1) U357(resetPD_b, clearPDreq2, reset);
nand #(1) U481(hnl_137, rfshSelected, A_b_1_, A_b_0_);
nand #(1) U480(hnl_130, refreshCycle_b, doAUXcycle, hnl_115);
nand #(1) U445(hnl_114, rfshPending, close1Pending_b, close0Pending_b);
nand #(1) U309(setPDmode_b, close1Selected, endCycleD, powerDownReqL);
nand #(1) U397(startAUX_b, doAUXcycleLocal, hnl_135);
nand #(1) U383(startPDRAScyc_b, hnl_116, hnl_136);
nand #(1) U366(hnl_128, hnl_122, doAUXcycleLocal);
nand #(1) U278(hnl_127, cyclePending_b, AUXpending_b);
not #(1) U516(powerDownReqL, hnl_104);
not #(1) U494(idle_b, idle);
not #(1) U478(hnl_115, hnl_138);
not #(1) U467(reset_b, reset);
srff I342(refreshCycle_b, endCycleD_b, hnl_137);
srff I310(hnl_138, setPDmode_b, resetPD_b);
srff I244(rfshPending, rfshReq_b, hnl_133);
endmodule

module slDly (out, in_b);
output out;
input in_b;
supply1 vdd;
supply0 gnd;
not #(100) U54(out, hnl_139);
not #(1) U46(hnl_140, hnl_141);
not #(1) U43(hnl_142, hnl_143);
not #(1) U41(hnl_141, in_b);
not #(1) U39(hnl_143, hnl_144);
not #(1) U38(hnl_139, hnl_142);
not #(1) U36(hnl_145, hnl_140);
not #(1) U33(hnl_146, hnl_145);
not #(1) U31(hnl_144, hnl_146);
endmodule

module u5Rasb (RASB, RASpending, RASpending_b, clearPDreq2, drivePacketRASaddr, incRfshRow_b, powerDownMode, reFetchCycle, reFetchCycle_b, updateRowAddr, AUXRASreq, BIMDI, DAmode_b, PDreq2, RASkill,
RASprecharge, RASrfshRetD, RASstate4, RS_0_, SInRaw_b, TestRASB, clearRASpending_b, doAUXcycle, endPowerDown_b, explicitRestore, idHitRowMiss, latchAbort, rclk, reset, rfshCout_1_, setPD, standby,
writeA0123x);
output RASB, RASpending, RASpending_b, clearPDreq2, drivePacketRASaddr, incRfshRow_b, powerDownMode, reFetchCycle, reFetchCycle_b, updateRowAddr;
input AUXRASreq, BIMDI, DAmode_b, PDreq2, RASkill, RASprecharge, RASrfshRetD, RASstate4, RS_0_, SInRaw_b, TestRASB, clearRASpending_b, doAUXcycle, endPowerDown_b, explicitRestore, idHitRowMiss,
latchAbort, rclk, reset, rfshCout_1_, setPD, standby, writeA0123x;
supply1 vdd;
supply0 gnd;
aoi211A #(1) I825(hnl_147, RASstate4, idHitRowMiss, AUXRASreq, RASpending);
aoi211A #(1) I823(hnl_148, idHitRowMiss, RASstate4, RASleading, RASaddrEn);
not #(1) U625(RASB, hnl_149);
nor #(1) I816(RASaddrInh_b, hnl_150, explicitRestore);
invEE U815(drivePacketRASaddr, hnl_151);
ffRA I811(RASaddrEn, rclk, RASaddrInh_b, hnl_152);
not #(1) U810(hnl_151, RASaddrEn);
nor #(1) U800(hnl_153, hnl_147, latchAbort, hnl_154);
aoi21A #(1) U783(hnl_155, updateKill_b, setPD_b, hnl_156);
nand #(1) U786(hnl_157, RASleading, RASkill_b, updateKill_b);
ffB #(1) I775(RASp1, rclk, hnl_158);
ffB #(1) I774(RASp2, rclk, RASp1);
ffB #(1) I770(reFetchCycle_b, rclk, hnl_159);
not #(1) I753(reFetchCycle, reFetchCycle_b);
ffBarB #(1) I784(updateKill_b, rclk, hnl_155);
ffBarB #(1) I737(clearPDreq2, rclk, hnl_160);
nand #(1) U817(hnl_150, DAmode_b, RASkill_b, reset_b);
nand #(1) U771(hnl_159, hnl_161, reset_b, doAUXcycle);
nand #(1) U699(hnl_162, RASp1, RASp2, RASp3);
srff I805(hnl_163, endPowerDown_b, setPD_b);
srff I724(powerDownMode_b, endPowerDown_b, hnl_164);
slDly I714(delayedRASB_b, RASB);
not #(1) U711(incRfshRow_b, hnl_165);
nand #(1) I710(hnl_165, hnl_166, burstRfshInc_b);
nand #(1) U788(hnl_156, RS_0_, reset_b);
nand #(1) U592(hnl_167, hnl_168, DAmode_b);
ffA I767(burstRfshInc_b, hnl_169, rclk);
ffA I700(RASp3, RASp2, rclk);
ffQBC I697(RASpending, RASpending_b, hnl_153, rclk);
nor #(1) I693(RASleading, RASp2, hnl_170);
not #(1) U732(powerDownMode, powerDownMode_b);
not #(1) U681(updateRowAddr, hnl_157);
nand #(1) U698(hnl_171, hnl_162, forceRAS_b);
nor #(1) U812(hnl_152, hnl_148, doAUXcycle, writeA0123x);
nor #(1) U633(hnl_172, hnl_168, SInRaw_b);
nor #(1) U703(hnl_158, RASprecharge, hnl_167);
nor #(1) U647(forceRAS_b, hnl_173, hnl_172);
not #(1) U821(hnl_174, hnl_175);
not #(1) U820(hnl_149, hnl_174);
not #(1) U819(hnl_175, hnl_176);
not #(1) U818(hnl_176, hnl_171);
not #(1) U799(RASkill_b, RASkill);
not #(1) U806(hnl_177, hnl_163);
not #(1) U801(hnl_154, clearRASpending_b);
not #(1) U769(doAUXcycle_b, doAUXcycle);
not #(1) U730(hnl_178, BIMDI);
not #(1) U726(setPD_b, setPD);
not #(1) U657(reset_b, reset);
not #(1) U628(hnl_173, TestRASB);
not #(1) U600(hnl_168, PDreq2);
nand #(1) U807(hnl_164, hnl_177, standby);
nand #(1) U772(hnl_161, hnl_179, reFetchCycle_b);
nand #(1) U766(hnl_169, RASrfshRetD, reFetchCycle_b);
nand #(1) U746(hnl_179, RASrfshRetD, rfshCout_1_);
nand #(1) U738(hnl_160, RASprecharge, PDreq2);
nand #(1) U733(hnl_166, delayedRASB_b, PDrfshEn);
nand #(1) U731(PDrfshEn, powerDownMode_b, hnl_178);
nand #(1) U692(hnl_170, RASp1, doAUXcycle_b);
endmodule

module u5AkWDly (BC_oe, BusCtrlEn_b, ackClear, ackLatch, ackWinOverD, inhLoadLast_b, ackDelay_1_, ackDelay_0_, ackWinDelay_2_, ackWinDelay_1_, ackWinDelay_0_, bcastWrite, eval, framePulseX, idHitA,
idHitB, rclk, reset);
output BC_oe, BusCtrlEn_b, ackClear, ackLatch, ackWinOverD, inhLoadLast_b;
input ackDelay_1_, ackDelay_0_, ackWinDelay_2_, ackWinDelay_1_, ackWinDelay_0_, bcastWrite, eval, framePulseX, idHitA, idHitB, rclk, reset;
supply1 vdd;
supply0 gnd;
aoi21A #(1) U131(hnl_180, idHitA, idHitB, bcastWrite);
nand #(1) U129(BC_oe, hnl_25, reset_b);
srff I119(hnl_25, hnl_181, hnl_182);
ffBarB #(1) I115(inhLoadLast_b, rclk, hnl_183);
mux21 #(1) I98(hnl_184, hnl_185, hnl_186, code0567);
oai21A U83(hnl_183, ackWinOverD, inhLoadLast_b, eval);
nor #(1) U133(hnl_187, hnl_180, mtclken_b);
nor #(1) U6_3_(ackWsel_3_, ackWselect_b_0_, ackWselect_b_1_);
nor #(1) U6_2_(ackWsel_2_, ackWselect_0_, ackWselect_b_1_);
nor #(1) U6_1_(ackWsel_1_, ackWselect_b_0_, ackWselect_1_);
nor #(1) U6_0_(ackWsel_0_, ackWselect_0_, ackWselect_1_);
nand #(1) U89(hnl_188, ackWselect_b_0_, ackWselect_b_1_, ackWselect_b_2_);
oai21A U88(hnl_189, ackWselect_1_, ackWselect_0_, ackWselect_2_);
nand #(1) U78(ackLatch, hnl_190, mtclken_b, reset_b);
latB I59_1_(ackSelect_1_, ackDelay_1_, framePulseX);
latB I59_0_(ackSelect_0_, ackDelay_0_, framePulseX);
latB I58_2_(ackWselect_2_, ackWinDelay_2_, framePulseX);
latB I58_1_(ackWselect_1_, ackWinDelay_1_, framePulseX);
latB I58_0_(ackWselect_0_, ackWinDelay_0_, framePulseX);
nand #(1) U20(code0567, hnl_189, hnl_188);
not #(1) U97(BusCtrlEn_b, hnl_191);
not #(1) U73_1_(ackSelect_b_1_, ackSelect_1_);
not #(1) U73_0_(ackSelect_b_0_, ackSelect_0_);
not #(1) U72_2_(ackWselect_b_2_, ackWselect_2_);
not #(1) U72_1_(ackWselect_b_1_, ackWselect_1_);
not #(1) U72_0_(ackWselect_b_0_, ackWselect_0_);
ffB #(1) I99(ackWinOverD, rclk, ackWinOver);
ffB #(1) I92(ackClear, rclk, hnl_184);
ffB #(1) I96(ackWinOver, rclk, ackClear);
ffB #(1) I71(hnl_192, rclk, hnl_190);
ffB #(1) I70(hnl_190, rclk, mtclken_b);
ffB #(1) I69(mtclken_b, rclk, evalD);
ffB #(1) I68(evalD, rclk, eval);
mux41 #(1) I48(hnl_191, hnl_192, hnl_190, mtclken_b, evalD, ackSel_2_, ackSel_1_, ackSel_0_, ackSel_3_);
mux41 #(1) I39(hnl_185, hnl_193, hnl_194, hnl_195, hnl_196, ackWsel_0_, ackWsel_3_, ackWsel_2_, ackWsel_1_);
mux41 #(1) I38(hnl_186, hnl_197, hnl_198, hnl_192, hnl_190, ackWsel_0_, ackWsel_3_, ackWsel_2_, ackWsel_1_);
ffA I33(hnl_197, hnl_198, rclk);
ffA I37(hnl_193, hnl_194, rclk);
ffA I36(hnl_194, hnl_195, rclk);
ffA I35(hnl_195, hnl_196, rclk);
ffA I34(hnl_196, hnl_197, rclk);
ffA I32(hnl_198, hnl_192, rclk);
nor #(1) U124(hnl_181, ackWinOverD, reset);
nor #(1) U50_0_(ackSel_3_, ackSelect_b_0_, ackSelect_b_1_);
nor #(1) U50_1_(ackSel_2_, ackSelect_0_, ackSelect_b_1_);
nor #(1) U50_2_(ackSel_1_, ackSelect_b_0_, ackSelect_1_);
nor #(1) U50_3_(ackSel_0_, ackSelect_0_, ackSelect_1_);
not #(1) U134(hnl_182, hnl_187);
not #(1) U65(reset_b, reset);
endmodule

module mux71x (Y, A, B, C, D, E, F, G, SelA, SelB, SelC, SelD, SelE, SelF, SelG);
output Y;
input A, B, C, D, E, F, G, SelA, SelB, SelC, SelD, SelE, SelF, SelG;
supply1 vdd;
supply0 gnd;
not #(1) U13(hnl_199, hnl_200);
not #(1) U42(Y, hnl_199);
not (weak0,weak1) #(1) I41(hnl_200, hnl_199);
tranif1 N27(hnl_200, B, SelB);
tranif1 N31(hnl_200, F, SelF);
tranif1 U1(hnl_200, A, SelA);
tranif1 N28(hnl_200, C, SelC);
tranif1 N38(hnl_200, G, SelG);
tranif1 N30(hnl_200, E, SelE);
tranif1 N29(hnl_200, D, SelD);
endmodule

module u5NSWErg (NSWE, selectOdd, loadNSWE, pd2, pd3, rclk, unloadNSWE);
output NSWE, selectOdd;
input loadNSWE, pd2, pd3, rclk, unloadNSWE;
supply1 vdd;
supply0 gnd;
oai21A U106(hnl_201, hnl_202, loadNSWE, rclk);
ffBarB #(1) I103(hnl_202, rclk, hnl_203);
nor #(1) U101(hnl_203, unloadNSWE, loadNSWE);
not #(1) U95(slowGatedNSWEclk, hnl_204);
nand #(1) U93(hnl_205, vdd, vdd, hnl_206);
not #(1) U91(gatedNSWEclk, hnl_206);
not #(1) U86(clkSelectEven, hnl_201);
not #(1) U107(hnl_207, hnl_208);
not #(1) U98(hnl_209, loadNSWE);
not #(1) U94(hnl_204, hnl_205);
nand #(1) U84(hnl_206, selectOdd, rclk, hnl_202);
ffA I90(hnl_210, pd3, slowGatedNSWEclk);
ffA I89(hnl_211, pd2, slowGatedNSWEclk);
ffB #(1) I99(NSWE, rclk, hnl_207);
ffNcA I104(selectOdd, hnl_212, clkSelectEven);
ffNcA I71(hnl_192, hnl_210, slowGatedNSWEclk);
ffNcA I70(hnl_190, hnl_192, slowGatedNSWEclk);
ffNcA I69(oddNSWE_b, hnl_190, gatedNSWEclk);
ffNcA I68(evenNSWE_b, hnl_213, gatedNSWEclk);
ffNcA I67(hnl_213, hnl_214, slowGatedNSWEclk);
ffNcA I66(hnl_214, hnl_211, slowGatedNSWEclk);
nand #(1) U105(hnl_212, hnl_209, selectOdd);
mux21 #(1) I43(hnl_208, evenNSWE_b, oddNSWE_b, selectOdd);
endmodule

module nandpd2 (Y, A, B);
inout Y;
input A, B;
supply1 vdd;
supply0 gnd;
tranif1 N2(hnl_215, gnd, B);
tranif1 N1(Y, hnl_215, A);
endmodule

module u5DARbit (DAR, loadDAR, reset_b, setDAR, testBD);
output DAR;
input loadDAR, reset_b, setDAR, testBD;
supply1 vdd;
supply0 gnd;
not #(1) U36(DAR, hnl_216);
not #(1) U35(hnl_85, hnl_217);
not #(1) U34(hnl_218, loadDAR);
not #(1) U33(hnl_146, testBD);
mux21 #(1) I32(hnl_217, hnl_216, hnl_146, setDAR);
ffBNcRA I28(hnl_216, hnl_218, hnl_85, reset_b);
endmodule

module u5id (debug_1_, debug_0_, dataZA2, dataZA3, idhit, A2_b, A3_b, dataInA2, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID);
output debug_1_, debug_0_;
inout dataZA2, dataZA3, idhit;
input A2_b, A3_b, dataInA2, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID;
supply1 vdd;
supply0 gnd;
latRA #(1) I53(debug_1_, dataInA3, writeDeviceID, reset_b);
latRA #(1) I21(debug_0_, dataInA2, writeDeviceID, reset_b);
xnandpc2 U51(idhit, debug_1_, evalId, A3_b);
xnandpc2 U50(idhit, debug_0_, evalId, A2_b);
nandpd2 U48(dataZA3, debug_1_, readDeviceId);
nandpd2 U42(dataZA2, debug_0_, readDeviceId);
endmodule

module u5Rhit (bank0RowAddr, bank1RowAddr, dataZbank0, dataZbank1, rowHitLeft, rowHitRight, BSEL, evalRowHit, packetRowAddr, packetRowAddr_b, readR_10_, reset_b, updateRowAddr);
output bank0RowAddr, bank1RowAddr;
inout dataZbank0, dataZbank1, rowHitLeft, rowHitRight;
input BSEL, evalRowHit, packetRowAddr, packetRowAddr_b, readR_10_, reset_b, updateRowAddr;
supply1 vdd;
supply0 gnd;
latRB #(1) I55(bank1RowAddr, n2, updateRowAddr, reset_b);
latRB #(1) I54(bank0RowAddr, n1, updateRowAddr, reset_b);
not #(1) U50(hnl_219, BSEL);
xnandpc2 U42(rowHitRight, bank1RowAddr, evalRowHit, packetRowAddr_b);
xnandpc2 U41(rowHitLeft, bank0RowAddr, evalRowHit, packetRowAddr_b);
mux21s #(1) I49(n2, bank1RowAddr, packetRowAddr, BSEL, hnl_219);
mux21s #(1) I3(n1, packetRowAddr, bank0RowAddr, BSEL, hnl_219);
nandpd2 U45(dataZbank1, bank1RowAddr, readR_10_);
nandpd2 U44(dataZbank0, bank0RowAddr, readR_10_);
endmodule

module u5RASadr (adrSelReg, n1_b, packetRowaddr_b, dataZ01, dataIn01, pd12, pd23, readR_8_, reset_b, writeA0123, writeR_8_);
output adrSelReg, n1_b, packetRowaddr_b;
inout dataZ01;
input dataIn01, pd12, pd23, readR_8_, reset_b, writeA0123, writeR_8_;
supply1 vdd;
supply0 gnd;
nandpd2 U12(dataZ01, adrSelReg, readR_8_);
latRA #(1) I9(adrSelReg, dataIn01, writeR_8_, reset_b);
hitSel I26(packetRowaddr_b, n1_b, pd23, pd12, adrSelReg, writeA0123);
endmodule

module u5RfshRw (carryOut, rfshRASaddr, dataZ, carryIn, dataIn, incRfshRow_b, readR_5_, writeR_5_);
output carryOut, rfshRASaddr;
inout dataZ;
input carryIn, dataIn, incRfshRow_b, readR_5_, writeR_5_;
supply1 vdd;
supply0 gnd;
not #(1) I51(rfshRASaddr, hnl_220);
countup I47(carryOut, hnl_220, incRfshRow_b, carryIn, writeR_5_, dataIn);
nandpd2 U130(dataZ, rfshRASaddr, readR_5_);
endmodule

module u5CASdy1 (readDelay, writeDelay, dataZ1, dataZ3, dataIn1, dataIn3, readR_2_, reset_b, writeR_2_);
output readDelay, writeDelay;
inout dataZ1, dataZ3;
input dataIn1, dataIn3, readR_2_, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
latRB #(1) hnl_221(readDelay, dataIn1, writeR_2_, reset_b);
latRB #(1) hnl_222(writeDelay, dataIn3, writeR_2_, reset_b);
nandpd2 U1076(dataZ1, readDelay, readR_2_);
nandpd2 U1077(dataZ3, writeDelay, readR_2_);
endmodule

module pdnull (Y, A);
inout Y;
input A;
supply1 vdd;
supply0 gnd;
tranif1 N1(Y, gnd, gnd);
endmodule

module nandpd1 (Y, A);
inout Y;
input A;
supply1 vdd;
supply0 gnd;
tranif1 N1(Y, gnd, A);
endmodule

module u5MscR4 (ackDelay, ackWinDelay, dataZ0, dataZ1, dataZ2, dataZ3, autoSkip, dataIn0, dataIn2, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_2_);
output ackDelay, ackWinDelay;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input autoSkip, dataIn0, dataIn2, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
pdnull U157(dataZ1, readR_9_);
pdnull U156(dataZ0, readR_9_);
latRB #(1) I132(ackDelay, dataIn2, writeR_2_, reset_b);
latRB #(1) I127(ackWinDelay, dataIn0, writeR_2_, reset_b);
nandpd1 U140(dataZ3, readR_0_);
nandpd1 U139(dataZ0, readR_0_);
nandpd1 U125(dataZ1, readR_0_);
nandpd2 U158(dataZ0, autoSkip, readR_3_);
nandpd2 U133(dataZ2, ackDelay, readR_2_);
nandpd2 U128(dataZ0, ackWinDelay, readR_2_);
endmodule

module u5bit4 (ADR_3_, CASctCy45, Count_2_, DAR_3_, NSWE_4_, RAScountLSB_b, RfshRwCy45, XferCntBorw45, ackDelay_1_, ackWinDelay_1_, partialId_b_2_, pd2_4_, readDelay_1_, skip, writeDelay_1_,
xcnt_b_0_, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, idHitB, rowHitLeftB, rowHitRightB, CASctCy34, DAmode_b, DLLByPassMode_b, NSAdr_3_, RASaddrEnable, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_,
RASsel_0_, RfshRwCy34, autoSkip, autoSkipEn, dataIn0_4_, dataIn1_4_, dataIn2_4_, dataIn3_4_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b,
incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_1_, pd0_4_, pd1_4_, pd2_5_, pd3_4_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset,
restoreBank0, restoreBank1, setDAR, skipBit, testBD_5_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_6_, writeR_5_, writeR_2_, writeR_1_);
output ADR_3_, CASctCy45, Count_2_, DAR_3_, NSWE_4_, RAScountLSB_b, RfshRwCy45, XferCntBorw45, ackDelay_1_, ackWinDelay_1_, partialId_b_2_, pd2_4_, readDelay_1_, skip, writeDelay_1_, xcnt_b_0_;
inout dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, idHitB, rowHitLeftB, rowHitRightB;
input CASctCy34, DAmode_b, DLLByPassMode_b, NSAdr_3_, RASaddrEnable, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy34, autoSkip, autoSkipEn, dataIn0_4_, dataIn1_4_, dataIn2_4_,
dataIn3_4_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_1_, pd0_4_, pd1_4_, pd2_5_, pd3_4_,
rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, skipBit, testBD_5_, unloadNSWE, updateRowAddr, writeA45,
writeA0123, writeA0123x, writeR_8_, writeR_6_, writeR_5_, writeR_2_, writeR_1_;
supply1 vdd;
supply0 gnd;
nand #(1) U588(hnl_223, hnl_224, DLLByPassMode_b);
latSRB rowExpRest0(rowExpRest_0_, dataIn3_4_, writeR_6_, vdd, reset);
latSRB rowImpRest0(rowImpRest_0_, dataIn2_4_, writeR_6_, vdd, reset);
latSRB rowAcc0(rowAcc_0_, dataIn1_4_, writeR_6_, reset_b, gnd);
latSRB rowPre0(rowPre_0_, dataIn0_4_, writeR_6_, reset_b, gnd);
ltxBarB Count2(Count_b_2_, writeA45, pd2_4_);
ltxBarB Addr31(Addr_31_, writeA0123, pd3_4_);
latBNcA I582(packetRowAddr_3_, RASaddrEnable, packetRowAddr_b_3_);
mux71x AdrMUX3(ADR_3_, ColAdr_3_, NSAdr_3_, packetRowAddr_3_, rfshRowAddr_3_, bank0RowAddr_3_, bank1RowAddr_3_, testBD_5_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_225, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg4(NSWE_4_, selectEven_4_, loadNSWE, pd2_4_, pd3_4_, rclk, unloadNSWE);
not #(1) I576(DAmode, DAmode_b);
nor #(1) I572(hnl_225, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U569(skip, hnl_223);
mux21 #(1) I567(hnl_224, skipBit, autoSkip, autoSkipEn);
not #(1) U562(RAScountLSB_b, RAScountLSB);
not #(1) U561(Count_2_, Count_b_2_);
mux41 #(1) I560(cnt0, rowPre_0_, rowAcc_0_, rowImpRest_0_, rowExpRest_0_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
latBarA RASct0(RAScountLSB, RASldCount, cnt0);
nandpd2 U559(dataZ3_4_, rowExpRest_0_, readR_6_);
nandpd2 U551(dataZ0_4_, rowPre_0_, readR_6_);
nandpd2 U541(dataZ1_4_, rowAcc_0_, readR_6_);
nandpd2 U539(dataZ2_4_, rowImpRest_0_, readR_6_);
u5DARbit DARbit3(DAR_3_, loadDAR, DAmode, setDAR, testBD_5_);
countdn Count3(XferCntBorw45, xcnt_b_0_, decXferCnt_b, gnd, writeA45, pd3_4_);
countup Col_3_(CASctCy45, net1718, incColAdr_b, CASctCy34, writeA0123x, pd0_4_);
u5id Id22_31(id_31_, id_22_, dataZ0_4_, dataZ2_4_, idHitB, partialId_b_1_, Addr_31_, dataIn0_4_, dataIn2_4_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_3_(bank0RowAddr_3_, bank1RowAddr_3_, dataZ0_4_, dataZ2_4_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_3_, packetRowAddr_b_3_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr3(adrSelReg_3_, partialId_b_2_, packetRowAddr_b_3_, dataZ0_4_, dataIn0_4_, pd1_4_, pd2_5_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw3(RfshRwCy45, rfshRowAddr_3_, dataZ0_4_, RfshRwCy34, dataIn0_4_, incRfshRow_b, readR_5_, writeR_5_);
u5CASdy1 CASdy1(readDelay_1_, writeDelay_1_, dataZ1_4_, dataZ3_4_, dataIn1_4_, dataIn3_4_, readR_2_, reset_b, writeR_2_);
u5MscR4 MscR4(ackDelay_1_, ackWinDelay_1_, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, autoSkip, dataIn0_4_, dataIn2_4_, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_2_);
not #(1) U498(ColAdr_3_, net1718);
not #(1) U493(reset_b, reset);
endmodule

module spdt1 (s1, s2);
inout s1;
input s2;
supply1 vdd;
supply0 gnd;
endmodule

module u5CAScyc (CAS, CASstate1_b, CASstate3_buf, CASwrite, LoadShiftRegister_b, WML, WRITE, decXferCnt_b, earlyREQinhibit, firstCycWE_b, incColAdr_b, loadLast, loadNSAdr, preloadNSWE, selRegData,
startNSAdr_b, trueCASstate1_b, unloadNSWE, writeD0123, writeD4567, writeSenseAmpPipe, CASenable, DAWD0123, DAWD4567, DAmode_b, NSOp, REQinhibiten, TestCAS, TestRASB, TestWML, TestWRITE, WPBNP,
abortOperation_b, earlyDone, inhLoadLast_b, killFirstCycle_b, localREQ, rclk, regOp, reset, standby, startCycle_b, virtuallyDone, writeA45, writeMaskedNSOp_b, writeOp_b);
output CAS, CASstate1_b, CASstate3_buf, CASwrite, LoadShiftRegister_b, WML, WRITE, decXferCnt_b, earlyREQinhibit, firstCycWE_b, incColAdr_b, loadLast, loadNSAdr, preloadNSWE, selRegData,
startNSAdr_b, trueCASstate1_b, unloadNSWE, writeD0123, writeD4567, writeSenseAmpPipe;
input CASenable, DAWD0123, DAWD4567, DAmode_b, NSOp, REQinhibiten, TestCAS, TestRASB, TestWML, TestWRITE, WPBNP, abortOperation_b, earlyDone, inhLoadLast_b, killFirstCycle_b, localREQ, rclk, regOp,
reset, standby, startCycle_b, virtuallyDone, writeA45, writeMaskedNSOp_b, writeOp_b;
supply1 vdd;
supply0 gnd;
ffBNcB I653(resetCnt, CASstate2_b, cnt8_b);
latBNcC I875(hnl_226, rclk, hnl_227);
latBNcC I835(hnl_228, rclk, hnl_229);
latRB #(1) I691(latchedSelReg, regOp, firstCycle, hnl_230);
ffD I856(decXferCnt_b, trueCASstate1_b, rclk);
nand #(0) U853(hnl_231, CASenable, hnl_232, hnl_233, REQinhibiten);
ffBNcD I844(preloadNSWE, rclk, hnl_234);
ffC #(1) I850(loadLast, rclk, preLoadLast);
ffC #(1) I842(incColAdr, rclk, hnl_235);
ffBarA #(1) I831(hnl_236, rclk, hnl_237);
aoi21A #(1) U864(earlyFC_b, hnl_238, CASstate2_b, writeA45);
aoi21A #(1) U832(hnl_237, WPBNP_b, loadMask, firstCycleD);
aoi21A #(1) U830(hnl_239, hnl_240, WPBNP, hnl_236);
ffBarB #(1) I807(preinhibitCount, rclk, hnl_239);
ffBarB #(1) I816(loadNSAdr_b, rclk, preLoadNSaddr);
not #(1) I817(CASstate3_buf, CASstate3_b);
nand #(1) I809(hnl_232, firstCycle_b, CASstate2);
invEE U860(writeD0123, hnl_226);
invEE U841(incColAdr_b, incColAdr);
invEE U797(writeD4567, hnl_228);
latBarSB #(1) I790(hnl_241, preWriteSenseAmpPipe_b, rclk, hnl_242);
oai21A U734(preCASstate1, CASenable_b, hnl_243, hnl_244);
not #(1) U595(writeMaskedNSOp, writeMaskedNSOp_b);
not #(1) U695(writeOp, writeOp_b);
not #(1) U702(LoadShiftRegister_b, preLoadSR);
not #(1) U752(unloadNSWE, hnl_245);
latB I854(preCASwrite_b, hnl_246, rclk);
spdt1 I686(CASstate2_b, CASstate1_b);
spdt1 I684(CASstate3, CASstate2);
ffBarA #(1) I829(hnl_240, rclk, NScnt_0_);
ffBarA #(1) I784(preFirstCycWE, rclk, inhibitFirstWriteCycle_b);
ffBarA #(1) I683(wrtPipeD, rclk, preWriteSenseAmpPipe_b);
ffBarC #(1) I776(CASstate4, rclk, CASstate3_b);
ffQBC I529(firstCycle_b, firstCycle, earlyFC_b, rclk);
ffQBC I716(CASstate2_b, CASstate2, hnl_247, rclk);
ffQBC I655(CASstate1, CASstate1_b, preCASstate1, rclk);
ffBarB #(1) I705(firstWPBNPcycle_b, rclk, hnl_248);
nor #(1) U768(hnl_235, preIncColAdr_b, WPBNPinh);
nor #(1) U737(hnl_249, hnl_250, CASstate1);
nor #(1) U731(hnl_251, hnl_252, hnl_253);
nor #(1) U638(resetNScnt_b, resetCnt, firstCycle);
invEEbuf U722(writeSenseAmpPipe, hnl_254);
invEEbuf U643(selRegData, hnl_255);
invEEbuf U637(WML, WML_b);
invEEbuf U636(CAS, CAS_b);
ffBNcA I624(hnl_256, CASstate0or4_b, hnl_257);
aoi21A #(1) U847(hnl_258, startCycle_b, CASstate4_b, inhLoadLast);
aoi21A #(1) U729(hnl_252, WPBNP_b, writeMaskedNSOp_b, inhibitCount_b);
aoi21A #(1) U760(loadNSWEmask, firstCycle_b, loadMask_b, writeMaskedNSOp_b);
ffA I756(maskedNSHoldOff, loadNSWEmask, rclk);
nor #(1) U524(preLoadSR, CASstate2_b, DAmode, writeOp);
nor #(1) U780(hnl_259, writeOp_b, regOp, DAmode);
nor #(1) U767(hnl_260, earlyDone, NSOp, CASstate2_b);
nor #(1) U669(DAinhibit, hnl_261, TestRASB, DAmode_b);
nor #(1) U603(maskedNSclkEn, CASstate3_b, writeMaskedNSOp_b, maskedNSHoldOff);
nor #(1) U567(hnl_257, NScnt_2_, NScnt_1_, NScnt_0_);
oai21A U696(hnl_248, hnl_158, firstWPBNPcycle_b, hnl_262);
not #(1) U852(earlyREQinhibit, hnl_231);
not #(1) U753(hnl_245, maskedNSclkEn);
not #(1) U746(CASstate0or4, CASstate0or4_b);
not #(1) U700(hnl_262, writeA45);
not #(1) U693(regOp_b, regOp);
not #(1) U660(WPBNP_b, WPBNP);
not #(1) U521(reset_b, reset);
nor #(1) I791(hnl_254, hnl_241, wrtPipeD);
nor #(1) I745(CASstate0or4_b, CASstate0, CASstate4);
nor #(1) I701(firstCycWE_b, preFirstCycWE, hnl_263);
ffQBB I834(loadMask_b, loadMask, preloadMask_b, rclk);
ffQBB I808(inhibitCount, inhibitCount_b, preinhibitCount, rclk);
ffQBB I765(firstCycleD_b, firstCycleD, firstCycle_b, rclk);
ffQBB I739(CASstate0_b, CASstate0, startCycle_b, rclk);
ffQBB I495(CASstate3, CASstate3_b, CASstate2, rclk);
ffBNcRA I486(NScnt_2_, NScnt_1_, NScnt_2_, resetNScnt_b);
ffBNcRA I485(NScnt_1_, NScnt_0_, NScnt_1_, resetNScnt_b);
ffBNcRA I484(NScnt_0_, CASstate0or4_b, NScnt_0_, resetNScnt_b);
not #(1) I662(loadNSAdr, loadNSAdr_b);
not #(1) U471(WRITE, write_b);
mux21 #(1) I838(preLoadLast, hnl_258, hnl_264, writeOp);
mux21 #(1) I824(hnl_253, hnl_265, regOp, firstCycleD_b);
mux21 #(1) I810(hnl_233, preinhibitCount, inhibitCount, writeMaskedNSOp);
mux21 #(1) I743(hnl_266, CASstate0_b, startCycle_b, writeOp_b);
mux21 #(1) I740(hnl_243, CASstate0_b, startCycle_b, writeOp_b);
nand #(1) U871(hnl_267, firstCycle, killFirstCycle_b, reset_b);
nand #(1) U815(hnl_247, CASstate1, reset_b, abortOperation_b);
nand #(1) U774(hnl_268, CASstate0or4, writeOp, hnl_269);
nand #(1) U773(hnl_270, writeOp, CASstate2, hnl_269);
nand #(1) U772(preWML_b, CASWMLen, inhibit1stMemWriteCyc_b, WPBNPinh);
nand #(1) U659(cnt8_b, hnl_257, WPBNP_b, hnl_256);
nand #(1) U877(trueCASstate1_b, inhibitFirstWriteCycle_b, CASstate1, hnl_271);
nand #(1) U497(hnl_255, latchedSelReg, hnl_230, DAmode_b);
nand #(1) U826(trueCASstate1_b, inhibitFirstWriteCycle_b, CASstate1, hnl_271);
nand #(1) U738(startNSAdr_b, CASstate2, NSOp, inhibitFirstWriteCycle_b);
nand #(1) U420(preCAS_b, CASWMLen, hnl_251, CASenable);
nor #(1) I771(WPBNPinh, inhibitCount_b, WPBNP_b);
nor #(1) I411(CASwrite, CASstate2_b, preCASwrite_b);
not #(1) U876(hnl_227, writeD0123_b);
not #(1) U803(hnl_229, preWriteD4567_b);
not #(1) U490(write_b, hnl_272);
nor #(1) U849(hnl_264, inhLoadLast, CASstate1_b);
nor #(1) U837(hnl_242, hnl_273, rclk);
nor #(1) U777(hnl_274, inhibitCount_b, writeMaskedNSOp_b);
nor #(1) U770(preLoadNSaddr, NSOp_b, CASstate1_b);
nor #(1) U706(hnl_263, WPBNP_b, firstWPBNPcycle_b);
nor #(1) U703(hnl_158, firstCycleD, CASstate3_b);
not #(1) U735(hnl_250, hnl_244);
DAff I251(CAS_b, rclk, DAinhibit, preCAS_b, DAmode_b);
DAff I342(WML_b, rclk, TestWML, preWML_b, DAmode_b);
DAff I287(writeD0123_b, rclk, DAWD0123, hnl_268, DAmode_b);
DAff I263(preWriteD4567_b, rclk, DAWD4567, hnl_270, DAmode_b);
nand #(1) U822(hnl_265, regOp_b, writeOp_b);
nand #(1) U788(preWriteSenseAmpPipe_b, writeOp_b, CASstate3);
nand #(1) U775(hnl_269, regOp, inhibitFirstWriteCycle_b);
nand #(1) U720(hnl_246, localREQ, hnl_259);
nand #(1) U690(stopCAS_b, inhibitFirstWriteCycle_b, virtuallyDone);
nand #(1) U689(hnl_244, CASstate4, stopCAS_b);
nand #(1) U645(preIncColAdr_b, hnl_260, inhibit1stMemWriteCyc_b);
not #(1) U870(hnl_238, hnl_267);
not #(1) U867(hnl_230, standby);
not #(1) U848(CASstate4_b, CASstate4);
not #(1) U846(inhLoadLast, inhLoadLast_b);
not #(1) U836(hnl_273, DAinhibit);
not #(1) U827(hnl_271, hnl_274);
not #(1) U823(inhibit1stMemWriteCyc_b, hnl_253);
not #(1) U781(DAmode, DAmode_b);
not #(1) U736(CASenable_b, CASenable);
not #(1) U670(hnl_261, TestCAS);
not #(1) U563(NSOp_b, NSOp);
not #(1) U496(Wn1, TestWRITE);
nand #(1) U863(hnl_234, preloadMask_b, earlyFC_b);
nand #(1) U733(CASWMLen, hnl_266, hnl_249);
nand #(1) U336(hnl_272, preCASwrite_b, Wn1);
nand #(1) U865(preloadMask_b, resetCnt, writeMaskedNSOp);
nand #(1) U449(inhibitFirstWriteCycle_b, firstCycleD, writeOp);
endmodule

module u5RegDec (framePulseX, readR_10_, readR_9_, readR_8_, readR_7_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_3_, writeR_2_,
writeR_1_, ADR_6_, ADR_2_, ADR_1_, ADR_0_, Addr_2_, PDMD, framePulse_b, reset, selRegData, writeD4567);
output framePulseX, readR_10_, readR_9_, readR_8_, readR_7_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_3_, writeR_2_, writeR_1_;
input ADR_6_, ADR_2_, ADR_1_, ADR_0_, Addr_2_, PDMD, framePulse_b, reset, selRegData, writeD4567;
supply1 vdd;
supply0 gnd;
nor #(1) F94DK(hnl_275, gnd, gnd);
nand #(1) U49(framePulseX, framePulse_b, hnl_276);
nand #(1) U44(hnl_277, hnl_278, selRegData);
not #(1) F94DJ(hnl_279, gnd);
not #(1) U43_0_(ADRB_1_, ADR_b_1_);
not #(1) U43_1_(ADRB_0_, ADR_b_0_);
not #(1) U52(hnl_276, reset);
not #(1) U45(hnl_278, PDMD);
not #(1) U35(hnl_85, writeD4567);
not #(1) U42(selRegDataB, hnl_277);
not #(1) U36(writeD4567B, hnl_85);
not #(1) U34(Addr_b_2_, Addr_2_);
not #(1) U32_0_(ADR_b_2_, ADR_2_);
not #(1) U32_1_(ADR_b_1_, ADR_1_);
not #(1) U32_2_(ADR_b_0_, ADR_0_);
not #(1) U33_0_(readR_10_, net144_0_);
not #(1) U33_1_(readR_9_, net144_1_);
not #(1) U33_2_(readR_8_, net144_2_);
not #(1) U33_3_(readR_7_, net144_3_);
not #(1) U33_4_(readR_6_, net144_4_);
not #(1) U33_5_(readR_5_, net144_5_);
not #(1) U33_7_(readR_3_, net144_6_);
not #(1) U33_8_(readR_2_, net144_7_);
not #(1) U33_9_(readR_1_, net144_8_);
not #(1) U33_10_(readR_0_, net144_9_);
not #(1) U30_0_(writeR_8_, net143_0_);
not #(1) U30_1_(writeR_7_, net143_1_);
not #(1) U30_2_(writeR_6_, net143_2_);
not #(1) U30_3_(writeR_5_, net143_3_);
not #(1) U30_5_(writeR_3_, net143_4_);
not #(1) U30_6_(writeR_2_, net143_5_);
not #(1) U30_7_(writeR_1_, net143_6_);
nand #(0) U4_0_(net142_0_, ADR_6_, ADR_b_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_1_(net142_1_, Addr_2_, ADR_b_0_, ADR_b_1_, ADR_2_);
nand #(0) U4_2_(net142_2_, Addr_b_2_, ADR_b_0_, ADR_b_1_, ADR_2_);
nand #(0) U4_3_(net142_3_, Addr_2_, ADRB_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_4_(net142_4_, Addr_b_2_, ADRB_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_5_(net142_5_, Addr_2_, ADR_b_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_6_(net142_6_, Addr_b_2_, ADR_b_0_, ADRB_1_, ADR_b_2_);
nand #(0) U4_7_(net142_7_, Addr_2_, ADRB_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_8_(net142_8_, Addr_b_2_, ADRB_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_9_(net142_9_, lsbx, ADR_b_0_, ADR_b_1_, ADR_b_2_);
nand #(0) U4_10_(net142_10_, lsbx_b, ADR_b_0_, ADR_b_1_, ADR_b_2_);
nor #(1) U27(lsbx, ADR_6_, Addr_b_2_);
nor #(1) U28(lsbx_b, ADR_6_, Addr_2_);
not #(1) U16_0_(sel_10_, net142_0_);
not #(1) U16_1_(sel_9_, net142_1_);
not #(1) U16_2_(sel_8_, net142_2_);
not #(1) U16_3_(sel_7_, net142_3_);
not #(1) U16_4_(sel_6_, net142_4_);
not #(1) U16_5_(sel_5_, net142_5_);
not #(1) U16_6_(sel_4_, net142_6_);
not #(1) U16_7_(sel_3_, net142_7_);
not #(1) U16_8_(sel_2_, net142_8_);
not #(1) U16_9_(sel_1_, net142_9_);
not #(1) U16_10_(sel_0_, net142_10_);
nand #(1) F94DI(hnl_280, gnd, gnd);
nand #(1) F94DH(hnl_281, gnd, gnd);
nand #(1) U8_0_(net144_0_, sel_10_, selRegDataB);
nand #(1) U8_1_(net144_1_, sel_9_, selRegDataB);
nand #(1) U8_2_(net144_2_, sel_8_, selRegDataB);
nand #(1) U8_3_(net144_3_, sel_7_, selRegDataB);
nand #(1) U8_4_(net144_4_, sel_6_, selRegDataB);
nand #(1) U8_5_(net144_5_, sel_5_, selRegDataB);
nand #(1) U8_7_(net144_6_, sel_3_, selRegDataB);
nand #(1) U8_8_(net144_7_, sel_2_, selRegDataB);
nand #(1) U8_9_(net144_8_, sel_1_, selRegDataB);
nand #(1) U8_10_(net144_9_, sel_0_, selRegDataB);
nand #(1) U218_0_(net143_0_, writeD4567B, readR_8_);
nand #(1) U218_1_(net143_1_, writeD4567B, readR_7_);
nand #(1) U218_2_(net143_2_, writeD4567B, readR_6_);
nand #(1) U218_3_(net143_3_, writeD4567B, readR_5_);
nand #(1) U218_5_(net143_4_, writeD4567B, readR_3_);
nand #(1) U218_6_(net143_5_, writeD4567B, readR_2_);
nand #(1) U218_7_(net143_6_, writeD4567B, readR_1_);
endmodule

module u5clkCtl (bcastWrite, runtclk, CASenable, DLLByPassMode_b, bcastWriteA, bcastWriteB, busyError_b, preCycState5, reset, tclkDisable_b, writeOp_b);
output bcastWrite, runtclk;
input CASenable, DLLByPassMode_b, bcastWriteA, bcastWriteB, busyError_b, preCycState5, reset, tclkDisable_b, writeOp_b;
supply1 vdd;
supply0 gnd;
nand #(0) U130(hnl_282, preCycState5, busyError_b, CASenable, writeOp_b);
not #(1) U129(bcastWrite, hnl_283);
nand #(1) U128(hnl_283, bcastWriteA, bcastWriteB);
srff I116(enableTclk_b, tclkDisable_b, hnl_282);
nor #(1) U104(forceRuntclk_b, hnl_204, reset);
nand #(1) I99(runtclk, forceRuntclk_b, enableTclk_b);
not #(1) U94(hnl_204, DLLByPassMode_b);
endmodule

module aoi22A (Y, A1, A2, B1, B2);
output Y;
input A1, A2, B1, B2;
supply1 vdd;
supply0 gnd;
tranif0 P4(hnl_284, vdd, B2);
tranif0 P3(hnl_284, vdd, B1);
tranif0 P2(Y, hnl_284, A2);
tranif0 P1(Y, hnl_284, A1);
tranif1 N3(Y, hnl_285, B1);
tranif1 N1(Y, hnl_215, A1);
tranif1 N4(hnl_285, gnd, B2);
tranif1 N2(hnl_215, gnd, A2);
endmodule

module nandpc2 (Y, A, PC);
inout Y;
input A, PC;
supply1 vdd;
supply0 gnd;
tranif0 P1(Y, vdd, PC);
tranif1 N1(Y, hnl_215, A);
tranif1 N2(hnl_215, gnd, PC);
endmodule

module u5HitLog (CASenable, RASkill, RASstate4, bcastWrite_b, idHitRowMiss, idHit_b, idMissReturn_b, killFirstCycle_b, latchAbort_b, nack, packetIdHit, regOp_b, RASidle_b, abortOperation_b, ackClear,
bcastWrite, busyError_b, eval, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, preCycState5, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, updateRowAddr, writeA45, writeA45_b,
writeA0123);
output CASenable, RASkill, RASstate4, bcastWrite_b, idHitRowMiss, idHit_b, idMissReturn_b, killFirstCycle_b, latchAbort_b, nack, packetIdHit, regOp_b;
input RASidle_b, abortOperation_b, ackClear, bcastWrite, busyError_b, eval, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, preCycState5, rclk, regOp, reset, row0hitA, row0hitB, row1hitA,
row1hitB, updateRowAddr, writeA45, writeA45_b, writeA0123;
supply1 vdd;
supply0 gnd;
not #(1) U497(latchAbort_b, hnl_286);
latRBNcA I460(hnl_286, abortOperation_b, preCycState4, hnl_287);
latBarA I435(hnl_288, writeA45, rowMiss);
ffBarB #(1) I485(killFirstCycle_b, rclk, hnl_289);
aoi21A #(1) U477(hnl_290, rowMiss, regOp_b, idHit_b);
nor #(1) I478(hnl_291, hnl_290, bcastWrite);
nand #(1) U472(hnl_292, idHitA, idHitB, rowMiss);
nor #(1) U471(hnl_293, writeA45_b, regOp, RASidle_b);
ffC #(1) I470(RASstate4, rclk, hnl_293);
aoi22A U494(rowMiss, row0hitA, row0hitB, row1hitA, row1hitB);
aoi22A U469(rowMiss, row0hitA, row0hitB, row1hitA, row1hitB);
ffB #(1) I463(preCycState4, rclk, writeA45);
nand #(1) U458(RASkill, hnl_294, latchAbort_b, nackNoAction_b);
ffA I439(ackClearD, ackClear, rclk);
latBarB I434(packetIdHit, writeA45, idHit_b);
nor #(1) U420(hnl_295, bcastWrite, hnl_296, hnl_297);
aoi21A #(1) U412(hnl_298, nackNoAction_b, hnl_299, writeA0123);
ffBarA #(1) I413(nackNoAction_b, rclk, hnl_298);
nor #(1) U426(hnl_297, packetRowHit_b, packetIdHit_b);
nor #(1) U425(hnl_296, regOp_b, packetIdHit_b);
nor #(1) U440(hnl_287, writeA0123, ackClearD);
nor #(1) U406(invalidate_b, powerDownMode, reset);
srff I405(row0valid_b, invalidate_b, hnl_300);
srff I404(row1valid_b, invalidate_b, hnl_301);
nand #(1) U476(hnl_302, idHitRowMiss, RASstate4);
nand #(1) U408(hnl_300, updateRowAddr, hnl_303);
nand #(1) U407(hnl_301, updateRowAddr, packetBSELx);
not #(1) U473(idHitRowMiss, hnl_292);
not #(1) U379(CASenable, hnl_295);
latWA U374(idHitA, hnl_304);
latWA U373(idHitB, hnl_305);
latWA U372(row0hitA, hnl_306);
latWA U371(row1hitA, hnl_307);
latWA U370(row1hitB, hnl_308);
latWA U369(row0hitB, hnl_309);
nand #(1) U483(hnl_289, hnl_302, hnl_137);
nand #(1) I299(hnl_294, packetIdHit_b, bcastWrite_b);
nand #(1) U457(hnl_299, preCycState4, hnl_291, hnl_302);
nand #(1) I261(CAS_OK, packetRowHit_b, regOp_b, bcastWrite_b);
nandpc2 U377(row0hitA, packetBSEL, eval);
nandpc2 U375(row1hitA, hnl_310, eval);
nandpc2 U359(row0hitA, row0valid_b, eval);
nandpc2 U352(row1hitA, row1valid_b, eval);
nand #(1) U481(hnl_137, idHit_b, preCycState5, bcastWrite_b);
nand #(1) U301(idMissReturn_b, RASkill, ackClear, busyError_b);
not #(1) U446(bcastWrite_b, bcastWrite);
not #(1) U418(hnl_310, packetBSEL);
not #(1) U350(hnl_303, packetBSELx);
nand #(1) U495(idHit_b, idHitA, idHitB);
nand #(1) U437(idHit_b, idHitA, idHitB);
nand #(1) U382(nack, busyError_b, CAS_OK);
not #(1) U496(packetRowHit_b, hnl_288);
not #(1) U450(regOp_b, regOp);
not #(1) U422(packetIdHit_b, packetIdHit);
endmodule

module invFF (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) U9(Y, A);
endmodule

module u5PreCyc (REQ, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idle, localREQ, virtuallyDone, writeA45, prewriteA45, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b,
NSOp, PDMD, RASreturn_b, RASstate4, RefreshReturn_b, TestRASB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitRowMiss, idMissReturn_b, preCycState5, rclk, regOp, reset, reset_b,
startNSAdr_b, writeOp_b);
output REQ, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idle, localREQ, virtuallyDone, writeA45, prewriteA45, writeA0123, writeA0123x;
input AUXorPDcycle, AUXpending_b, DAmode_b, NSOp, PDMD, RASreturn_b, RASstate4, RefreshReturn_b, TestRASB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitRowMiss, idMissReturn_b,
preCycState5, rclk, regOp, reset, reset_b, startNSAdr_b, writeOp_b;
supply1 vdd;
supply0 gnd;
nand #(1) U646(preDriveColAdr, earlyREQ_b, regOp_b);
nand #(1) U701(earlyREQ_b, hnl_311, hnl_262, hnl_312);
aoi21A #(1) U700(hnl_262, RASstate4, idHitRowMiss, goIdle);
nand #(0) I489(hnl_59, idMissReturn_b, RASreturn_b, RefreshReturn_b, reset_b);
latB I704(writeOpD2_b, writeOp_b, preCycState5);
nand #(1) U632(hnl_311, state2x_b, earlyREQ_b);
nand #(1) U702(hnl_313, virtuallyDone, hnl_314);
ffBarA #(1) I574(hnl_314, rclk, virtuallyDone);
ffBarD I606(preevalR, rclk, localframePulse_b);
ffBarD I603(preevalL, rclk, localframePulse_b);
not #(1) U697(frameEnableX_b, frameEnableX);
not #(1) U692(state2x_b, state2x);
not #(1) U691(state2x, writeA0123x_b);
aoi211A #(1) I681(clearDriveColAdr_b, idHitRowMiss, RASstate4, AUXorPDcycle, hnl_315);
ffB #(1) I629(localREQ_b, rclk, earlyREQ_b);
ffB #(1) I639(goIdle, rclk, hnl_59);
ffB #(1) I581(virtuallyDone, rclk, earlyDone);
aoi22A U707(hnl_312, hnl_316, writeOpD2_b, earlyDone, hnl_317);
aoi22A U675(hnl_312, hnl_316, writeOpD2_b, earlyDone, hnl_317);
nor #(1) U638(hnl_318, earlyDone, goIdle);
nor #(1) I669(busy_b, hnl_319, hnl_320);
ffBNcD I654(prewriteA45, rclk, state2x);
ffBNcD I534(prewriteA0123, rclk, localframePulse);
ffBNcD I535(writeA0123x_b, rclk, hnl_321);
oai21A U699(hnl_162, frameEnableX_b, frameRaw_b, busyError_b);
ffBarRA I642(preDriveNSAdr, rclk, hnl_134, hnl_322);
not #(1) U651(hnl_323, hnl_324);
not #(1) U645(preDriveNSAdr_b, preDriveNSAdr);
not #(1) U634(REQ_b, hnl_325);
ffRA I672(hnl_326, rclk, reset_b, hnl_162);
ffRA I631(hnl_324, rclk, clearDriveColAdr_b, preDriveColAdr);
not #(1) U649(hnl_315, hnl_134);
invEEbuf U566(REQ, REQ_b);
invFF U604(evalR, preevalR);
invFF U600(evalL, preevalL);
invFF U564(writeA0123, prewriteA0123);
invFF U563(writeA0123x, writeA0123x_b);
invEE U652(driveColAdr, hnl_323);
invEE I498(writeA45, prewriteA45);
invEE U526(driveNSAdr, preDriveNSAdr_b);
ffQBB I666(hnl_319, idle, idleEarly_b, rclk);
nand #(1) U693(localframePulse_b, hnl_327, frameEnableX);
nand #(1) U688(hnl_328, frameEnableX, AUXpending_b);
nand #(1) U673(busyError_b, hnl_326, prewriteA45);
DAff I492(hnl_325, rclk, hnl_329, hnl_330, DAmode_b);
mux21 #(1) I477(idleEarly_b, hnl_318, hnl_331, busy_b);
oai21A U515(hnl_134, hnl_332, preDriveNSAdr, state2x_b);
not #(1) U445(localREQ, localREQ_b);
nor #(1) U695(localframePulse, frameRaw_b, frameEnableX_b);
nor #(1) U677(hnl_317, writeOpD2_b, virtuallyDone);
nor #(1) U517(hnl_332, startNSAdr_b, NSOp_b);
nor #(1) U536(hnl_321, frameRaw_b, hnl_328, idleEarly_b);
nor #(1) U636(hnl_330, earlyREQ_b, earlyREQinhibit);
nor #(1) U643(hnl_322, localREQ_b, DAmode);
nor #(1) U637(hnl_331, reset, evalL);
nor #(1) U493(hnl_107, TestRASB, PDMD);
not #(1) U687(hnl_320, AUXpending_b);
not #(1) U694(hnl_327, frameRaw_b);
not #(1) U647(regOp_b, regOp);
not #(1) U644(DAmode, DAmode_b);
not #(1) U640(hnl_329, hnl_107);
not #(1) U511(NSOp_b, NSOp);
ffBarB #(1) I576(hnl_316, rclk, hnl_313);
endmodule

module u5PreHit (CASenable, RASkill, RASstate4, REQ, bcastWrite, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idHitRowMiss, idle, killFirstCycle_b, latchAbort, latchAbort_b, localREQ, nack,
pwrdnRcvrs, runtclk, virtuallyDone, writeA45, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b, DLLByPassMode_b, NSOp, PDMD, RASidle_b, RASreturn_b, RcvrsOff_b, RefreshReturn_b,
TestRASB, abortOperation_b, ackClear, bcastWriteA, bcastWriteB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, preCycState5, rawBE_b,
rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, startNSAdr_b, tclkDisable_b, updateRowAddr, writeOp_b);
output CASenable, RASkill, RASstate4, REQ, bcastWrite, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idHitRowMiss, idle, killFirstCycle_b, latchAbort, latchAbort_b, localREQ, nack, pwrdnRcvrs,
runtclk, virtuallyDone, writeA45, writeA0123, writeA0123x;
input AUXorPDcycle, AUXpending_b, DAmode_b, DLLByPassMode_b, NSOp, PDMD, RASidle_b, RASreturn_b, RcvrsOff_b, RefreshReturn_b, TestRASB, abortOperation_b, ackClear, bcastWriteA, bcastWriteB,
earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, preCycState5, rawBE_b, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB,
startNSAdr_b, tclkDisable_b, updateRowAddr, writeOp_b;
supply1 vdd;
supply0 gnd;
nand #(1) F94DG(hnl_333, gnd, gnd);
latB F94DF(hnl_334, gnd, gnd);
aoi21A #(1) U704(hnl_335, setLatch_b, hnl_313, hnl_158);
aoi21A #(1) U701(hnl_335, setLatch_b, hnl_313, hnl_158);
nand #(0) U696(hnl_248, REQ, packetIdHit, NSOp, abortOperation_b);
latBarSB #(1) I692(hnl_336, hnl_337, hnl_262, hnl_338);
not #(1) U703(hnl_158, RcvrsOff_b);
not #(1) U702(hnl_313, hnl_336);
not #(1) U700(hnl_262, hnl_162);
not #(1) U698(hnl_171, rawBE_b);
not #(1) U695(hnl_339, writeOp_b);
nand #(1) U686(hnl_337, hnl_327, hnl_339, hnl_340);
nand #(1) U678(hnl_338, setLatch_b, DLLByPassMode_b, reset_b);
not #(1) U662(pwrdnRcvrs, hnl_335);
nand #(1) U699(hnl_162, preCycState5, setLatch_b);
nand #(1) U697(setLatch_b, hnl_171, hnl_248);
nand #(1) U694(hnl_327, idHitRowMiss, regOp_b);
nand #(1) U693(hnl_340, bcastWrite_b, idHit_b);
not #(1) U651(latchAbort_b, latchAbort);
u5clkCtl clkCtl(bcastWrite, runtclk, CASenable, DLLByPassMode_b, bcastWriteA, bcastWriteB, busyError_b, preCycState5, reset, tclkDisable_b, writeOp_b);
u5HitLog HitLog(CASenable, RASkill, RASstate4, bcastWrite_b, idHitRowMiss, idHit_b, idMissReturn_b, killFirstCycle_b, hnl_341, nack, packetIdHit, regOp_b, RASidle_b, abortOperation_b, ackClear,
bcastWrite, busyError_b, evalR, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, preCycState5, rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, updateRowAddr, writeA45, writeA45_b,
writeA0123);
u5PreCyc PreCyc(REQ, busyError_b, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idle, localREQ, virtuallyDone, writeA45, writeA45_b, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b,
NSOp, PDMD, RASreturn_b, RASstate4, RefreshReturn_b, TestRASB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitRowMiss, idMissReturn_b, preCycState5, rclk, regOp, reset, reset_b,
startNSAdr_b, writeOp_b);
not #(1) U590(reset_b, reset);
not #(1) U444(latchAbort, hnl_341);
endmodule

module u5RshXS (close0Pending_b, close0Selected, close1Pending_b, close1Selected, closeReq_b, endCycleD, rclk, reset);
output close0Pending_b, close0Selected, close1Pending_b, close1Selected;
input closeReq_b, endCycleD, rclk, reset;
supply1 vdd;
supply0 gnd;
ffBarC #(1) I11(close1Selected, rclk, hnl_342);
ffBarC #(1) I10(close0Selected, rclk, close0Pending_b);
not #(1) U443(close0Pending_b, hnl_343);
not #(1) U447(close1Pending_b, close1Pending);
nand #(1) U446(hnl_342, close0Pending_b, close1Pending);
aoi21A #(1) U253(hnl_344, endCycleD, close1Selected, reset);
aoi21A #(1) U250(hnl_345, endCycleD, close0Selected, reset);
srff I252(close1Pending, closeReq_b, hnl_344);
srff I251(hnl_343, closeReq_b, hnl_345);
endmodule

module u5RAScyc (DeviceBusy, RASAUXRet_b, RAScount_b, RASidle_b, RASldCount, RASprecharge, RASreturn_b, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RS_0_, RSTR, clearRASpending_b, close0Pending_b,
close0Selected, close1Pending_b, close1Selected, explicitRestore, localRSTR_b, setPD, DAmode_b, PD64after, PDreq2, RAScountLSB_b, RASoverflow_b, RASpending, RASpending_b, TestRSTR, busy_b,
closeCycle, closeCycle_b, closeReq_b, doAUXcycle, endCycleD_buf, needRestore_b, powerDownReq_b, rclk, reFetchCycle_b, reset, turboDLL_b);
output DeviceBusy, RASAUXRet_b, RAScount_b, RASidle_b, RASldCount, RASprecharge, RASreturn_b, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RS_0_, RSTR, clearRASpending_b, close0Pending_b,
close0Selected, close1Pending_b, close1Selected, explicitRestore, localRSTR_b, setPD;
input DAmode_b, PD64after, PDreq2, RAScountLSB_b, RASoverflow_b, RASpending, RASpending_b, TestRSTR, busy_b, closeCycle, closeCycle_b, closeReq_b, doAUXcycle, endCycleD_buf, needRestore_b,
powerDownReq_b, rclk, reFetchCycle_b, reset, turboDLL_b;
supply1 vdd;
supply0 gnd;
nor #(1) F94DC(hnl_346, gnd, gnd);
nor #(1) U800(hnl_153, hnl_347, RASidleLocal_b);
ffBNcRA I846(hnl_348, RAScount_b, RASoverflow_b, hnl_349);
nand #(1) I827(explicitRestore, reFetchCycle_b, expRestore_b);
ffBarD I451(hnl_350, rclk, hnl_351);
invFF U826(RAScount_b, hnl_350);
ffB #(1) I788(initLoad_b, rclk, hnl_352);
not #(1) U824(RS_0_, preRS_0_);
not #(1) U823(RS_b_0_, preRS_b_0_);
not #(1) U822(RS_b_1_, preRS_b_1_);
not #(1) U821(RS_1_, preRS_1_);
not #(1) U820(RS_b_2_, preRS_b_2_);
not #(1) U819(RS_2_, preRS_2_);
u5RshXS RshXS(close0Pending_b, close0Selected, close1Pending_b, close1Selected, closeReq_b, endCycleD_buf, rclk, reset);
ffA I631(hnl_324, initLoad_b, rclk);
ffA I808(hnl_353, hnl_324, rclk);
ffBarA #(1) I807(setPDEarly, rclk, hnl_354);
not #(1) U525(localRSTR_b, hnl_355);
not #(1) U754(needRestore, needRestore_b);
aoi21A #(1) U696(hnl_248, vdd, needRestore_b, hnl_353);
not #(1) U494(RSTR, hnl_356);
not #(1) I645(hnl_355, RSTR_b);
not #(1) U776(hnl_357, turboDLL_b);
ffQBB I545(preRS_2_, preRS_b_2_, hnl_77, rclk);
ffQBB I773(RASn2, hnl_358, RASn3, rclk);
ffC #(1) I763(RASsel_3_, rclk, hnl_153);
ffBarC #(1) I762(RASsel_1_, rclk, RASprecharge_b);
ffBarC #(1) I761(RASsel_2_, rclk, hnl_359);
nand #(1) F94DB(hnl_360, gnd, gnd);
nand #(1) F94DA(hnl_361, gnd, gnd);
nand #(1) U784(hnl_352, RASpending, RASpendingD_b);
not #(1) U739(doAUXcycle_b, doAUXcycle);
not #(1) U736(reset_b, reset);
ffRC I734(RASsel_0_, rclk, powerDownReq_b, hnl_362);
ffRC I793(setPD, rclk, reset_b, setPDEarly);
aoi21A #(1) U770(hnl_363, RAScntLSBdel, RAScntZ, hnl_358);
oai21A U730(m13, PD2leading, closeCycle, RS_1_);
nor #(1) U725(hnl_364, RASidleLocal_b, PD2leading);
nor #(1) U755(hnl_365, RS_b_2_, RS_b_1_, RS_b_0_);
nor #(1) U744(RASpowerDown, RS_2_, RS_b_1_, RS_b_0_);
nor #(1) U693(hnl_340, m00, RS_b_2_, RS_b_0_);
ffSB I657(hnl_366, rclk, hnl_168, reset);
not #(1) U658(clearRASpending_b, hnl_366);
not #(1) U679(RASprecharge, RASprecharge_b);
DAff I639(RSTR_b, rclk, TestRSTR, hnl_367, DAmode_b);
aoi22A U600(hnl_168, RS_b_2_, RS_b_0_, RS_2_, RS_0_);
ffQBC I765(RAScntZ_b, RAScntZ, hnl_368, rclk);
ffQBC I499(preRS_0_, preRS_b_0_, hnl_369, rclk);
ffQBC I498(preRS_1_, preRS_b_1_, hnl_370, rclk);
ffBarA #(1) I716(hnl_371, rclk, PDreq2);
not #(1) U576(RASsense, RASsense_b);
ffD I825(RASldCount, hnl_372, rclk);
ffBarB #(1) I792(RASpendingD_b, rclk, RASpending);
ffBarB #(1) I772(RAScntLSBdel, rclk, RAScountLSB_b);
ffBarB #(1) I740(PD2leading, rclk, hnl_373);
nand #(1) I231(hnl_374, RASidleLocal_b, RASn2);
nand #(1) U797(hnl_372, hnl_352, hnl_368);
nand #(1) I721(hnl_375, expRestore_b, reset_b);
nand #(1) U709(m00, needRestore_b, closeCycle_b);
nand #(1) I690(hnl_376, m13, m14);
nand #(1) I571(hnl_377, m11, m12);
nand #(1) I729(hnl_378, m15, reset_b, m16);
nand #(1) U722(hnl_379, m21, m22, m23);
nand #(1) I695(hnl_380, m03, reset_b, m04);
nand #(1) U684(hnl_381, setRSTR_b, RASsense_b, RSTR_b);
nand #(1) U674(hnl_362, RS_0_, hnl_382, hnl_383);
nand #(1) I551(hnl_73, m21, m02, RASprecharge_b);
nand #(1) U849(RASidle_b, RS_2_, RS_1_, RS_0_);
nand #(1) U831(DeviceBusy, hnl_365, busy_b, hnl_269);
nand #(1) U777(RASidleLocal_b, RS_2_, RS_1_, RS_0_);
nand #(1) U627(expRestore_b, preRS_b_2_, preRS_1_, preRS_0_);
nand #(1) U622(RASholdOff_b, RS_b_2_, RS_1_, RS_b_0_);
nand #(1) U593(RASAUXRet_b, RAScntZ, RASholdOff, doAUXcycle);
nand #(1) U591(RASreturn_b, RAScntZ, doAUXcycle_b, RASsense);
nand #(1) U588(RASsense_b, RS_b_2_, RS_b_1_, RS_0_);
nand #(1) U578(RASprecharge_b, RS_2_, RS_b_1_, RS_0_);
nand #(1) U400(RASn3, hnl_348, RAScount_b, RASn2);
nor #(1) U544(hnl_77, hnl_364, hnl_375, hnl_379);
nor #(1) U429(hnl_370, hnl_377, hnl_376, hnl_378);
nor #(1) U430(hnl_369, hnl_73, hnl_340, hnl_380);
nor #(1) U798(hnl_347, needRestore, RASpending_b);
nor #(1) U775(hnl_269, hnl_357, PD64after);
nor #(1) U732(hnl_359, RASsense, RASpowerDown);
nor #(1) U683(setRSTR_b, hnl_248, setPDEarly);
nand #(0) U685(hnl_354, RAScntZ, RS_0_, RS_1_, RS_b_2_);
nand #(0) U560(m11, RAScntZ, RS_b_1_, RS_b_0_, RS_b_2_);
nand #(0) U190(hnl_351, RASn3, RASidleLocal_b, hnl_363, RAScount_b);
nand #(1) U724(hnl_373, PDreq2, hnl_371);
nand #(1) U691(m12, RS_1_, RS_b_0_);
nand #(1) U660(hnl_382, RS_b_2_, RS_1_);
nand #(1) U562(m14, RASpendingD_b, RS_1_);
nand #(1) U561(m16, RS_b_2_, RS_1_);
nand #(1) U559(m15, RS_1_, RS_b_0_);
not #(1) U845(hnl_349, hnl_374);
not #(1) U840(hnl_356, hnl_384);
not #(1) U839(hnl_384, hnl_385);
not #(1) U838(hnl_385, hnl_242);
not #(1) U837(hnl_242, localRSTR_b);
not #(1) U621(RASholdOff, RASholdOff_b);
nand #(1) U702(m21, RAScntZ, RS_1_, RS_b_2_);
nand #(1) U701(m23, RAScntZ_b, RS_2_, RS_b_1_);
nand #(1) U699(m22, RAScntZ_b, RS_2_, RS_b_0_);
nand #(1) U663(hnl_383, needRestore_b, RS_1_, RASpending);
nand #(1) U647(hnl_367, hnl_381, RASholdOff_b, reset_b);
nand #(1) U557(m02, RAScntZ, RS_b_1_, RS_2_);
nand #(1) U555(m03, RASpendingD_b, RS_0_, RS_2_);
nand #(1) U553(m04, RAScntZ_b, RS_0_, RS_b_2_);
mux21 #(1) I532(hnl_368, RASn3, RASn2, RAScntLSBdel);
endmodule

module u5MscR7 (control_7_, control_5_, control_4_, control_3_, dataZ0, dataZ1, dataZ2, dataZ3, DAmode, dataIn0, dataIn1, dataIn2, dataIn3, ictrl_5_, ictrl_4_, ictrl_3_, readR_9_, readR_7_, readR_3_,
readR_0_, reset, writeR_3_);
output control_7_, control_5_, control_4_, control_3_;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input DAmode, dataIn0, dataIn1, dataIn2, dataIn3, ictrl_5_, ictrl_4_, ictrl_3_, readR_9_, readR_7_, readR_3_, readR_0_, reset, writeR_3_;
supply1 vdd;
supply0 gnd;
nor #(1) I149(control_5_, DAmode, hnl_386);
not #(1) U150(hnl_386, C5);
pdnull U147(dataZ1, readR_9_);
pdnull U146(dataZ0, readR_9_);
pdnull U145(dataZ3, readR_0_);
latBarSB #(1) I143_0_(control_7_, dataIn0, writeR_3_, reset);
latBarSB #(1) I143_1_(C5, dataIn1, writeR_3_, reset);
latBarSB #(1) I143_2_(control_4_, dataIn2, writeR_3_, reset);
latBarSB #(1) I143_3_(control_3_, dataIn3, writeR_3_, reset);
nandpd1 U148(dataZ3, readR_7_);
nandpd1 U242(dataZ0, readR_0_);
nandpd1 U138(dataZ2, readR_7_);
nandpd2 U133(dataZ0, control_7_, readR_3_);
nandpd2 U131_0_(dataZ1, ictrl_5_, readR_3_);
nandpd2 U131_1_(dataZ2, ictrl_4_, readR_3_);
nandpd2 U131_2_(dataZ3, ictrl_3_, readR_3_);
endmodule

module u5bit78 (ADR_6_, CASctCy70, NSWE_7_, RfshRwCy70, bcastWriteB, chainOut_8_, control_7_, control_5_, control_4_, control_3_, opcode_3_, opcode_0_, pd2_7_, dataZ0_7_, dataZ1_7_, dataZ2_7_,
dataZ3_7_, idHitA, rowHitLeftB, rowHitRightB, CASctCy67, DAmode_b, NSAdr_6_, RASaddrEnable, RfshRwCy67, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn1_7_, dataIn2_7_, dataIn3_7_, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, ictrl_5_, ictrl_4_, ictrl_3_, incColAdr_b, incRfshRow_b, loadNSWE, localBSEL, partialId_b_4_, pd0_7_, pd0_8_, pd1_7_, pd1_8_, pd2_8_, pd3_7_,
pd3_8_, rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_3_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_8_, unloadNSWE, updateRowAddr, writeA0123, writeA0123x,
writeR_8_, writeR_5_, writeR_3_, writeR_1_);
output ADR_6_, CASctCy70, NSWE_7_, RfshRwCy70, bcastWriteB, chainOut_8_, control_7_, control_5_, control_4_, control_3_, opcode_3_, opcode_0_, pd2_7_;
inout dataZ0_7_, dataZ1_7_, dataZ2_7_, dataZ3_7_, idHitA, rowHitLeftB, rowHitRightB;
input CASctCy67, DAmode_b, NSAdr_6_, RASaddrEnable, RfshRwCy67, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn1_7_, dataIn2_7_, dataIn3_7_, driveColAdr, driveNSAdr, drivePacketRASaddr,
driveRfshAddr_b, eval, ictrl_5_, ictrl_4_, ictrl_3_, incColAdr_b, incRfshRow_b, loadNSWE, localBSEL, partialId_b_4_, pd0_7_, pd0_8_, pd1_7_, pd1_8_, pd2_8_, pd3_7_, pd3_8_, rclk, readR_10_, readR_9_,
readR_8_, readR_7_, readR_5_, readR_3_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_8_, unloadNSWE, updateRowAddr, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_3_,
writeR_1_;
supply1 vdd;
supply0 gnd;
aoi21A #(1) F94AV(hnl_387, gnd, gnd, gnd);
ffBarRA F94AU(hnl_388, gnd, gnd, vdd);
ltxRB F94AT(hnl_389, gnd, gnd, vdd);
ffC #(1) F94AS(hnl_390, gnd, gnd);
nand #(0) F94AP(hnl_391, gnd, gnd, gnd, gnd);
nor #(1) F94AR(hnl_392, gnd, gnd);
nor #(1) F94AQ(hnl_393, gnd, gnd);
nand #(1) F94AO(hnl_394, gnd, gnd);
nand #(1) F94AN(hnl_395, gnd, gnd);
ltxSB I572(hnl_396, hnl_62, writeA0123, reset);
ltxBarSB op0(A0_8_, writeA0123x, pd0_8_, reset);
ltxBarSB op3(hnl_397, writeA0123x, pd1_8_, reset);
ltxBarB Addr35(Addr_35_, writeA0123, pd3_8_);
ltxBarB Addr34(Addr_34_, writeA0123, pd3_7_);
latBNcA I584(packetRowAddr_6_, RASaddrEnable, packetRowAddr_b_6_);
mux71x AdrMUX6(ADR_6_, ColAdr_6_, NSAdr_6_, packetRowAddr_6_, rfshRowAddr_6_, bank0RowAddr_6_, bank1RowAddr_6_, testBD_8_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_398, restoreBank0,
restoreBank1, DAmode);
not #(1) U574(bcastWriteB, hnl_396);
not #(1) I544(opcode_0_, A0_8_);
not #(1) U543(opcode_3_, hnl_397);
nand #(1) U571(hnl_62, pd1_8_, pd0_8_);
u5NSWErg NSWErg7(NSWE_7_, selectEven_7_, loadNSWE, pd2_7_, pd3_7_, rclk, unloadNSWE);
not #(1) I556(DAmode, DAmode_b);
nor #(1) I552(hnl_398, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U548(RfshRwCy70, hnl_399);
not #(1) U547(CASctCy70, hnl_78);
not #(1) U549(hnl_399, hnl_400);
not #(1) U546(hnl_78, net965);
not #(1) U545(chainOut_8_, hnl_68);
not #(1) U539(hnl_68, hnl_401);
mux21 #(1) I537(hnl_401, chainOutEven_8_, chainOutOdd_8_, rclk);
not #(1) U519(ColAdr_6_, net964);
countup Col_6_(net965, net964, incColAdr_b, CASctCy67, writeA0123x, pd0_7_);
u5id Id26_35(id_35_, id_26_, dataZ1_7_, dataZ3_7_, idHitA, partialId_b_5_, Addr_35_, dataIn1_7_, dataIn3_7_, eval, readR_1_, reset_b, writeR_1_);
u5id Id25_34(id_34_, id_25_, dataZ0_7_, dataZ2_7_, idHitA, partialId_b_4_, Addr_34_, dataIn0_7_, dataIn2_7_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_6_(bank0RowAddr_6_, bank1RowAddr_6_, dataZ0_7_, dataZ2_7_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_6_, packetRowAddr_b_6_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr6(adrSelReg_6_, partialId_b_5_, packetRowAddr_b_6_, dataZ0_7_, dataIn0_7_, pd1_7_, pd2_8_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw6(hnl_400, rfshRowAddr_6_, dataZ0_7_, RfshRwCy67, dataIn0_7_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR7 MscR7(control_7_, control_5_, control_4_, control_3_, dataZ0_7_, dataZ1_7_, dataZ2_7_, dataZ3_7_, DAmode, dataIn0_7_, dataIn1_7_, dataIn2_7_, dataIn3_7_, ictrl_5_, ictrl_4_, ictrl_3_,
readR_9_, readR_7_, readR_3_, readR_0_, reset, writeR_3_);
not #(1) F94AM(hnl_402, gnd);
not #(1) F94AL(hnl_403, gnd);
not #(1) U511(reset_b, reset);
endmodule

module u5CCct (out, q, bypassIn, clk_b, errorIn, load, resetCnt_b, sel);
output out, q;
input bypassIn, clk_b, errorIn, load, resetCnt_b, sel;
supply1 vdd;
supply0 gnd;
nor #(1) U18(hnl_404, hnl_405, errorIn);
ffBNcRA I17(hnl_405, clk_b, q, resetCnt_b);
not #(1) U4(hnl_406, bypassIn);
latBarA I2(hnl_407, load, clk_b);
not #(1) I21(q, hnl_404);
not #(1) U11(out, hnl_408);
mux21 #(1) I3(hnl_408, hnl_407, hnl_406, sel);
endmodule

module u5CCLog (count, loadIctrl, powerOn, resetCap, resetCnt_b, done, evalCurrentCnt, gated_mclk, rclk, reset, writeA0123);
output count, loadIctrl, powerOn, resetCap, resetCnt_b;
input done, evalCurrentCnt, gated_mclk, rclk, reset, writeA0123;
supply1 vdd;
supply0 gnd;
ffSync I54(loadIctrl, rclk, hnl_409);
aoi21A #(1) U42(resetCnt_b, s0_b, resetCap, reset);
aoi21A #(1) U2(hnl_410, done_b, s1_b, s0_b);
ffB #(1) I36(s0, gated_mclk, hnl_411);
ffB #(1) I35(resetCap, gated_mclk, hnl_410);
not #(1) U34(s0_b, s0);
not #(1) U33(s1_b, resetCap);
nor #(1) I32(done_b, done, reset);
oai21A U3(hnl_411, s1_b, hnl_142, done_b);
nand #(0) U7(hnl_409, evalCurrentCnt, writeA0123, s0, resetCap);
nand #(0) U24(hnl_412, done_b, s1_b, s0_b, gated_mclk);
nand #(1) I18(powerOn, resetCap, s0);
not #(1) U43(hnl_142, evalCurrentCnt);
not #(1) I21(count, hnl_412);
endmodule

module u5CCctl (ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, powerOn, resetCap, control_7_, control_6_, control_5_, control_4_, control_3_, control_2_, control_1_, control_0_, done,
evalCurrentCnt, gated_mclk, rclk, reset, writeA0123);
output ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, powerOn, resetCap;
input control_7_, control_6_, control_5_, control_4_, control_3_, control_2_, control_1_, control_0_, done, evalCurrentCnt, gated_mclk, rclk, reset, writeA0123;
supply1 vdd;
supply0 gnd;
u5CCct CCct_0_(ictrl_0_, CCn1_1_, control_0_, CCn1_0_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_1_(ictrl_1_, CCn1_2_, control_1_, CCn1_1_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_2_(ictrl_2_, CCn1_3_, control_2_, CCn1_2_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_3_(ictrl_3_, CCn1_4_, control_3_, CCn1_3_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_4_(ictrl_4_, CCn1_5_, control_4_, CCn1_4_, error, loadIctrl, resetCnt_b, control_7_);
u5CCct CCct_5_(ictrl_5_, error, control_5_, CCn1_5_, gnd, loadIctrl, resetCnt_b, control_7_);
ffBNcRA I52(hnl_413, count, hnl_413, resetCnt_b);
mux21 #(1) I46(CCn1_0_, hnl_413, count, control_6_);
u5CCLog CCLog(count, loadIctrl, powerOn, resetCap, resetCnt_b, done, evalCurrentCnt, gated_mclk, rclk, reset, writeA0123);
endmodule

module u5CASdy0 (readDelay_0_, writeDelay_0_, dataZ1, dataZ3, dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_);
output readDelay_0_, writeDelay_0_;
inout dataZ1, dataZ3;
input dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
latSB #(1) I398(readDelay_0_, dataIn1, writeR_2_, reset);
latRB #(1) I397(writeDelay_0_, dataIn3, writeR_2_, reset_b);
nandpd2 U402(dataZ1, readDelay_0_, readR_2_);
nandpd2 U395(dataZ3, writeDelay_0_, readR_2_);
endmodule

module u5MscR3 (ackDelay, ackWinDelay, skipBit, dataZ0, dataZ1, dataZ2, dataIn0, dataIn2, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_3_, writeR_2_);
output ackDelay, ackWinDelay, skipBit;
inout dataZ0, dataZ1, dataZ2;
input dataIn0, dataIn2, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_3_, writeR_2_;
supply1 vdd;
supply0 gnd;
pdnull U157(dataZ1, readR_9_);
pdnull U156(dataZ0, readR_9_);
latRB #(1) I158(skipBit, dataIn0, writeR_3_, reset_b);
latRB #(1) I155(ackWinDelay, dataIn0, writeR_2_, reset_b);
latRB #(1) hnl_414(ackDelay, dataIn2, writeR_2_, reset_b);
nandpd1 U128(dataZ1, readR_0_);
nandpd2 U161(dataZ0, skipBit, readR_3_);
nandpd2 U238(dataZ2, ackDelay, readR_2_);
nandpd2 U132(dataZ0, ackWinDelay, readR_2_);
endmodule

module u5bit3 (ADR_2_, CASctCy34, Count_1_, DAR_2_, NSWE_3_, RASctCy32, RfshRwCy34, ackDelay_0_, ackWinDelay_0_, partialId_b_1_, pd2_3_, readDelay_0_, rfshBSEL, skipBit, writeDelay_0_, dataZ0_3_,
dataZ1_3_, dataZ2_3_, dataZ3_3_, idHitB, rowHitLeftB, rowHitRightB, CASctCy23, DAmode_b, NSAdr_2_, RASaddrEnable, RAScount_b, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy23,
dataIn0_3_, dataIn1_3_, dataIn2_3_, dataIn3_3_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_0_, pd0_3_,
pd1_3_, pd2_4_, pd3_3_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, testBD_4_, unloadNSWE,
updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_6_, writeR_5_, writeR_3_, writeR_2_, writeR_1_);
output ADR_2_, CASctCy34, Count_1_, DAR_2_, NSWE_3_, RASctCy32, RfshRwCy34, ackDelay_0_, ackWinDelay_0_, partialId_b_1_, pd2_3_, readDelay_0_, rfshBSEL, skipBit, writeDelay_0_;
inout dataZ0_3_, dataZ1_3_, dataZ2_3_, dataZ3_3_, idHitB, rowHitLeftB, rowHitRightB;
input CASctCy23, DAmode_b, NSAdr_2_, RASaddrEnable, RAScount_b, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy23, dataIn0_3_, dataIn1_3_, dataIn2_3_, dataIn3_3_, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_0_, pd0_3_, pd1_3_, pd2_4_, pd3_3_, rclk, readR_10_, readR_9_, readR_8_,
readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, testBD_4_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_6_,
writeR_5_, writeR_3_, writeR_2_, writeR_1_;
supply1 vdd;
supply0 gnd;
latSRB rowExpRest1(rowExpRest_1_, dataIn3_3_, writeR_6_, reset_b, gnd);
latSRB rowImpRest1(rowImpRest_1_, dataIn2_3_, writeR_6_, vdd, reset);
latSRB rowAcc1(rowAcc_1_, dataIn1_3_, writeR_6_, reset_b, gnd);
latSRB rowPre1(rowPre_1_, dataIn0_3_, writeR_6_, vdd, reset);
ltxBarB Count1(Count_b_1_, writeA45, pd3_3_);
ltxBarB Addr30(Addr_30_, writeA0123, pd3_3_);
latBNcA I578(packetRowAddr_2_, RASaddrEnable, packetRowAddr_b_2_);
mux71x AdrMUX2(ADR_2_, ColAdr_2_, NSAdr_2_, packetRowAddr_2_, rfshRowAddr_2_, bank0RowAddr_2_, bank1RowAddr_2_, testBD_4_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_224, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg3(NSWE_3_, selectEven_3_, loadNSWE, pd2_3_, pd3_3_, rclk, unloadNSWE);
not #(1) I571(DAmode, DAmode_b);
nor #(1) I567(hnl_224, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U553(Count_1_, Count_b_1_);
u5RfshRw RfshRw2(RfshRwCy34, rfshRowAddr_2_, dataZ0_3_, n3_0_, dataIn0_3_, incRfshRow_b, readR_5_, writeR_5_);
u5RfshRw RfshBS(n3_0_, rfshBSEL, dataZ1_3_, RfshRwCy23, dataIn1_3_, incRfshRow_b, readR_5_, writeR_5_);
mux41 #(1) I548(cnt1, rowPre_1_, rowAcc_1_, rowImpRest_1_, rowExpRest_1_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
nandpd2 U547(dataZ3_3_, rowExpRest_1_, readR_6_);
nandpd2 U529(dataZ2_3_, rowImpRest_1_, readR_6_);
nandpd2 U517(dataZ0_3_, rowPre_1_, readR_6_);
nandpd2 U515(dataZ1_3_, rowAcc_1_, readR_6_);
u5id Id21_30(id_30_, id_21_, dataZ0_3_, dataZ2_3_, idHitB, partialId_b_0_, Addr_30_, dataIn0_3_, dataIn2_3_, eval, readR_1_, reset_b, writeR_1_);
u5DARbit DARbit2(DAR_2_, loadDAR, DAmode, setDAR, testBD_4_);
not #(1) U555(ColAdr_2_, net3105);
countup RASct1(RASctCy32, RAScnt_1_, RAScount_b, gnd, RASldCount, cnt1);
countup Col_2_(CASctCy34, net3105, incColAdr_b, CASctCy23, writeA0123x, pd0_3_);
u5Rhit Rhit_2_(bank0RowAddr_2_, bank1RowAddr_2_, dataZ0_3_, dataZ2_3_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_2_, packetRowAddr_b_2_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr2(adrSelReg_2_, partialId_b_1_, packetRowAddr_b_2_, dataZ0_3_, dataIn0_3_, pd1_3_, pd2_4_, readR_8_, reset_b, writeA0123, writeR_8_);
u5CASdy0 CASdy0(readDelay_0_, writeDelay_0_, dataZ1_3_, dataZ3_3_, dataIn1_3_, dataIn3_3_, readR_2_, reset, reset_b, writeR_2_);
u5MscR3 MscR3(ackDelay_0_, ackWinDelay_0_, skipBit, dataZ0_3_, dataZ1_3_, dataZ2_3_, dataIn0_3_, dataIn2_3_, readR_9_, readR_3_, readR_2_, readR_0_, reset_b, writeR_3_, writeR_2_);
not #(1) U490(reset_b, reset);

always @(negedge writeR_1_) begin : load_rdram
   parameter FILE_NAME = "rdram_gate_";
   parameter FILE_EXT = ".data";
   reg [7:0] file_number;
   reg [8*20-1:0] file_name;
   integer i;
   reg [3:0] nibble;
   if ($test$plusargs("load_rdram") && (id_21_ !== 1'bx)) begin
      nibble = id_21_;
      file_number = nibble + ((nibble > 9) ? "a" - 10 : "0");
$display("%m: loading %s", {FILE_NAME, file_number, FILE_EXT});
      $readmemh({FILE_NAME, file_number, FILE_EXT}, NEC_18M_RDRAM.top.MemC.core);
      end
   end
endmodule

module u5DirtyB (dirtyB0, dirtyB1, needRestore_b, CASwrite, localRSTR_b, packetBSELx, rclk, reset);
output dirtyB0, dirtyB1, needRestore_b;
input CASwrite, localRSTR_b, packetBSELx, rclk, reset;
supply1 vdd;
supply0 gnd;
nor #(1) U52(clearDirtyB, localRSTR_b, hnl_415);
ffBarA #(1) I51(hnl_415, rclk, localRSTR_b);
aoi21A #(1) U49(hnl_416, packetBSELx, clearDirtyB, reset);
aoi21A #(1) U48(hnl_417, clearDirtyB, hnl_411, reset);
nand #(1) U4(hnl_406, CASwrite, hnl_411);
nand #(1) U9(hnl_418, CASwrite, packetBSELx);
not #(1) U3(hnl_411, packetBSELx);
not #(1) U27(hnl_419, packetBSELx);
aoi22A U60(needRestore_b, hnl_419, dirtyB0, packetBSELx, dirtyB1);
aoi22A U43(needRestore_b, hnl_419, dirtyB0, packetBSELx, dirtyB1);
srff I10(dirtyB1, hnl_418, hnl_416);
srff I5(dirtyB0, hnl_406, hnl_417);
endmodule

module u5Wcntl (TestMPBT, TestWE, TestWML, TestWPBT, TestWRITE, TestRASB, TestRSTR, TimingTest, WPB_MPBTest, rawTestWE);
output TestMPBT, TestWE, TestWML, TestWPBT, TestWRITE;
input TestRASB, TestRSTR, TimingTest, WPB_MPBTest, rawTestWE;
supply1 vdd;
supply0 gnd;
not #(1) U130(TestRAS, TestRASB);
nor #(1) U177(hnl_420, WEatRSTRfall_b, hnl_421);
not #(1) I186(TestWPBT, hnl_422);
not #(1) I185(TestWML, hnl_423);
not #(1) I184(TestWE, hnl_424);
not #(1) I183(TestMPBT, hnl_425);
not #(1) I171(TestWRITE, hnl_426);
ffBNcRA I18(WEatRSTRfall_b, TestRSTR, rawTestWE, TestRAS);
ffNcA I17(WEatRASBfall, rawTestWE, TestRASB);
nand #(1) I160(hnl_427, hnl_428, WEatRSTRfall, WEatRASBfall_b);
nand #(1) U144(hnl_429, hnl_430, TimingTest, hnl_431);
not #(1) U20(WEatRSTRfall, WEatRSTRfall_b);
not #(1) U182(hnl_432, hnl_433);
nor #(1) I173(hnl_433, rawTestWE, hnl_420);
nor #(1) U175(hnl_421, TimingTest, WPB_MPBTest);
nand #(0) U79(hnl_434, rawTestWE, WEatRSTRfall, WEatRASBfall, TimingTest);
nand #(1) I168(hnl_435, hnl_434, hnl_436);
nand #(1) U104(hnl_423, rawTestWE, WEatRSTRfall, TestWPBT);
nand #(1) U155(hnl_424, hnl_429, TestRAS);
nand #(1) U170(hnl_426, hnl_432, TestRAS);
nand #(1) U169(hnl_436, WEatRASBfall_b, WPB_MPBTest);
nand #(1) U165(hnl_425, hnl_435, TestRAS);
nand #(1) U125(hnl_422, TestRAS, WPB_MPBTest);
not #(1) I181(hnl_428, rawTestWE);
not #(1) U180(hnl_431, WPB_MPBTest);
not #(1) U151(hnl_430, hnl_427);
not #(1) U100(WEatRASBfall_b, WEatRASBfall);
endmodule

module u5DAdec (AGEGND, AGEING, CMPV, HVST, PDMD, ROLLC, RcvrsOff_b, SDST, SerialMode, SimpleMode, TimingTest, VCMNA, VRST, WPB_MPBTest, chain_b, BIMDI, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_,
DAmode, powerDownMode, runclk_b);
output AGEGND, AGEING, CMPV, HVST, PDMD, ROLLC, RcvrsOff_b, SDST, SerialMode, SimpleMode, TimingTest, VCMNA, VRST, WPB_MPBTest, chain_b;
input BIMDI, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, DAmode, powerDownMode, runclk_b;
supply1 vdd;
supply0 gnd;
nor #(1) U413(RcvrsOff_b, runclk_b, powerDownMode);
nand #(1) U328(hnl_437, hnl_41, RcvrsOff_b, hnl_300);
not #(1) I403(DARt_2_, hnl_438);
nand #(1) U331(DRAMtest, DARt_3_, DARt_4_);
not #(1) U366(hnl_128, powerDownMode);
not #(1) U410(DAR_b_2_, hnl_439);
not #(1) U579(BIMD_b, BIMDI);
invEE I290(chain_b, hnl_437);
not #(1) I390(ROLLC, hnl_440);
not #(1) I389(AGEGND, hnl_303);
not #(1) I344(AGEING, hnl_441);
not #(1) I395(PDMD, hnl_442);
not #(1) I394(VRST, hnl_443);
not #(1) I393(VCMNA, hnl_444);
not #(1) I392(HVST, hnl_445);
not #(1) I391(SDST, hnl_446);
nor #(1) U411(hnl_439, hnl_298, BIMDI);
nor #(1) U372(DA0, DARt_0_, DARt_1_);
nor #(1) U371(DA1, DAR_b_0_, DARt_1_);
nor #(1) U370(DA2, DARt_0_, DAR_b_1_);
nor #(1) U369(DA3, DAR_b_0_, DAR_b_1_);
nand #(1) I365(hnl_447, hnl_128, hnl_448);
nand #(1) U350(hnl_303, SimpleMode, DAR_b_2_, DA2);
nand #(1) U336(hnl_272, DAR_b_4_, DAR_b_2_, DA1);
nand #(1) U338(hnl_441, SimpleMode, DAR_b_2_, DA1);
nand #(1) U368(hnl_440, R_IFTest, DAR_b_2_, DA0);
nand #(1) U347(hnl_449, R_IFTest, DAR_b_2_, DA1);
nand #(1) U348(hnl_450, DAR_b_4_, DAR_b_2_, DA2);
nand #(1) U400(hnl_438, DAR_2_, BIMD_b, DAmode);
nand #(1) U363(hnl_443, DRAMtest, DARt_2_, DA3);
nand #(1) U361(hnl_444, DRAMtest, DARt_2_, DA2);
nand #(1) U358(hnl_448, DRAMtest, DAR_b_2_, DA3);
nand #(1) U357(hnl_446, DRAMtest, DARt_2_, DA0);
nand #(1) U354(hnl_445, DRAMtest, DARt_2_, DA1);
nor #(1) U412(hnl_298, DAR_2_, hnl_451);
nor #(1) U405(DAR_b_3_, DAR_3_, BIMDI);
not #(1) U404(hnl_451, DAmode);
not #(1) U396(hnl_442, hnl_447);
nand #(1) U408(hnl_300, DARt_3_, DAmode);
nand #(1) U398_0_(DAR_b_4_, DAR_4_, BIMD_b);
nand #(1) U398_1_(DAR_b_1_, DAR_1_, BIMD_b);
nand #(1) U398_2_(DAR_b_0_, DAR_0_, BIMD_b);
nand #(1) U330(hnl_41, DAR_b_3_, DARt_4_);
not #(1) I417(CMPV, hnl_449);
not #(1) I351(WPB_MPBTest, hnl_450);
not #(1) I345(TimingTest, hnl_272);
not #(1) I407(SerialMode, hnl_300);
not #(1) I406(DARt_3_, DAR_b_3_);
not #(1) I399_0_(DARt_4_, DAR_b_4_);
not #(1) I399_1_(DARt_1_, DAR_b_1_);
not #(1) I399_2_(DARt_0_, DAR_b_0_);
not #(1) I292(SimpleMode, hnl_41);
not #(1) I275(R_IFTest, DRAMtest);
endmodule

module u5TstCtl (AGEGND, AGEING, CMPV, DAWD0123, DAWD4567, DAmode_b, DLLByPassMode_b, HVST, PDMD, ROLLC, RcvrsOff_b, SDST, TestMPBT, TestSOut, TestWE, TestWML, TestWPBT, TestWRITE, VCMNA, VRST,
chain_b, enableSOut, loadDAR, needRestore_b, testLoad_b, BIMDI, CASwrite, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, RCRED, SInRaw_b, TestCAS, TestRASB, TestRSTR, chainOut_8_, localBSEL, localRSTR_b,
lowVref, powerDownMode, rclk, reset, resetDAmode_b, runclk_b, slow, testBD_b_0_);
output AGEGND, AGEING, CMPV, DAWD0123, DAWD4567, DAmode_b, DLLByPassMode_b, HVST, PDMD, ROLLC, RcvrsOff_b, SDST, TestMPBT, TestSOut, TestWE, TestWML, TestWPBT, TestWRITE, VCMNA, VRST, chain_b,
enableSOut, loadDAR, needRestore_b, testLoad_b;
input BIMDI, CASwrite, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, RCRED, SInRaw_b, TestCAS, TestRASB, TestRSTR, chainOut_8_, localBSEL, localRSTR_b, lowVref, powerDownMode, rclk, reset, resetDAmode_b,
runclk_b, slow, testBD_b_0_;
supply1 vdd;
supply0 gnd;
nor #(1) I351(DAmode, hnl_452, DLLByPassMode_b);
latRA #(1) I318(hnl_453, SInRaw_b, lowVref, resetDAmode_b);
u5DirtyB DirtyB(dirtyB0, dirtyB1, needRestore_b, CASwrite, localRSTR_b, localBSEL, rclk, reset);
srff I313(hnl_454, TestRASB, hnl_455);
u5Wcntl Wcntl(TestMPBT, TestWE, TestWML, TestWPBT, TestWRITE, TestRASB, TestRSTR, TimingTest, WPB_MPBTest, rawTestWE);
u5DAdec DAdec(AGEGND, AGEING, CMPV, HVST, PDMD, ROLLC, RcvrsOff_b, SDST, SerialMode, SimpleMode, TimingTest, VCMNA, VRST, WPB_MPBTest, chain_b, BIMDI, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, DAmode,
powerDownMode, runclk_b);
nand #(1) U213(hnl_455, DAmode, rclk);
invEE U251(DAmode_b, DAmode);
not #(1) U295(testLoad_b, hnl_456);
not #(1) I287(TestSOut, hnl_457);
not #(1) I289(loadDAR, hnl_458);
oai21A U255(hnl_458, TestCAS, DAmode_b, TestRASB);
mux31 #(1) I273(hnl_459, chainOut_8_, FailDetectOut_b, hnl_460, hnl_51, SimpleMode, ROLLC);
mux21 #(1) I262(hnl_461, DAcnt_b_1_, hnl_462, DAcnt_0_);
nand #(1) U308(hnl_463, TestCAS, TestRASB, SimpleMode);
nand #(1) I243(hnl_464, hnl_465, hnl_466);
nor #(1) U236(hnl_51, hnl_467, ROLLC);
not #(1) I312(enableSOut, hnl_55);
not #(1) I285(DAWD4567, hnl_468);
not #(1) I230(DAWD0123, hnl_469);
nand #(1) I229(hnl_470, hnl_471, hnl_463, DAmode);
ffBNcRA I305(hnl_472, hnl_473, gnd, TestCAS_b);
ffBNcRA I296(hnl_474, hnl_455, hnl_475, hnl_476);
ffBNcRA I293(hnl_477, SOutClk_b, hnl_478, resetFailDet_b);
ffBNcRA I286(hnl_479, SOutClk, hnl_480, resetFailDet_b);
ffBNcRA I249(hnl_481, TestCAS, gnd, TestRASB);
ffBNcRA I245(hnl_482, hnl_473, hnl_483, TestCAS_b);
ffBNcRA I242(hnl_475, hnl_455, gnd, hnl_476);
ffBNcRA I240(DAcnt_1_, hnl_484, hnl_461, testCntReset_b);
ffBNcRA I226(DAcnt_0_, hnl_484, DAcnt_0_, testCntReset_b);
not #(1) I301(cmpData, testBD_b_0_);
not #(1) I278(xor_result, hnl_485);
not #(1) I258(DAcnt_b_1_, DAcnt_1_);
not #(1) I232(rawTestWE, SInRaw_b);
not #(1) I290(TestRAS, TestRASB);
not #(1) I223(hnl_456, hnl_486);
nor #(1) U352(hnl_452, BIMDI, hnl_453);
nor #(1) U270(FailDetectOut_b, hnl_479, hnl_477);
nor #(1) U264(hnl_480, hnl_479, xor_result);
nor #(1) U259(hnl_478, hnl_477, xor_result);
nor #(1) U235(hnl_484, hnl_455, TestRAS);
nand #(1) I216(SOutClk, hnl_482, hnl_473, TestRAS);
not #(1) U339(hnl_487, powerDownMode);
not #(1) U313(hnl_55, hnl_470);
not #(1) U297(hnl_467, SerialMode);
not #(1) U294(hnl_485, hnl_464);
not #(1) U292(TestCAS_b, TestCAS);
not #(1) U288(hnl_488, chainOut_8_);
not #(1) U271(hnl_462, DAcnt_b_1_);
not #(1) U263(hnl_457, hnl_459);
not #(1) U257(hnl_460, RCRED);
not #(1) U250(SOutClk_b, SOutClk);
not #(1) U241(hnl_483, hnl_472);
nand #(1) U336(DLLByPassMode_b, hnl_487, slow);
nand #(1) U314(testCntReset_b, hnl_454, TestRASB);
nand #(1) U247(resetFailDet_b, hnl_481, DAmode);
nand #(1) U298(hnl_466, testBD_b_0_, hnl_488);
nand #(1) U282(hnl_468, DAcnt_0_, DAcnt_b_1_);
nand #(1) U277(hnl_476, TestCAS, TestRAS);
nand #(1) U265(hnl_465, chainOut_8_, cmpData);
nand #(1) U252(hnl_469, DAcnt_0_, DAcnt_1_);
nand #(1) U244(hnl_473, hnl_455, TestRAS);
nand #(1) U228(hnl_486, hnl_474, TestRAS);
nand #(1) U225(hnl_471, TestRAS, SerialMode);
endmodule

module RWDfthru (RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_);
inout RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_;
supply1 vdd;
supply0 gnd;
endmodule

module u5idA (debug, dataZA3, idhit, A3_b, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID);
output debug;
inout dataZA3, idhit;
input A3_b, dataInA3, evalId, readDeviceId, reset_b, writeDeviceID;
supply1 vdd;
supply0 gnd;
latRA #(1) I53(debug, dataInA3, writeDeviceID, reset_b);
xnandpc2 U51(idhit, debug, evalId, A3_b);
nandpd2 U48(dataZA3, debug, readDeviceId);
endmodule

module u5MscR0 (setRR_b, dataZ0, dataZ1, dataZ2, dataZ3, dataIn3, incRfshRow_b, readR_9_, readR_2_, readR_0_, reset, writeR_7_);
output setRR_b;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn3, incRfshRow_b, readR_9_, readR_2_, readR_0_, reset, writeR_7_;
supply1 vdd;
supply0 gnd;
not #(1) U176(hnl_489, incRfshRow_b);
not #(1) U172(setRR_b, hnl_490);
nor #(1) U171(clearSetRR_b, reset, hnl_489);
pdnull U164(dataZ1, readR_9_);
pdnull U163(dataZ0, readR_9_);
latRB #(1) I175(hnl_490, dataIn3, writeR_7_, clearSetRR_b);
nandpd1 U155(dataZ2, readR_9_);
nandpd1 U148(dataZ1, readR_0_);
nandpd1 U133(dataZ3, readR_2_);
nandpd1 U131(dataZ0, readR_2_);
nandpd1 U132(dataZ1, readR_2_);
endmodule

module u5bit0 (ADR_7_, Addr_0_, Addr_2_, NSWE_0_, RASoverflow_b, RfshRwCy01, muxBS8, setRR_b, testBD_b_0_, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, idHitB, rowHitLeftA, rowHitRightA, CASctCy70,
DAmode_b, NSAdr_7_, RASaddrEnable, RAScount_b, RASctCy10, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy70, dataIn0_0_, dataIn1_0_, dataIn2_0_, dataIn3_0_, driveColAdr, driveNSAdr,
drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, pd0_0_, pd1_0_, pd2_0_, pd3_0_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_2_,
readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_0_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_1_);
output ADR_7_, Addr_0_, Addr_2_, NSWE_0_, RASoverflow_b, RfshRwCy01, muxBS8, setRR_b, testBD_b_0_;
inout dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, idHitB, rowHitLeftA, rowHitRightA;
input CASctCy70, DAmode_b, NSAdr_7_, RASaddrEnable, RAScount_b, RASctCy10, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy70, dataIn0_0_, dataIn1_0_, dataIn2_0_, dataIn3_0_,
driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, pd0_0_, pd1_0_, pd2_0_, pd3_0_, rclk, readR_10_, readR_9_, readR_8_,
readR_6_, readR_5_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_0_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_,
writeR_5_, writeR_1_;
supply1 vdd;
supply0 gnd;
aoi21A #(1) F94AJ(hnl_491, gnd, gnd, gnd);
ffBarRA F94AK(hnl_492, gnd, gnd, vdd);
ltxRB F94AI(hnl_493, gnd, gnd, vdd);
ffC #(1) F94AH(hnl_494, gnd, gnd);
nand #(0) F94AE(hnl_495, gnd, gnd, gnd, gnd);
nor #(1) F94AG(hnl_496, gnd, gnd);
nor #(1) F94AF(hnl_497, gnd, gnd);
nand #(1) F94AD(hnl_498, gnd, gnd);
nand #(1) F94AC(hnl_499, gnd, gnd);
latSRB rowExpRest4(rowExpRest_4_, dataIn3_0_, writeR_6_, reset_b, gnd);
latSRB rowImpRest4(rowImpRest_4_, dataIn2_0_, writeR_6_, reset_b, gnd);
latSRB rowAcc4(rowAcc_4_, dataIn1_0_, writeR_6_, reset_b, gnd);
latSRB rowPre4(rowPre_4_, dataIn0_0_, writeR_6_, reset_b, gnd);
ltxBarB Addr0(Addr_b_0_, writeA45, pd3_0_);
ltxBarSB Addr2(A0_0_, writeA0123x, pd0_0_, reset);
latBNcA I522(packetRowAddr_7_, RASaddrEnable, packetRowAddr_b_7_);
mux71x AdrMUX7(ADR_7_, ColAdr_7_, NSAdr_7_, packetRowAddr_7_, rfshRowAddr_7_, bank0RowAddr_7_, bank1RowAddr_7_, testBD_0_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_500, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg0(NSWE_0_, selectEven_0_, loadNSWE, pd2_0_, pd3_0_, rclk, unloadNSWE);
nor #(1) U516(hnl_500, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U515(Addr_0_, Addr_b_0_);
not #(1) U513(muxBS8, hnl_501);
ffBNcRA I505(hnl_501, hnl_502, testBD_0_, DAmode);
mux41 #(1) I502(cnt4, rowPre_4_, rowAcc_4_, rowImpRest_4_, rowExpRest_4_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
not #(1) U506(hnl_502, loadDAR);
nandpd2 U501(dataZ3_0_, rowExpRest_4_, readR_6_);
nandpd2 U495(dataZ2_0_, rowImpRest_4_, readR_6_);
nandpd2 U493(dataZ1_0_, rowAcc_4_, readR_6_);
nandpd2 U489(dataZ0_0_, rowPre_4_, readR_6_);
not #(1) U470(ColAdr_7_, net2018);
not #(1) U528(RASoverflow_b, hnl_503);
not #(1) U463(testBD_b_0_, testBD_0_);
not #(1) U514(Addr_2_, A0_0_);
countup RASct4(hnl_504, RAScnt_4_, RAScount_b, RASctCy10, RASldCount, cnt4);
countup Col_7_(net2017, net2018, incColAdr_b, CASctCy70, writeA0123x, pd1_0_);
u5idA Id27(id_27_, dataZ2_0_, idHitB, partialId_b_6_, dataIn2_0_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_7_(bank0RowAddr_7_, bank1RowAddr_7_, dataZ1_0_, dataZ3_0_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_7_, packetRowAddr_b_7_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr7(adrSelReg_7_, partialId_b_6_, packetRowAddr_b_7_, dataZ1_0_, dataIn1_0_, pd2_0_, pd3_0_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw7(RfshRwCy01, rfshRowAddr_7_, dataZ2_0_, RfshRwCy70, dataIn2_0_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR0 MscR0(setRR_b, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, dataIn3_0_, incRfshRow_b, readR_9_, readR_2_, readR_0_, reset, writeR_7_);
not #(1) U527(hnl_503, hnl_504);
not #(1) I465(DAmode, DAmode_b);
not #(1) F94AB(hnl_505, gnd);
not #(1) F94AA(hnl_506, gnd);
not #(1) U458(reset_b, reset);
endmodule

module u5CASdy2 (readDelay, writeDelay, dataZ1, dataZ3, dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_);
output readDelay, writeDelay;
inout dataZ1, dataZ3;
input dataIn1, dataIn3, readR_2_, reset, reset_b, writeR_2_;
supply1 vdd;
supply0 gnd;
latSB #(1) I413(writeDelay, dataIn3, writeR_2_, reset);
latRB #(1) I396(readDelay, dataIn1, writeR_2_, reset_b);
nandpd2 U402(dataZ1, readDelay, readR_2_);
nandpd2 U395(dataZ3, writeDelay, readR_2_);
endmodule

module u5MscR5 (PDslow, ackWinDelay, dataZ0, dataZ1, dataZ3, dataIn0, readR_9_, readR_7_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeR_3_, writeR_2_);
output PDslow, ackWinDelay;
inout dataZ0, dataZ1, dataZ3;
input dataIn0, readR_9_, readR_7_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeR_3_, writeR_2_;
supply1 vdd;
supply0 gnd;
latRB #(1) I145(PDslow, dataIn0, writeR_3_, reset_b);
pdnull U144(dataZ1, readR_9_);
pdnull U143(dataZ0, readR_9_);
pdnull U142(dataZ3, readR_0_);
latSB #(1) I131(ackWinDelay, dataIn0, writeR_2_, reset);
nandpd1 U132(dataZ3, readR_7_);
nandpd1 U125(dataZ0, readR_0_);
nandpd2 U148(dataZ0, PDslow, readR_3_);
nandpd2 U127(dataZ0, ackWinDelay, readR_2_);
endmodule

module u5bit5 (ADR_4_, CASctCy56, DAR_4_, NSWE_5_, PDslow, RfshRwCy56, XferCntBorw56, ackWinDelay_2_, partialId_b_3_, pd2_5_, readDelay_2_, setDAR, writeDelay_2_, xcnt4321, dataZ0_5_, dataZ1_5_,
dataZ2_5_, dataZ3_5_, idHitA, rowHitLeftB, rowHitRightB, CASctCy45, DAmode_b, NSAdr_4_, RASaddrEnable, RfshRwCy45, XferCntBorw45, dataIn0_5_, dataIn1_5_, dataIn2_5_, dataIn3_5_, decXferCnt_b,
driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_2_, pd0_5_, pd1_5_, pd2_6_, pd3_5_, rclk, readR_10_, readR_9_,
readR_8_, readR_7_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_6_, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_,
writeR_5_, writeR_3_, writeR_2_, writeR_1_, xcnt_b_4_, xcnt_b_3_);
output ADR_4_, CASctCy56, DAR_4_, NSWE_5_, PDslow, RfshRwCy56, XferCntBorw56, ackWinDelay_2_, partialId_b_3_, pd2_5_, readDelay_2_, setDAR, writeDelay_2_, xcnt4321;
inout dataZ0_5_, dataZ1_5_, dataZ2_5_, dataZ3_5_, idHitA, rowHitLeftB, rowHitRightB;
input CASctCy45, DAmode_b, NSAdr_4_, RASaddrEnable, RfshRwCy45, XferCntBorw45, dataIn0_5_, dataIn1_5_, dataIn2_5_, dataIn3_5_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr,
driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_2_, pd0_5_, pd1_5_, pd2_6_, pd3_5_, rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_3_,
readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_6_, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_5_, writeR_3_, writeR_2_,
writeR_1_, xcnt_b_4_, xcnt_b_3_;
supply1 vdd;
supply0 gnd;
ltxBarB Addr32(Addr_32_, writeA0123, pd3_5_);
latBNcA I566(packetRowAddr_4_, RASaddrEnable, packetRowAddr_b_4_);
mux71x AdrMUX4(ADR_4_, ColAdr_4_, NSAdr_4_, packetRowAddr_4_, rfshRowAddr_4_, bank0RowAddr_4_, bank1RowAddr_4_, testBD_6_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_507, restoreBank0,
restoreBank1, DAmode);
nand #(0) U561(hnl_508, xcnt_b_1_, xcnt_b_2_, xcnt_b_3_, xcnt_b_4_);
u5NSWErg NSWErg5(NSWE_5_, selectEven_5_, loadNSWE, pd2_5_, pd3_5_, rclk, unloadNSWE);
not #(1) I544(DAmode, DAmode_b);
nor #(1) I540(hnl_507, driveRfshAddr_b, restoreBank0, restoreBank1);
u5id Id23_32(id_32_, id_23_, dataZ0_5_, dataZ2_5_, idHitA, partialId_b_2_, Addr_32_, dataIn0_5_, dataIn2_5_, eval, readR_1_, reset_b, writeR_1_);
u5DARbit DARbit4(DAR_4_, loadDAR, DAmode, setDAR, testBD_6_);
not #(1) U510(ColAdr_4_, net893);
countdn Count5(XferCntBorw56, xcnt_b_2_, decXferCnt_b, n8, writeA45, pd3_5_);
countdn Count4(n8, xcnt_b_1_, decXferCnt_b, XferCntBorw45, writeA45, pd2_5_);
countup Col_4_(CASctCy56, net893, incColAdr_b, CASctCy45, writeA0123x, pd0_5_);
u5Rhit Rhit_4_(bank0RowAddr_4_, bank1RowAddr_4_, dataZ0_5_, dataZ2_5_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_4_, packetRowAddr_b_4_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr4(adrSelReg_4_, partialId_b_3_, packetRowAddr_b_4_, dataZ0_5_, dataIn0_5_, pd1_5_, pd2_6_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw4(RfshRwCy56, rfshRowAddr_4_, dataZ0_5_, RfshRwCy45, dataIn0_5_, incRfshRow_b, readR_5_, writeR_5_);
u5CASdy2 CASdy2(readDelay_2_, writeDelay_2_, dataZ1_5_, dataZ3_5_, dataIn1_5_, dataIn3_5_, readR_2_, reset, reset_b, writeR_2_);
u5MscR5 MscR5(PDslow, ackWinDelay_2_, dataZ0_5_, dataZ1_5_, dataZ3_5_, dataIn0_5_, readR_9_, readR_7_, readR_3_, readR_2_, readR_0_, reset, reset_b, writeR_3_, writeR_2_);
not #(1) U519(hnl_509, testBD_7_);
not #(1) I562(xcnt4321, hnl_508);
not #(1) U513(setDAR, hnl_509);
not #(1) U505(reset_b, reset);
endmodule

module u5RstCtr (PD64after, clearCount_b, endPowerDown_b, reset, resetDAmode_b, turboDLL_b, DAmode_b, PDreq2, PDslow, PON, Rx_2, rawBE_b);
output PD64after, clearCount_b, endPowerDown_b, reset, resetDAmode_b, turboDLL_b;
input DAmode_b, PDreq2, PDslow, PON, Rx_2, rawBE_b;
supply1 vdd;
supply0 gnd;
not #(1) U258(reset_b, hnl_510);
invFF U257(reset, reset_b);
nor #(1) U251(hnl_511, PD64after, PDreq2_b, forceCounting_b);
nand #(1) U260(hnl_512, PON, PON);
nand #(1) U249(clearCount, hnl_513, PON);
not #(1) U261(resetDAmode_b, hnl_512);
not #(1) U246(endPowerDown_b, hnl_514);
not #(1) U252(turboDLL_b, hnl_511);
not #(1) U247(clearCount_b, clearCount);
not #(1) U245(PD64after, hnl_515);
nor #(1) U242(hnl_516, Rx_512, PDreq2_b);
srff I250(hnl_515, PDreq2, hnl_517);
srff I241(forceCounting_b, hnl_516, endPowerDown_b);
nand #(1) U259(countEq224_b, Rx_256, Rx_128, Rx_64);
nand #(1) U238(countEq76_b, Rx_128, Rx_16, Rx_8);
not #(1) U239(Rx_512_b, Rx_512);
not #(1) U230(PDreq2_b, PDreq2);
not #(1) U229(localClearCount_b, clearCount);
nand #(1) U240(hnl_513, rawBE_b, forceCounting_b);
oai21A U227(hnl_514, clearCount, finishPowerDown_b, reset_b);
mux21 #(1) I237(finishPowerDown_b, countEq12_b, countEq160_b, PDslow);
mux21 #(1) I221(hnl_517, countEq76_b, countEq224_b, PDslow);
ffBNcRA I214(Rx_512, Rx_256, Rx_512, localClearCount_b);
ffBNcRA I213(Rx_256, Rx_128, Rx_256, localClearCount_b);
ffBNcRA I212(Rx_128, Rx_64, Rx_128, localClearCount_b);
ffBNcRA I211(Rx_64, Rx_32, Rx_64, localClearCount_b);
ffBNcRA I210(Rx_32, Rx_16, Rx_32, localClearCount_b);
ffBNcRA I209(Rx_16, Rx_8, Rx_16, localClearCount_b);
ffBNcRA I208(Rx_8, Rx_4, Rx_8, localClearCount_b);
ffBNcRA I207(Rx_4, Rx_2, Rx_4, localClearCount_b);
nand #(1) U197(hnl_510, Rx_512_b, PON, DAmode_b);
nand #(1) U226(countEq160_b, Rx_256, Rx_64);
nand #(1) U224(countEq12_b, Rx_16, Rx_8);
endmodule

module u5BEminC (standby, stbybWak, DLLByPassMode_b, DeviceBusy, powerDownMode, rawBE_b, rclk, rdPipeBusy_b, reset_b);
output standby, stbybWak;
input DLLByPassMode_b, DeviceBusy, powerDownMode, rawBE_b, rclk, rdPipeBusy_b, reset_b;
supply1 vdd;
supply0 gnd;
nand #(1) I215(ksink, rawBE_b, reset_b);
nand #(1) I212(standby_b, rdPipeBusy_b, BEcnt, hnl_469);
not #(1) U214(standby, standby_b);
nand #(1) I227(stbybWak, DLLByPassMode_b, standby, wake_b);
not #(1) U250(reset, reset_b);
not #(1) U243(hnl_518, powerDownMode);
ffSB I249(BEcnt, rclk, countIs15or0, reset);
ffSB I233(wake, rclk, hnl_483, ksink);
nor #(1) I228(hnl_519, ksink, wake);
not #(1) U222(wake_b, wake);
ffB #(1) I219(BEm4, rclk, hnl_520);
oai21A U211(hnl_520, countIs15or0, hnl_521, hnl_519);
ffBarA #(1) I208(BEm3, rclk, hnl_510);
xor #(1) U203(hnl_521, BEm3, BEm4);
nor #(1) U199(countIs15or0, BEm4, BEm1, BEm2);
nand #(1) U252(hnl_469, wake, reset_b);
nand #(1) U241(hnl_483, hnl_484, hnl_516);
nand #(1) U235(hnl_484, countIs15or0, wake);
nand #(1) U221(hnl_522, wake_b, BEm1);
nand #(1) U198(hnl_523, wake_b, BEm4);
nand #(1) U197(hnl_510, wake_b, BEm2);
nand #(1) U242(hnl_516, hnl_518, DeviceBusy);
ffBarB #(1) I195(BEm1, rclk, hnl_523);
ffBarB #(1) I194(BEm2, rclk, hnl_522);
endmodule

module u5PreScl (checkskip, evalCurrentCnt, sampleskip, mclk_div16, reset);
output checkskip, evalCurrentCnt, sampleskip;
input mclk_div16, reset;
supply1 vdd;
supply0 gnd;
oai21A U309(hnl_524, evalCurrentCnt_b, s1, hnl_525);
not #(1) U306(sampleskip, hnl_526);
not #(1) U305(checkskip, hnl_527);
ffRA I292(s0, mclk_div16, reset_b, s1);
ffSB I293(s1, mclk_div16, hnl_528, reset);
nand #(1) U291(evalCurrentCnt, evalCurrentCnt_b, mclk_div16);
ffBarRA I290(evalCurrentCnt_b, mclk_div16, preRsh, reset_b);
nand #(1) U300(hnl_526, s1, s0);
nand #(1) U283(hnl_529, q0, reset_b);
nor #(1) I301(hnl_527, s1, s0);
nor #(1) U187(hnl_530, hnl_529, hnl_531);
nand #(1) U280(preRsh, q2, q1, hnl_530);
ffRC I278(q0, mclk_div16, reset_b, hnl_125);
not #(1) U188(reset_b, reset);
nand #(0) U178(hnl_531, q3, q5, q6, q7);
not #(1) U310(hnl_528, hnl_524);
not #(1) U299(hnl_525, s0);
not #(1) U279(hnl_125, q0);
latBarSB #(1) I175(q5, hnl_532, q4, clear2);
latBarSB #(1) I193(q1, hnl_533, q0, reset);
latBarSB #(1) I189(q3, hnl_534, q2, clear2);
latNBarA #(1) I198(hnl_533, hnl_535, q0);
latNBarA #(1) I192(hnl_532, hnl_536, q4);
latNBarA #(1) I195(q7, hnl_537, q6);
latNBarA #(1) I197(q2, q1, q0);
latNBarA #(1) I182(q6, q5, q4);
latNBarA #(1) I199(q4, q3, q2);
latNBarA #(1) I183(hnl_534, hnl_538, q2);
latSA #(1) I201(hnl_536, q6, q4, clear2);
latSA #(1) I202(hnl_538, q4, q2, clear2);
latSA #(1) I176(hnl_535, q2, q0, reset);
latSA #(1) I180(hnl_537, q7, q6, clear2);
srff I177(clear2, reset_b, q1);
endmodule

module u5BElog (PD64after, checkskip, clearCount_b, endPowerDown_b, evalCurrentCnt, reset, resetDAmode_b, sampleskip, standby, stbybWak, turboDLL_b, DAmode_b, DLLByPassMode_b, DeviceBusy, PDreq2,
PDslow, PON, Rx_2, mclk_div16, powerDownMode, rawBE_b, rclk, rdPipeBusy_b);
output PD64after, checkskip, clearCount_b, endPowerDown_b, evalCurrentCnt, reset, resetDAmode_b, sampleskip, standby, stbybWak, turboDLL_b;
input DAmode_b, DLLByPassMode_b, DeviceBusy, PDreq2, PDslow, PON, Rx_2, mclk_div16, powerDownMode, rawBE_b, rclk, rdPipeBusy_b;
supply1 vdd;
supply0 gnd;
nor #(1) F94CE(hnl_539, gnd, gnd);
not #(1) F94CB(hnl_540, gnd);
not #(1) F94CA(hnl_541, gnd);
nand #(1) F94CD(hnl_542, gnd, gnd);
nand #(1) F94CC(hnl_543, gnd, gnd);
u5RstCtr RstCtr(PD64after, clearCount_b, endPowerDown_b, reset, resetDAmode_b, turboDLL_b, DAmode_b, PDreq2, PDslow, PON, Rx_2, rawBE_b);
u5BEminC BEminC(standby, stbybWak, DLLByPassMode_b, DeviceBusy, powerDownMode, rawBE_b, rclk, rdPipeBusy_b, reset_b);
u5PreScl PreScl(checkskip, evalCurrentCnt, sampleskip, mclk_div16, reset);
not #(1) U71(reset_b, reset);
endmodule

module u5WEgen (ADRx_6_, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, earlyDone, loadNSWE, ADR_6_, Addr_2_, Addr_1_, Addr_0_, CASstate1_b, Count_2_, Count_1_, Count_0_, DAmode_b, Last_b,
NSOp, NSWE_7_, NSWE_6_, NSWE_5_, NSWE_4_, NSWE_3_, NSWE_2_, NSWE_1_, NSWE_0_, RASB, RawLast, TestWE, firstCycWE_b, loadLast, preloadNSWE, rclk, regOp, reset, trueCASstate1_b, writeA0123x,
writeMaskedNSOp_b, writeOp_b, xcnt4321, xcnt_b_0_);
output ADRx_6_, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, earlyDone, loadNSWE;
input ADR_6_, Addr_2_, Addr_1_, Addr_0_, CASstate1_b, Count_2_, Count_1_, Count_0_, DAmode_b, Last_b, NSOp, NSWE_7_, NSWE_6_, NSWE_5_, NSWE_4_, NSWE_3_, NSWE_2_, NSWE_1_, NSWE_0_, RASB, RawLast,
TestWE, firstCycWE_b, loadLast, preloadNSWE, rclk, regOp, reset, trueCASstate1_b, writeA0123x, writeMaskedNSOp_b, writeOp_b, xcnt4321, xcnt_b_0_;
supply1 vdd;
supply0 gnd;
ffB #(1) I341(hnl_544, rclk, hnl_545);
ltxRB F94BD(hnl_546, gnd, gnd, vdd);
nand #(1) F94AZ(hnl_547, gnd, gnd);
nand #(1) F94AY(hnl_548, gnd, gnd);
not #(1) F94AX(hnl_549, gnd);
nor #(1) U320(hnl_545, writeA0123x, reset, RASB);
aoi21A #(1) U339(hnl_487, xcnt_b_0_, xcnt4321, regOp);
ffA I328(hnl_550, hnl_487, rclk);
oai21A U318(hnl_551, CASstate1_b, Last_b, hnl_552);
ffRC I355(earlyDone, rclk, hnl_544, hnl_553);
ffRC I317(earlyDone, rclk, hnl_544, hnl_553);
invFF U314(loadNSWE, preloadNSWE);
not #(1) U311(ADRx_6_, hnl_528);
nor #(1) U305(hnl_554, NSOp, writeOp_b);
not #(1) U304(lastMaskEnable, hnl_555);
nand #(1) U303(hnl_555, xcnt_b_0_, xcnt4321, hnl_554);
ffC #(1) I297(firstMaskEnable, rclk, hnl_556);
nor #(1) I288(hnl_556, firstCycWE_b, NSOp, writeOp_b);
DAff I286_0_(ubWE_7_, rclk, assertWE, net1378_0_, DAmode_b);
DAff I286_1_(ubWE_6_, rclk, assertWE, net1378_1_, DAmode_b);
DAff I286_2_(ubWE_5_, rclk, assertWE, net1378_2_, DAmode_b);
DAff I286_3_(ubWE_4_, rclk, assertWE, net1378_3_, DAmode_b);
DAff I286_4_(ubWE_3_, rclk, assertWE, net1378_4_, DAmode_b);
DAff I286_5_(ubWE_2_, rclk, assertWE, net1378_5_, DAmode_b);
DAff I286_6_(ubWE_1_, rclk, assertWE, net1378_6_, DAmode_b);
DAff I286_7_(ubWE_0_, rclk, assertWE, net1378_7_, DAmode_b);
nand #(1) U327(hnl_557, Last_b, hnl_41, hnl_550);
nand #(1) U298(hnl_466, Count_2_, Count_1_, Count_0_);
nand #(1) U283(hnl_529, Addr_b_2_, Addr_b_1_, Addr_b_0_);
not #(1) U262(assertWE, hnl_558);
not #(1) U280_0_(WE_7_, ubWE_7_);
not #(1) U280_1_(WE_6_, ubWE_6_);
not #(1) U280_2_(WE_5_, ubWE_5_);
not #(1) U280_3_(WE_4_, ubWE_4_);
not #(1) U280_4_(WE_3_, ubWE_3_);
not #(1) U280_5_(WE_2_, ubWE_2_);
not #(1) U280_6_(WE_1_, ubWE_1_);
not #(1) U280_7_(WE_0_, ubWE_0_);
mux21 #(1) I319(hnl_553, hnl_557, hnl_551, trueCASstate1_b);
mux21 #(1) I261_0_(net1378_0_, NSWE_7_, rawWE_b_7_, writeMaskedNSOp_b);
mux21 #(1) I261_1_(net1378_1_, NSWE_6_, rawWE_b_6_, writeMaskedNSOp_b);
mux21 #(1) I261_2_(net1378_2_, NSWE_5_, rawWE_b_5_, writeMaskedNSOp_b);
mux21 #(1) I261_3_(net1378_3_, NSWE_4_, rawWE_b_4_, writeMaskedNSOp_b);
mux21 #(1) I261_4_(net1378_4_, NSWE_3_, rawWE_b_3_, writeMaskedNSOp_b);
mux21 #(1) I261_5_(net1378_5_, NSWE_2_, rawWE_b_2_, writeMaskedNSOp_b);
mux21 #(1) I261_6_(net1378_6_, NSWE_1_, rawWE_b_1_, writeMaskedNSOp_b);
mux21 #(1) I261_7_(net1378_7_, NSWE_0_, rawWE_b_0_, writeMaskedNSOp_b);
nand #(0) I282(Mask_6_, Addr_2_, Addr_1_, Addr_0_, firstMaskEnable);
nand #(0) I258(Mask_9_, Count_b_2_, Count_b_1_, Count_b_0_, lastMaskEnable);
not #(1) U323(hnl_552, earlyDone);
not #(1) U310(hnl_528, ADR_6_);
not #(1) U309(rawWE_b_7_, Mask_15_);
not #(1) U307(hnl_558, TestWE);
not #(1) U289(rawWE_b_0_, Mask_0_);
not #(1) U295_0_(Addr_b_2_, Addr_2_);
not #(1) U295_1_(Addr_b_1_, Addr_1_);
not #(1) U295_2_(Addr_b_0_, Addr_0_);
not #(1) U255_0_(Count_b_2_, Count_2_);
not #(1) U255_1_(Count_b_1_, Count_1_);
not #(1) U255_2_(Count_b_0_, Count_0_);
nand #(1) U330(hnl_41, loadLast, RawLast);
nand #(1) U300(rawWE_b_1_, Mask_9_, Mask_1_);
nand #(1) U293(rawWE_b_4_, Mask_12_, Mask_4_);
nand #(1) U292(hnl_559, Addr_b_2_, Addr_b_0_);
nand #(1) U287(hnl_560, Count_1_, Count_0_);
nand #(1) U285(rawWE_b_5_, Mask_13_, Mask_5_);
nand #(1) U278(hnl_127, Count_2_, Count_0_);
nand #(1) U273(hnl_561, Count_2_, Count_1_);
nand #(1) U269(rawWE_b_6_, Mask_14_, Mask_6_);
nand #(1) U267(hnl_562, Addr_b_1_, Addr_b_0_);
nand #(1) U266(rawWE_b_2_, Mask_10_, Mask_2_);
nand #(1) U265(hnl_465, Addr_b_2_, Addr_b_1_);
nand #(1) U259(rawWE_b_3_, Mask_11_, Mask_3_);
nand #(1) I302(Mask_14_, hnl_561, lastMaskEnable);
nand #(1) I299(Mask_1_, hnl_465, firstMaskEnable);
nand #(1) I291(Mask_0_, hnl_529, firstMaskEnable);
nand #(1) I275(Mask_15_, hnl_466, lastMaskEnable);
nand #(1) I253(Mask_3_, Addr_2_, firstMaskEnable);
nand #(1) I251(Mask_12_, Count_b_2_, lastMaskEnable);
nand #(1) I277(Mask_10_, Count_b_2_, Count_b_1_, lastMaskEnable);
nand #(1) I274(Mask_4_, hnl_562, Addr_2_, firstMaskEnable);
nand #(1) I263(Mask_13_, hnl_561, hnl_127, lastMaskEnable);
nand #(1) I257(Mask_11_, hnl_560, Count_b_2_, lastMaskEnable);
nand #(1) I250(Mask_2_, hnl_465, hnl_559, firstMaskEnable);
nand #(1) I248(Mask_5_, Addr_2_, Addr_1_, firstMaskEnable);
endmodule

module bufEE (Y, A);
output Y;
input A;
supply1 vdd;
supply0 gnd;
not #(1) I17(hnl_33, A);
not #(1) U9(Y, hnl_33);
endmodule

module u5MscR2 (autoSkipEn, powerDownReq_b, dataZ0, dataZ1, dataZ2, dataZ3, dataIn0, dataIn3, endPowerDown_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, writeR_7_, writeR_3_);
output autoSkipEn, powerDownReq_b;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn0, dataIn3, endPowerDown_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, writeR_7_, writeR_3_;
supply1 vdd;
supply0 gnd;
nandpd2 U166(dataZ0, autoSkipEn, readR_3_);
latSB #(1) I162(autoSkipEn, dataIn0, writeR_3_, reset);
pdnull U126(dataZ3, readR_2_);
pdnull U125(dataZ1, readR_2_);
pdnull U161(dataZ1, readR_9_);
pdnull U160(dataZ0, readR_9_);
not #(1) U142(powerDownReq_b, powerDownReq);
latRB #(1) I129(powerDownReq, dataIn3, writeR_7_, endPowerDown_b);
nandpd1 U138(dataZ2, readR_9_);
nandpd1 U225(dataZ0, readR_0_);
endmodule

module u5bit2 (ADR_1_, BSEL, CASctCy23, Count_0_, DAR_1_, NSWE_2_, RASctCy21, RfshRwCy23, autoSkipEn, localBSEL, packetBSELx, partialId_b_0_, pd2_2_, powerDownReq_b, rfshCout_1_, dataZ0_2_,
dataZ1_2_, dataZ2_2_, dataZ3_2_, idHitB, rowHitLeftA, rowHitRightA, CASctCy12, DAmode_b, NSAdr_1_, RASaddrEnable, RAScount_b, RASctCy32, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_,
RfshRwCy12, dataIn0_2_, dataIn1_2_, dataIn2_2_, dataIn3_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, endPowerDown_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE,
packetBSEL, pd0_2_, pd1_2_, pd2_3_, pd3_2_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR,
testBD_3_, testBSEL, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_3_, writeR_1_);
output ADR_1_, BSEL, CASctCy23, Count_0_, DAR_1_, NSWE_2_, RASctCy21, RfshRwCy23, autoSkipEn, localBSEL, packetBSELx, partialId_b_0_, pd2_2_, powerDownReq_b, rfshCout_1_;
inout dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, idHitB, rowHitLeftA, rowHitRightA;
input CASctCy12, DAmode_b, NSAdr_1_, RASaddrEnable, RAScount_b, RASctCy32, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy12, dataIn0_2_, dataIn1_2_, dataIn2_2_, dataIn3_2_,
driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, endPowerDown_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, packetBSEL, pd0_2_, pd1_2_, pd2_3_, pd3_2_, rclk, readR_10_,
readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_3_, testBSEL, unloadNSWE, updateRowAddr, writeA45,
writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
invEE U545(localBSEL, hnl_57);
latSRB rowExpRest2(rowExpRest_2_, dataIn3_2_, writeR_6_, vdd, reset);
latSRB rowImpRest2(rowImpRest_2_, dataIn2_2_, writeR_6_, vdd, reset);
latSRB rowAcc2(rowAcc_2_, dataIn1_2_, writeR_6_, reset_b, gnd);
latSRB rowPre2(rowPre_2_, dataIn0_2_, writeR_6_, reset_b, gnd);
ltxBarB Count0(Count_b_0_, writeA45, pd3_2_);
ltxBarB Addr29(Addr_29_, writeA0123, pd3_2_);
latBNcA I577(packetRowAddr_1_, RASaddrEnable, packetRowAddr_b_1_);
mux71x AdrMUX1(ADR_1_, ColAdr_1_, NSAdr_1_, packetRowAddr_1_, rfshRowAddr_1_, bank0RowAddr_1_, bank1RowAddr_1_, testBD_3_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_563, restoreBank0,
restoreBank1, DAmode);
mux71x BSMUX(BSEL, hnl_564, hnl_564, hnl_564, rfshBSEL, gnd, vdd, testBSEL, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_563, restoreBank0, restoreBank1, DAmode);
u5NSWErg NSWErg2(NSWE_2_, selectEven_2_, loadNSWE, pd2_2_, pd3_2_, rclk, unloadNSWE);
bufEE U571(packetBSELx, hnl_565);
mux21 #(1) I569(hnl_565, hnl_396, hnl_566, driveRfshAddr_b);
not #(1) I557(DAmode, DAmode_b);
nor #(1) I553(hnl_563, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U549(rfshCout_1_, RfshRwCy23);
not #(1) U547(Count_0_, Count_b_0_);
mux41 #(1) I537(cnt2, rowPre_2_, rowAcc_2_, rowImpRest_2_, rowExpRest_2_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
nandpd2 U524(dataZ0_2_, rowPre_2_, readR_6_);
nandpd2 U536(dataZ3_2_, rowExpRest_2_, readR_6_);
nandpd2 U530(dataZ2_2_, rowImpRest_2_, readR_6_);
nandpd2 U528(dataZ1_2_, rowAcc_2_, readR_6_);
u5DARbit DARbit1(DAR_1_, loadDAR, DAmode, setDAR, testBD_3_);
latB I572(hnl_396, rfshBSEL, driveRfshAddr_b);
latB I570(hnl_566, packetBSEL, writeA45);
latB I508(hnl_564, packetBSEL, writeA45);
not #(1) U550(ColAdr_1_, net3743);
countup RASct2(RASctCy21, RAScnt_2_, RAScount_b, RASctCy32, RASldCount, cnt2);
countup Col_1_(CASctCy23, net3743, incColAdr_b, CASctCy12, writeA0123x, pd0_2_);
u5idA Id29(id_29_, dataZ2_2_, idHitB, Addr_29_, dataIn2_2_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_1_(bank0RowAddr_1_, bank1RowAddr_1_, dataZ0_2_, dataZ2_2_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_1_, packetRowAddr_b_1_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr1(adrSelReg_1_, partialId_b_0_, packetRowAddr_b_1_, dataZ0_2_, dataIn0_2_, pd1_2_, pd2_3_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw1(RfshRwCy23, rfshRowAddr_1_, dataZ0_2_, RfshRwCy12, dataIn0_2_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR2 MscR2(autoSkipEn, powerDownReq_b, dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, dataIn0_2_, dataIn3_2_, endPowerDown_b, readR_9_, readR_3_, readR_2_, readR_0_, reset, writeR_7_, writeR_3_);
not #(1) U575(hnl_57, BSEL);
not #(1) U463(reset_b, reset);
endmodule

module u5MscR6 (control_6_, control_2_, control_1_, control_0_, dataZ0, dataZ1, dataZ2, dataZ3, dataIn0, dataIn1, dataIn2, dataIn3, ictrl_2_, ictrl_1_, ictrl_0_, readR_9_, readR_7_, readR_3_,
readR_0_, reset, writeR_3_);
output control_6_, control_2_, control_1_, control_0_;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn0, dataIn1, dataIn2, dataIn3, ictrl_2_, ictrl_1_, ictrl_0_, readR_9_, readR_7_, readR_3_, readR_0_, reset, writeR_3_;
supply1 vdd;
supply0 gnd;
pdnull U148(dataZ1, readR_9_);
pdnull U147(dataZ0, readR_9_);
pdnull U146(dataZ3, readR_0_);
latBarSB #(1) I143_0_(control_6_, dataIn0, writeR_3_, reset);
latBarSB #(1) I143_1_(control_2_, dataIn1, writeR_3_, reset);
latBarSB #(1) I143_2_(control_1_, dataIn2, writeR_3_, reset);
latBarSB #(1) I143_3_(control_0_, dataIn3, writeR_3_, reset);
nandpd1 U150(dataZ3, readR_7_);
nandpd1 U149(dataZ2, readR_7_);
nandpd1 U136(dataZ1, readR_7_);
nandpd2 U130_0_(dataZ1, ictrl_2_, readR_3_);
nandpd2 U130_1_(dataZ2, ictrl_1_, readR_3_);
nandpd2 U130_2_(dataZ3, ictrl_0_, readR_3_);
nandpd2 U263(dataZ0, control_6_, readR_3_);
endmodule

module u5bit6 (ADR_5_, CASctCy67, NSWE_6_, RfshRwCy67, control_6_, control_2_, control_1_, control_0_, mclkOn, partialId_b_4_, pd2_6_, xcnt_b_4_, xcnt_b_3_, dataZ0_6_, dataZ1_6_, dataZ2_6_,
dataZ3_6_, idHitA, rowHitLeftB, rowHitRightB, CASctCy56, DAmode_b, NSAdr_5_, RASaddrEnable, RfshRwCy56, XferCntBorw56, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_, decXferCnt_b, done, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, evalCurrentCnt, gated_mclk, ictrl_2_, ictrl_1_, ictrl_0_, incColAdr_b, incRfshRow_b, loadNSWE, localBSEL, partialId_b_3_, pd0_6_, pd1_6_,
pd2_7_, pd3_6_, rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_3_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123,
writeA0123x, writeR_8_, writeR_5_, writeR_3_, writeR_1_);
output ADR_5_, CASctCy67, NSWE_6_, RfshRwCy67, control_6_, control_2_, control_1_, control_0_, mclkOn, partialId_b_4_, pd2_6_, xcnt_b_4_, xcnt_b_3_;
inout dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_, idHitA, rowHitLeftB, rowHitRightB;
input CASctCy56, DAmode_b, NSAdr_5_, RASaddrEnable, RfshRwCy56, XferCntBorw56, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_, decXferCnt_b, done, driveColAdr, driveNSAdr, drivePacketRASaddr,
driveRfshAddr_b, eval, evalCurrentCnt, gated_mclk, ictrl_2_, ictrl_1_, ictrl_0_, incColAdr_b, incRfshRow_b, loadNSWE, localBSEL, partialId_b_3_, pd0_6_, pd1_6_, pd2_7_, pd3_6_, rclk, readR_10_,
readR_9_, readR_8_, readR_7_, readR_5_, readR_3_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_5_,
writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
srff I563(hnl_567, evalCurrentCnt, hnl_568);
nor #(1) U564(hnl_67, hnl_567, reset);
nor #(1) U562(hnl_568, hnl_569, reset);
ffA I561(hnl_569, hnl_570, gated_mclk);
ffA I560(hnl_570, hnl_571, gated_mclk);
ffA I559(hnl_571, done, gated_mclk);
ltxBarB Addr33(Addr_33_, writeA0123, pd3_6_);
latBNcA I551(packetRowAddr_5_, RASaddrEnable, packetRowAddr_b_5_);
mux71x AdrMUX5(ADR_5_, ColAdr_5_, NSAdr_5_, packetRowAddr_5_, rfshRowAddr_5_, bank0RowAddr_5_, bank1RowAddr_5_, testBD_7_, driveColAdr, driveNSAdr, drivePacketRASaddr, hnl_572, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg6(NSWE_6_, selectEven_6_, loadNSWE, pd2_6_, pd3_6_, rclk, unloadNSWE);
not #(1) I535(DAmode, DAmode_b);
nor #(1) I531(hnl_572, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) U504(ColAdr_5_, net701);
countdn Count7(hnl_573, xcnt_b_4_, decXferCnt_b, n8, writeA45, pd3_6_);
countdn Count6(n8, xcnt_b_3_, decXferCnt_b, XferCntBorw56, writeA45, pd2_6_);
countup Col_5_(CASctCy67, net701, incColAdr_b, CASctCy56, writeA0123x, pd0_6_);
u5id Id24_33(id_33_, id_24_, dataZ0_6_, dataZ2_6_, idHitA, partialId_b_3_, Addr_33_, dataIn0_6_, dataIn2_6_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_5_(bank0RowAddr_5_, bank1RowAddr_5_, dataZ0_6_, dataZ2_6_, rowHitLeftB, rowHitRightB, localBSEL, eval, packetRowAddr_5_, packetRowAddr_b_5_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr5(adrSelReg_5_, partialId_b_4_, packetRowAddr_b_5_, dataZ0_6_, dataIn0_6_, pd1_6_, pd2_7_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw5(RfshRwCy67, rfshRowAddr_5_, dataZ0_6_, RfshRwCy56, dataIn0_6_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR6 MscR6(control_6_, control_2_, control_1_, control_0_, dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_, ictrl_2_, ictrl_1_, ictrl_0_, readR_9_,
readR_7_, readR_3_, readR_0_, reset, writeR_3_);
not #(1) U565(mclkOn, hnl_67);
not #(1) U499(reset_b, reset);
endmodule

module u5MscR1 (deviceEnableMode, dataZ0, dataZ1, dataZ2, dataZ3, dataIn0, readR_9_, readR_3_, readR_2_, reset_b, writeR_3_);
output deviceEnableMode;
inout dataZ0, dataZ1, dataZ2, dataZ3;
input dataIn0, readR_9_, readR_3_, readR_2_, reset_b, writeR_3_;
supply1 vdd;
supply0 gnd;
not #(1) U153(deviceEnableMode, hnl_574);
not #(1) U152(hnl_574, hnl_575);
pdnull U151(dataZ1, readR_9_);
pdnull U150(dataZ0, readR_9_);
latRB #(1) I132(hnl_575, dataIn0, writeR_3_, reset_b);
nandpd1 U162(dataZ1, readR_2_);
nandpd1 U161(dataZ3, readR_2_);
nandpd1 U129(dataZ2, readR_2_);
nandpd1 U128(dataZ0, readR_2_);
nandpd2 U131(dataZ0, hnl_575, readR_3_);
endmodule

module u5bit1 (ADR_8_, ADR_0_, Addr_1_, CASctCy12, DAR_0_, NSWE_1_, RASctCy10, RfshRwCy12, deviceEnableMode, packetBSEL, testBSEL, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, idHitB, rowHitLeftA,
rowHitRightA, BIMDI, DAmode_b, NSAdr_0_, RASaddrEnable, RAScount_b, RASctCy21, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy01, dataIn0_1_, dataIn1_1_, dataIn2_1_, dataIn3_1_,
driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, muxBS8, pd0_1_, pd1_1_, pd2_1_, pd2_2_, pd3_1_, rclk, readR_10_, readR_9_,
readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_1_, testBD_2_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x,
writeR_8_, writeR_6_, writeR_5_, writeR_3_, writeR_1_);
output ADR_8_, ADR_0_, Addr_1_, CASctCy12, DAR_0_, NSWE_1_, RASctCy10, RfshRwCy12, deviceEnableMode, packetBSEL, testBSEL;
inout dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, idHitB, rowHitLeftA, rowHitRightA;
input BIMDI, DAmode_b, NSAdr_0_, RASaddrEnable, RAScount_b, RASctCy21, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy01, dataIn0_1_, dataIn1_1_, dataIn2_1_, dataIn3_1_, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, eval, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, muxBS8, pd0_1_, pd1_1_, pd2_1_, pd2_2_, pd3_1_, rclk, readR_10_, readR_9_, readR_8_,
readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_1_, testBD_2_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_,
writeR_6_, writeR_5_, writeR_3_, writeR_1_;
supply1 vdd;
supply0 gnd;
latSRB rowExpRest3(rowExpRest_3_, dataIn3_1_, writeR_6_, reset_b, gnd);
latSRB rowImpRest3(rowImpRest_3_, dataIn2_1_, writeR_6_, vdd, reset);
latSRB rowAcc3(rowAcc_3_, dataIn1_1_, writeR_6_, vdd, reset);
latSRB rowPre3(rowPre_3_, dataIn0_1_, writeR_6_, reset_b, gnd);
ltxBarB Addr1(Addr_b_1_, writeA45, pd3_1_);
latBNcA I569_0_(packetRowAddr_8_, RASaddrEnable, packetRowAddr_b_8_);
latBNcA I569_1_(packetRowAddr_0_, RASaddrEnable, packetRowAddr_b_0_);
mux71x AdrMUX8(ADR_8_, gnd, gnd, packetRowAddr_8_, rfshRowAddr_8_, bank0RowAddr_8_, bank1RowAddr_8_, testADR8, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfAddr, restoreBank0, restoreBank1,
DAmode);
mux71x AdrMUX0(ADR_0_, ColAdr_0_, NSAdr_0_, packetRowAddr_0_, rfshRowAddr_0_, bank0RowAddr_0_, bank1RowAddr_0_, testBD_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfAddr, restoreBank0,
restoreBank1, DAmode);
u5NSWErg NSWErg1(NSWE_1_, selectEven_1_, loadNSWE, pd2_1_, pd3_1_, rclk, unloadNSWE);
not #(1) I562(DAmode, DAmode_b);
nor #(1) I558(driveRfAddr, driveRfshAddr_b, restoreBank0, restoreBank1);
not #(1) I555(testADR8, hnl_401);
not #(1) U554(testBSEL, hnl_576);
invEEbuf U553(packetBSEL, n1_b);
not #(1) U552(Addr_1_, Addr_b_1_);
nand #(1) U547(hnl_577, muxBS8, hnl_74);
mux21 #(1) I544(hnl_576, hnl_78, hnl_84, hnl_577);
mux21 #(1) I537(hnl_401, hnl_84, hnl_78, hnl_577);
DAff I533(hnl_578, hnl_80, hnl_75, testBD_1_, hnl_74);
mux41 #(1) I520(cnt3, rowPre_3_, rowAcc_3_, rowImpRest_3_, rowExpRest_3_, RASsel_0_, RASsel_1_, RASsel_2_, RASsel_3_);
not #(1) U548(hnl_75, rfshBSEL);
not #(1) U546(hnl_78, testBD_1_);
not #(1) U545(hnl_74, BIMDI);
not #(1) U543(hnl_80, loadDAR);
not #(1) U534(hnl_84, hnl_578);
nandpd2 U508(dataZ0_1_, rowPre_3_, readR_6_);
nandpd2 U519(dataZ3_1_, rowExpRest_3_, readR_6_);
nandpd2 U514(dataZ2_1_, rowImpRest_3_, readR_6_);
nandpd2 U512(dataZ1_1_, rowAcc_3_, readR_6_);
u5DARbit DARbit0(DAR_0_, loadDAR, DAmode, setDAR, testBD_2_);
not #(1) U480(ColAdr_0_, net4595);
countup RASct3(RASctCy10, RAScnt_3_, RAScount_b, RASctCy21, RASldCount, cnt3);
countup Col_0_(CASctCy12, net4595, incColAdr_b, gnd, writeA0123x, pd0_1_);
u5idA Id28(id_28_, dataZ2_1_, idHitB, partialId_b_7_, dataIn2_1_, eval, readR_1_, reset_b, writeR_1_);
u5Rhit Rhit_8_(bank0RowAddr_8_, bank1RowAddr_8_, dataZ1_1_, dataZ3_1_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_8_, packetRowAddr_b_8_, readR_10_, reset_b, updateRowAddr);
u5Rhit Rhit_0_(bank0RowAddr_0_, bank1RowAddr_0_, dataZ0_1_, dataZ2_1_, rowHitLeftA, rowHitRightA, localBSEL, eval, packetRowAddr_0_, packetRowAddr_b_0_, readR_10_, reset_b, updateRowAddr);
u5RASadr RASadr8(adrSelReg_8_, partialId_b_7_, packetRowAddr_b_8_, dataZ1_1_, dataIn1_1_, pd2_1_, pd3_1_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RASadr RASadr0(adrSelReg_0_, n1_b, packetRowAddr_b_0_, dataZ0_1_, dataIn0_1_, pd1_1_, pd2_2_, readR_8_, reset_b, writeA0123, writeR_8_);
u5RfshRw RfshRw8(dbIllegal4641_0_, rfshRowAddr_8_, dataZ2_1_, RfshRwCy01, dataIn2_1_, incRfshRow_b, readR_5_, writeR_5_);
u5RfshRw RfshRw0(RfshRwCy12, rfshRowAddr_0_, dataZ0_1_, gnd, dataIn0_1_, incRfshRow_b, readR_5_, writeR_5_);
u5MscR1 MscR1(deviceEnableMode, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, dataIn0_1_, readR_9_, readR_3_, readR_2_, reset_b, writeR_3_);
not #(1) U470(reset_b, reset);
endmodule

module u5StdCel (ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_, AGEGND, AGEING, BCOeven_b, BCOodd_b, BC_oe, BSEL, CAS, CMPF, CMPV, DAmode_b, DLLByPassMode_b, HVST, MPBT,
PDMD, RASB, REQ, ROLLC, RSTR, SDST, TestSOut, VCMNA, VRST, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, WML, WPBT, WRITE, ackWinOverD, chain_b, checkskip, clearCount_b, control_5_,
control_4_, control_3_, control_2_, control_1_, control_0_, deviceEnableMode, enableSOut, framePulseX, gated_mclk, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode,
powerOn, pwrdnRcvrs, reset, resetCap, runtclk, sampleskip, selRegData, standby, stbybWak, sytload_b, testLoad_b, turboDLL_b, writeA45, writeA0123, writeA0123x, writeD0123, writeD4567,
writeSenseAmpPipe, RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_,
RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_, RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_,
RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_,
RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_,
dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_,
dataZ3_2_, dataZ3_1_, dataZ3_0_, BEevenD, BEoddD, BIMDI, Last_b, OpX_1_, OpX_0_, PON, RCRED, RawLast, Rx_2, SInRaw_b, TestCAS, TestRASB, TestRSTR, VREG, Vrefin, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_,
WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_,
WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_,
WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_,
WDL8_1_, WDL8_0_, autoSkip, bcastWriteA, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_,
dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_,
dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, done, frameEnableX, framePulse_b, frameRaw_b, lowVref, mclk, mtclk, opcode_b_2_, opcode_b_1_, pd0_8_, pd0_7_, pd0_6_, pd0_5_,
pd0_4_, pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_,
pd3_6_, pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_, pd3_0_, rawBE_b, rclk, runclk_b, slow, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_);
output ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_, AGEGND, AGEING, BCOeven_b, BCOodd_b, BC_oe, BSEL, CAS, CMPF, CMPV, DAmode_b, DLLByPassMode_b, HVST, MPBT, PDMD, RASB,
REQ, ROLLC, RSTR, SDST, TestSOut, VCMNA, VRST, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, WML, WPBT, WRITE, ackWinOverD, chain_b, checkskip, clearCount_b, control_5_, control_4_,
control_3_, control_2_, control_1_, control_0_, deviceEnableMode, enableSOut, framePulseX, gated_mclk, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, powerOn,
pwrdnRcvrs, reset, resetCap, runtclk, sampleskip, selRegData, standby, stbybWak, sytload_b, testLoad_b, turboDLL_b, writeA45, writeA0123, writeA0123x, writeD0123, writeD4567, writeSenseAmpPipe;
inout RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_,
RDL2_2_, RDL2_1_, RDL2_0_, RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_,
RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_,
RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_,
dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_,
dataZ3_1_, dataZ3_0_;
input BEevenD, BEoddD, BIMDI, Last_b, OpX_1_, OpX_0_, PON, RCRED, RawLast, Rx_2, SInRaw_b, TestCAS, TestRASB, TestRSTR, VREG, Vrefin, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_,
WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_,
WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_, WDL6_5_,
WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_, autoSkip,
bcastWriteA, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_,
dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_,
dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, done, frameEnableX, framePulse_b, frameRaw_b, lowVref, mclk, mtclk, opcode_b_2_, opcode_b_1_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_,
pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_,
pd3_3_, pd3_2_, pd3_1_, pd3_0_, rawBE_b, rclk, runclk_b, slow, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_;
supply1 vdd;
supply0 gnd;
u5CMPV I992(CMPF, CMPV, vdd, Vrefin, VREG);
u5BENSad I978(NSAdr_7_, NSAdr_6_, NSAdr_5_, NSAdr_4_, NSAdr_3_, NSAdr_2_, NSAdr_1_, NSAdr_0_, BEevenD, BEoddD, loadNSAdr, rclk, writeOp_b);
u5CDOpCk CdOpCk(MPBT, NSOp, REQinhibiten, WPBNP, WPBT, abortOperation_b, preCycState5, readOpDelay, regOp, startCycle_b, writeMaskedNSOp_b, writeOp_b, CASenable, DAmode_b, OpX_1_, OpX_0_, SInRaw_b,
TestMPBT, TestWPBT, deviceEnableMode, opcode_3_, opcode_0_, opcode_b_2_, opcode_b_1_, rclk, readDelay_2_, readDelay_1_, readDelay_0_, reset, writeA45, writeDelay_2_, writeDelay_1_, writeDelay_0_);
u5XS XS(gated_mclk, mclk_div16, rdPipeBusy_b, tclkDisable_b, CASstate3_buf, earlyDone, mclk, mclkOn, rclk, readOpDelay, reset);
u5BSNack BSNack(BCOeven_b, BCOodd_b, RASaddrEnable, sytload_b, BusCtrlEn_b, LoadShiftRegister_b, ackLatch, bcastWrite, idHitA, idHitB, latchAbort_b, mtclk, nack, rclk, reset, skip, writeA45);
u5RshCtl RshCtl(AUXRASreq, AUXorPDcycle, AUXpending_b, PDreq2, RASrfshRetD, RefreshReturn_b, closeCycle, closeCycle_b, closeReq_b, doAUXcycle, driveRfshAddr_b, endCycleD_buf, restoreBank0,
restoreBank1, PD64after, RASAUXRet_b, RASidle_b, clearPDreq2, close0Pending_b, close0Selected, close1Pending_b, close1Selected, decXferCnt_b, explicitRestore, idle, packetBSELx, powerDownReq_b, rclk,
reFetchCycle, reset, setRR_b, writeA45, writeA0123x);
u5Rasb Rasb(RASB, RASpending, RASpending_b, clearPDreq2, drivePacketRASaddr, incRfshRow_b, powerDownMode, reFetchCycle, reFetchCycle_b, updateRowAddr, AUXRASreq, BIMDI, DAmode_b, PDreq2, RASkill,
RASprecharge, RASrfshRetD, RASstate4, RS_0_, SInRaw_b, TestRASB, clearRASpending_b, doAUXcycle, endPowerDown_b, explicitRestore, idHitRowMiss, latchAbort, rclk, reset, rfshCout_1_, setPD, standby,
writeA0123x);
u5AkWDly AkWDly(BC_oe, BusCtrlEn_b, ackClear, ackLatch, ackWinOverD, inhLoadLast_b, ackDelay_1_, ackDelay_0_, ackWinDelay_2_, ackWinDelay_1_, ackWinDelay_0_, bcastWrite, evalR, framePulseX, idHitA,
idHitB, rclk, reset);
u5bit4 bit4(ADR_3_, CASctCy45, Count_2_, DAR_3_, NSWE_4_, RAScountLSB_b, RfshRwCy45, XfrCntBorw45, ackDelay_1_, ackWinDelay_1_, partialId_b_2_, pd2_4_, readDelay_1_, skip, writeDelay_1_, xcnt_b_0_,
dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, idHitB, row0hitA, row1hitA, CASctCy34, DAmode_b, DLLByPassMode_b, NSAdr_3_, RASaddrEnable, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_,
RfshRwCy34, autoSkip, autoSkipEn, dataIn0_4_, dataIn1_4_, dataIn2_4_, dataIn3_4_, decXferCnt_b, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalR, incColAdr_b, incRfshRow_b,
loadDAR, loadNSWE, localBSEL, partialId_b_1_, pd0_4_, pd1_4_, pd2_5_, pd3_4_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0,
restoreBank1, setDAR, skipBit, testBD_5_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_6_, writeR_5_, writeR_2_, writeR_1_);
u5CAScyc CAScyc(CAS, CASstate1_b, CASstate3_buf, CASwrite, LoadShiftRegister_b, WML, WRITE, decXferCnt_b, earlyREQinhibit, firstCycWE_b, incColAdr_b, loadLast, loadNSAdr, preloadNSWE, selRegData,
startNSAdr_b, trueCASstate1_b, unloadNSWE, writeD0123, writeD4567, writeSenseAmpPipe, CASenable, DAWD0123, DAWD4567, DAmode_b, NSOp, REQinhibiten, TestCAS, TestRASB, TestWML, TestWRITE, WPBNP,
abortOperation_b, earlyDone, inhLoadLast_b, killFirstCycle_b, localREQ, rclk, regOp, reset, standby, startCycle_b, virtuallyDone, writeA45, writeMaskedNSOp_b, writeOp_b);
u5RegDec RegDec(framePulseX, readR_10_, readR_9_, readR_8_, readR_7_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_3_, writeR_2_,
writeR_1_, ADRx_6_, ADR_2_, ADR_1_, ADR_0_, Addr_2_, PDMD, framePulse_b, reset, selRegData, writeD4567);
u5PreHit PreHit(CASenable, RASkill, RASstate4, REQ, bcastWrite, busy_b, driveColAdr, driveNSAdr, evalL, evalR, idHitRowMiss, idle, killFirstCycle_b, latchAbort, latchAbort_b, localREQ, nack,
pwrdnRcvrs, runtclk, virtuallyDone, writeA45, writeA0123, writeA0123x, AUXorPDcycle, AUXpending_b, DAmode_b, DLLByPassMode_b, NSOp, PDMD, RASidle_b, RASreturn_b, RcvrsOff_b, RefreshReturn_b,
TestRASB, abortOperation_b, ackClear, bcastWriteA, bcastWriteB, earlyDone, earlyREQinhibit, frameEnableX, frameRaw_b, idHitA, idHitB, packetBSEL, packetBSELx, powerDownMode, preCycState5, rawBE_b,
rclk, regOp, reset, row0hitA, row0hitB, row1hitA, row1hitB, startNSAdr_b, tclkDisable_b, updateRowAddr, writeOp_b);
u5RAScyc RAScyc(DeviceBusy, RASAUXRet_b, RAScount_b, RASidle_b, RASldCount, RASprecharge, RASreturn_b, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RS_0_, RSTR, clearRASpending_b, close0Pending_b,
close0Selected, close1Pending_b, close1Selected, explicitRestore, localRSTR_b, setPD, DAmode_b, PD64after, PDreq2, RAScountLSB_b, RASoverflow_b, RASpending, RASpending_b, TestRSTR, busy_b,
closeCycle, closeCycle_b, closeReq_b, doAUXcycle, endCycleD_buf, needRestore_b, powerDownReq_b, rclk, reFetchCycle_b, reset, turboDLL_b);
u5bit78 bit78(ADR_6_, CASctCy70, NSWE_7_, RfshRwCy70, bcastWriteB, chainOut_8_, control_7_, control_5_, control_4_, control_3_, opcode_3_, opcode_0_, pd2_7_, dataZ0_7_, dataZ1_7_, dataZ2_7_,
dataZ3_7_, idHitA, row0hitB, row1hitB, CASctCy67, DAmode_b, NSAdr_6_, RASaddrEnable, RfshRwCy67, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn1_7_, dataIn2_7_, dataIn3_7_, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalL, ictrl_5_, ictrl_4_, ictrl_3_, incColAdr_b, incRfshRow_b, loadNSWE, localBSEL, partialId_b_4_, pd0_7_, pd0_8_, pd1_7_, pd1_8_, pd2_8_, pd3_7_,
pd3_8_, rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_3_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_8_, unloadNSWE, updateRowAddr, writeA0123, writeA0123x,
writeR_8_, writeR_5_, writeR_3_, writeR_1_);
u5CCctl CCctl(ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, powerOn, resetCap, control_7_, control_6_, control_5_, control_4_, control_3_, control_2_, control_1_, control_0_, done,
evalCurrentCnt, gated_mclk, rclk, reset, writeA0123);
u5bit3 bit3(ADR_2_, CASctCy34, Count_1_, DAR_2_, NSWE_3_, RASctCy32, RfshRwCy34, ackDelay_0_, ackWinDelay_0_, partialId_b_1_, pd2_3_, readDelay_0_, rfshBSEL, skipBit, writeDelay_0_, dataZ0_3_,
dataZ1_3_, dataZ2_3_, dataZ3_3_, idHitB, row0hitA, row1hitA, CASctCy23, DAmode_b, NSAdr_2_, RASaddrEnable, RAScount_b, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy23, dataIn0_3_,
dataIn1_3_, dataIn2_3_, dataIn3_3_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalR, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_0_, pd0_3_, pd1_3_,
pd2_4_, pd3_3_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, setDAR, testBD_4_, unloadNSWE, updateRowAddr,
writeA45, writeA0123, writeA0123x, writeR_8_, writeR_6_, writeR_5_, writeR_3_, writeR_2_, writeR_1_);
u5TstCtl TstCtl(AGEGND, AGEING, CMPV, DAWD0123, DAWD4567, DAmode_b, DLLByPassMode_b, HVST, PDMD, ROLLC, RcvrsOff_b, SDST, TestMPBT, TestSOut, TestWE, TestWML, TestWPBT, TestWRITE, VCMNA, VRST,
chain_b, enableSOut, loadDAR, needRestore_b, testLoad_b, BIMDI, CASwrite, DAR_4_, DAR_3_, DAR_2_, DAR_1_, DAR_0_, RCRED, SInRaw_b, TestCAS, TestRASB, TestRSTR, chainOut_8_, localBSEL, localRSTR_b,
lowVref, powerDownMode, rclk, reset, resetDAmode_b, runclk_b, slow, testBD_b_0_);
RWDfthru I652_8_(RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_);
RWDfthru I652_7_(RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_);
RWDfthru I652_6_(RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_);
RWDfthru I652_5_(RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_);
RWDfthru I652_4_(RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_);
RWDfthru I652_3_(RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_);
RWDfthru I652_2_(RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_);
RWDfthru I652_1_(RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_);
RWDfthru I652_0_(RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_);
u5bit0 bit0(ADR_7_, Addr_0_, Addr_2_, NSWE_0_, RASoverflow_b, RfshRwCy01, muxBS8, setRR_b, testBD_b_0_, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, idHitB, row0hitA, row1hitA, CASctCy70, DAmode_b,
NSAdr_7_, RASaddrEnable, RAScount_b, RASctCy10, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy70, dataIn0_0_, dataIn1_0_, dataIn2_0_, dataIn3_0_, driveColAdr, driveNSAdr,
drivePacketRASaddr, driveRfshAddr_b, evalR, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, pd0_0_, pd1_0_, pd2_0_, pd3_0_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_2_,
readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_0_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_1_);
u5bit5 bit5(ADR_4_, CASctCy56, DAR_4_, NSWE_5_, PDslow, RfshRwCy56, XfrCntBorw56, ackWinDelay_2_, partialId_b_3_, pd2_5_, readDelay_2_, setDAR, writeDelay_2_, xcnt4321, dataZ0_5_, dataZ1_5_,
dataZ2_5_, dataZ3_5_, idHitA, row0hitB, row1hitB, CASctCy45, DAmode_b, NSAdr_4_, RASaddrEnable, RfshRwCy45, XfrCntBorw45, dataIn0_5_, dataIn1_5_, dataIn2_5_, dataIn3_5_, decXferCnt_b, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalL, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, partialId_b_2_, pd0_5_, pd1_5_, pd2_6_, pd3_5_, rclk, readR_10_, readR_9_, readR_8_,
readR_7_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_6_, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_,
writeR_5_, writeR_3_, writeR_2_, writeR_1_, xcnt_b_4_, xcnt_b_3_);
u5BElog BElog(PD64after, checkskip, clearCount_b, endPowerDown_b, evalCurrentCnt, reset, resetDAmode_b, sampleskip, standby, stbybWak, turboDLL_b, DAmode_b, DLLByPassMode_b, DeviceBusy, PDreq2,
PDslow, PON, Rx_2, mclk_div16, powerDownMode, rawBE_b, rclk, rdPipeBusy_b);
u5WEgen WEgen(ADRx_6_, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, earlyDone, loadNSWE, ADR_6_, Addr_2_, Addr_1_, Addr_0_, CASstate1_b, Count_2_, Count_1_, Count_0_, DAmode_b, Last_b,
NSOp, NSWE_7_, NSWE_6_, NSWE_5_, NSWE_4_, NSWE_3_, NSWE_2_, NSWE_1_, NSWE_0_, RASB, RawLast, TestWE, firstCycWE_b, loadLast, preloadNSWE, rclk, regOp, reset, trueCASstate1_b, writeA0123x,
writeMaskedNSOp_b, writeOp_b, xcnt4321, xcnt_b_0_);
u5bit2 bit2(ADR_1_, BSEL, CASctCy23, Count_0_, DAR_1_, NSWE_2_, RASctCy21, RfshRwCy23, autoSkipEn, localBSEL, packetBSELx, partialId_b_0_, pd2_2_, powerDownReq_b, rfshCout_1_, dataZ0_2_, dataZ1_2_,
dataZ2_2_, dataZ3_2_, idHitB, row0hitA, row1hitA, CASctCy12, DAmode_b, NSAdr_1_, RASaddrEnable, RAScount_b, RASctCy32, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy12, dataIn0_2_,
dataIn1_2_, dataIn2_2_, dataIn3_2_, driveColAdr, driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, endPowerDown_b, evalR, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, packetBSEL, pd0_2_, pd1_2_,
pd2_3_, pd3_2_, rclk, readR_10_, readR_9_, readR_8_, readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_3_, testBSEL, unloadNSWE,
updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_, writeR_7_, writeR_6_, writeR_5_, writeR_3_, writeR_1_);
u5bit6 bit6(ADR_5_, CASctCy67, NSWE_6_, RfshRwCy67, control_6_, control_2_, control_1_, control_0_, mclkOn, partialId_b_4_, pd2_6_, xcnt_b_4_, xcnt_b_3_, dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_,
idHitA, row0hitB, row1hitB, CASctCy56, DAmode_b, NSAdr_5_, RASaddrEnable, RfshRwCy56, XfrCntBorw56, dataIn0_6_, dataIn1_6_, dataIn2_6_, dataIn3_6_, decXferCnt_b, done, driveColAdr, driveNSAdr,
drivePacketRASaddr, driveRfshAddr_b, evalL, evalCurrentCnt, gated_mclk, ictrl_2_, ictrl_1_, ictrl_0_, incColAdr_b, incRfshRow_b, loadNSWE, localBSEL, partialId_b_3_, pd0_6_, pd1_6_, pd2_7_, pd3_6_,
rclk, readR_10_, readR_9_, readR_8_, readR_7_, readR_5_, readR_3_, readR_1_, readR_0_, reset, restoreBank0, restoreBank1, testBD_7_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x,
writeR_8_, writeR_5_, writeR_3_, writeR_1_);
u5bit1 bit1(ADR_8_, ADR_0_, Addr_1_, CASctCy12, DAR_0_, NSWE_1_, RASctCy10, RfshRwCy12, deviceEnableMode, packetBSEL, testBSEL, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, idHitB, row0hitA, row1hitA,
BIMDI, DAmode_b, NSAdr_0_, RASaddrEnable, RAScount_b, RASctCy21, RASldCount, RASsel_3_, RASsel_2_, RASsel_1_, RASsel_0_, RfshRwCy01, dataIn0_1_, dataIn1_1_, dataIn2_1_, dataIn3_1_, driveColAdr,
driveNSAdr, drivePacketRASaddr, driveRfshAddr_b, evalR, incColAdr_b, incRfshRow_b, loadDAR, loadNSWE, localBSEL, muxBS8, pd0_1_, pd1_1_, pd2_1_, pd2_2_, pd3_1_, rclk, readR_10_, readR_9_, readR_8_,
readR_6_, readR_5_, readR_3_, readR_2_, readR_1_, reset, restoreBank0, restoreBank1, rfshBSEL, setDAR, testBD_1_, testBD_2_, unloadNSWE, updateRowAddr, writeA45, writeA0123, writeA0123x, writeR_8_,
writeR_6_, writeR_5_, writeR_3_, writeR_1_);
endmodule

module probe (probe);
inout probe;
supply1 vdd;
supply0 gnd;
endmodule

module u5IOgnd (gnd, vdd);
input gnd, vdd;
supply1 vdd;
supply0 gnd;
endmodule

module u5InProt (padin, pad);
output padin;
inout pad;
supply1 vdd;
supply0 gnd;
P4res Rin(pad, padin);
tranif1 N18(gnd, pad, gnd);
tranif1 N15(gnd, pad, gnd);
tranif1 N11(gnd, pad, gnd);
tranif1 N6(gnd, pad, gnd);
tranif1 N5(gnd, pad, gnd);
tranif1 N2(gnd, pad, gnd);
endmodule

module u5DABuf (Out, En_b, In);
output Out;
input En_b, In;
supply1 vdd;
supply0 gnd;
not (weak0,weak1) #(1) U33(out0B, out1);
nand #(1) U37(hnl_580, out1, En);
not #(1) I32(out1, out0B);
not #(1) I31(En, En_b);
not #(1) I36(Out, hnl_580);
tranif1 N29(hnl_581, gnd, In);
tranif1 N27(out0B, hnl_581, En);
tranif0 P25(out0B, hnl_582, En_b);
tranif0 P28(hnl_582, vdd, In);
endmodule

module cxfr (D, GN, GP, S);
output D;
input GN, GP, S;
supply1 vdd;
supply0 gnd;
tranif0 P8(S, D, GP);
tranif1 N9(S, D, GN);
endmodule

module u5DfLatB (Q, D, DB, enb, pdb);
output Q;
input D, DB, enb, pdb;
supply1 vdd;
supply0 gnd;
nand #(1) nandd(outd, outc, pdb);
nand #(1) nandb(lclkb, outa, pdb);
rtranif1 N100(ds, gnd, dsb);
rtranif0 P99(ds, vdd, dsb);
not (weak0,weak1) #(1) U94(dsb, ds);
not #(1) ine(lclk, outd);
not #(1) inc(outc, enb);
not #(1) ina(outa, enb);
cxfr U85(dsb, lclk, lclkb, D);
cxfr U64(ds, lclk, lclkb, DB);
not #(1) U65(Q, ds);
endmodule

module u5DfLat (Q, D, DB, en, pdb);
output Q;
input D, DB, en, pdb;
supply1 vdd;
supply0 gnd;
nand #(1) nandc(outc, en, pdb);
nand #(1) nanda(outa, en, pdb);
rtranif0 P101(ds, vdd, dsb);
rtranif1 N100(ds, gnd, dsb);
not (weak0,weak1) #(1) U94(dsb, ds);
not #(1) ind(outd, outc);
not #(1) inb(lclk, outa);
cxfr U85(dsb, lclk, lclkb, D);
cxfr U64(ds, lclk, lclkb, DB);
not #(1) ine(lclkb, outd);
not #(1) U65(Q, ds);
endmodule

module u5BEInpt (BEevenD, BEoddD, TestRSTR, rawBE_b, runclk_b, BusEnable, DAmode_b, VRefin, powerDownMode, rclk, stbybWak);
output BEevenD, BEoddD, TestRSTR, rawBE_b, runclk_b;
input BusEnable, DAmode_b, VRefin, powerDownMode, rclk, stbybWak;
supply1 vdd;
supply0 gnd;
lvtncap C462(gnd, gnd);
ffB #(1) I460(hnl_583, rclk, BEodd);
ffB #(1) I459(BEevenD, rclk, hnl_439);
not #(1) U458(BEoddD, hnl_583);
u5InProt BEinProt(BusEnableIn, BusEnable);
u5DABuf RSTRDAbuf(TestRSTR, DAmode_b, BusEnableIn);
u5BEsnif BEsnif(rawBE_b, VRefin, BusEnableIn);
u5DfLatB I436(BEeven, eq, eqb, rclk, pwrdnB);
u5DfLat I435(BEodd, oq, oqb, rclk, pwrdnB);
u5EIRcvr Reven(eq, eqb, powerDownMode, VRefin, BusEnableIn, rclk);
u5OIRcvr ROdd(oqb, oq, powerDownMode, BusEnableIn, rclk, VRefin);
not #(1) U411(hnl_439, BEeven);
nand #(1) U313(hnl_55, hnl_584, rawBE_b);
not #(1) U461(pwrdnB, powerDownMode);
not #(1) U308(runclk_b, hnl_55);
not #(1) U302(hnl_584, stbybWak);
endmodule

module u5VrfLow (lowVref, VRefin);
output lowVref;
input VRefin;
supply1 vdd;
supply0 gnd;
not #(1) U5(hnl_585, o1);
not #(1) U3(o1, VRefin);
not #(1) I6(lowVref, hnl_585);
endmodule

module u5SIO (SInRaw_b, SOut, VRefin, lowVref, CMPF, CMPV, DAmode_b, SIn, TestSOut, VRef, deviceEnableMode, enableSOut, tclk);
output SInRaw_b, SOut, VRefin, lowVref;
input CMPF, CMPV, DAmode_b, SIn, TestSOut, VRef, deviceEnableMode, enableSOut, tclk;
supply1 vdd;
supply0 gnd;
u5VrfLow I167(lowVref, VRefin);
u5InProt Sininprot(hnl_586, SIn);
u5InProt Vrefinprot(VRefin, VRef);
u5OscMJ OscMJ(osc, oscen);
u5SoDrv SoDrv(oscen, SOut, hnl_587, osc, hnl_17);
nor #(1) U143(hnl_588, CMPV, DAmode_b);
probe I159(osc);
u5SioMux I150(hnl_589, hnl_590, hnl_591, CMPF, DAmode_b, CMPV, hnl_588);
not #(1) U77(hnl_592, hnl_593);
not #(1) I153(hnl_594, SInRaw_b);
not #(1) I152(hnl_17, hnl_430);
not #(1) I149(hnl_595, hnl_596);
nand #(1) U154(hnl_590, hnl_594, deviceEnableMode);
nand #(1) U148(hnl_596, hnl_589, hnl_17);
not #(1) LowB(hnl_597, hnl_586);
not #(1) HighB(hnl_598, hnl_586);
not #(1) U76(hnl_593, hnl_586);
not #(1) U142(hnl_591, TestSOut);
not #(1) U151(hnl_430, enableSOut);
not #(1) U146(hnl_587, hnl_595);
not #(1) U75(SInRaw_b, hnl_592);
endmodule

module latW (Y, A);
output Y;
inout A;
supply1 vdd;
supply0 gnd;
rtranif1 N22(A, gnd, Y);
tranif1 N27(Y, gnd, A);
rtranif0 P21(A, vdd, Y);
tranif0 P28(Y, vdd, A);
endmodule

module u5OutDrv (pad, q0, q1, q2, q3, q4, q5);
inout pad;
input q0, q1, q2, q3, q4, q5;
supply1 vdd;
supply0 gnd;
////////////////////////////////////////////////////////////////////////////////
// hack
//P2res R59(q2r, q2);
//P2res R58(q3r, q3);
//P2res R57(q4r, q4);
//P2res R56(q5r, q5);

//tranif1 N43(gnd, pad, q2r);
//tranif1 N33(gnd, pad, q3r);
//tranif1 N1(gnd, pad, q4r);
//tranif1 N42(gnd, pad, q5r);

tranif1 N43(gnd, pad, q2);
tranif1 N33(gnd, pad, q3);
tranif1 N1(gnd, pad, q4);
tranif1 N42(gnd, pad, q5);
////////////////////////////////////////////////////////////////////////////////
tranif1 N4(gnd, pad, q0);
tranif1 N44(gnd, pad, q1);
endmodule

module u5OutMux (q0, q1, q2, q3, q4, q5, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b);
output q0, q1, q2, q3, q4, q5;
input evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b;
supply1 vdd;
supply0 gnd;
not #(1) U82(q0, d0);
not #(1) U74(q1, d1);
not #(1) U88(q2, d2);
not #(1) U90(q3, d3);
not #(1) U69(q4, d4);
not #(1) U91(q5, d5);
nand #(1) U155(e0, evenData, ictrl_0_);
nand #(1) U154(o0, oddData, ictrl_0_);
nand #(1) U153(e1, evenData, ictrl_1_);
nand #(1) U152(o1, oddData, ictrl_1_);
nand #(1) U128(e2, evenData, ictrl_2_);
nand #(1) U127(o2, oddData, ictrl_2_);
nand #(1) U134(e4, evenData, ictrl_4_);
nand #(1) U51(o4, oddData, ictrl_4_);
nand #(1) U133(e5, evenData, ictrl_5_);
nand #(1) U77(o5, oddData, ictrl_5_);
nand #(1) U61(o3, oddData, ictrl_3_);
nand #(1) U126(e3, evenData, ictrl_3_);
cxfr U151(d0, tclkL, tclkL_b, o0);
cxfr U150(d0, tclkL_b, tclkL, e0);
cxfr U149(d1, tclkL, tclkL_b, o1);
cxfr U148(d1, tclkL_b, tclkL, e1);
cxfr U136(d2, tclkL_b, tclkL, e2);
cxfr U135(d2, tclkL, tclkL_b, o2);
cxfr U119(d3, tclkL_b, tclkL, e3);
cxfr U56(d3, tclkL, tclkL_b, o3);
cxfr U99(d4, tclkL_b, tclkL, e4);
cxfr U52(d4, tclkL, tclkL_b, o4);
cxfr U118(d5, tclkL_b, tclkL, e5);
cxfr U76(d5, tclkL, tclkL_b, o5);
endmodule

module u5OutLat3 (out, load, loadB, pipeB, rdl, wrtPipe, wrtPipeB);
output out;
input load, loadB, pipeB, rdl, wrtPipe, wrtPipeB;
supply1 vdd;
supply0 gnd;
latW U35(lat1, hnl_599);
not #(1) U67(rdlB, rdl);
cxfr U34(hnl_599, wrtPipe, wrtPipeB, rdlB);
tranif1 N59(hnl_600, gnd, pipeB);
tranif1 N56(out, hnl_600, loadB);
tranif1 N53(out, hnl_601, load);
tranif1 N51(hnl_601, gnd, lat1);
tranif0 P57(out, hnl_602, load);
tranif0 P55(hnl_602, vdd, pipeB);
tranif0 P54(hnl_603, vdd, lat1);
tranif0 P52(out, hnl_603, loadB);
endmodule

module u5OutLat2 (out, load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB);
output out;
input load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB;
supply1 vdd;
supply0 gnd;
not #(1) U32(hnl_604, regin);
latW U35(lat1, hnl_599);
cxfr U34(hnl_599, wrtPipe, wrtPipeB, mux1);
tranif1 N64(hnl_605, gnd, srdB);
tranif1 N59(hnl_600, hnl_605, pipeB);
tranif1 N56(out, hnl_600, loadB);
tranif1 N53(out, hnl_601, load);
tranif1 N51(hnl_601, gnd, lat1);
tranif1 N50(hnl_606, gnd, hnl_604);
tranif1 N49(mux1, hnl_606, srd);
tranif1 N14(hnl_607, gnd, rdl);
tranif1 N13(mux1, hnl_607, srdB);
rtranif0 P33(regin, vdd, gnd);
tranif0 P62(hnl_602, vdd, srdB);
tranif0 P57(out, hnl_602, load);
tranif0 P55(hnl_602, vdd, pipeB);
tranif0 P54(hnl_603, vdd, lat1);
tranif0 P52(out, hnl_603, loadB);
tranif0 P48(hnl_608, vdd, hnl_604);
tranif0 P47(mux1, hnl_608, srdB);
tranif0 P10(mux1, hnl_609, srd);
tranif0 P11(hnl_609, vdd, rdl);
endmodule

module u5OutLat1 (out, load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB);
output out;
input load, loadB, pipeB, rdl, regin, srd, srdB, wrtPipe, wrtPipeB;
supply1 vdd;
supply0 gnd;
not #(1) U32(hnl_604, regin);
latW U35(lat1, hnl_599);
cxfr U34(hnl_599, wrtPipe, wrtPipeB, mux1);
tranif1 N59(hnl_600, gnd, pipeB);
tranif1 N56(out, hnl_600, loadB);
tranif1 N53(out, hnl_601, load);
tranif1 N51(hnl_601, gnd, lat1);
tranif1 N50(hnl_606, gnd, hnl_604);
tranif1 N49(mux1, hnl_606, srd);
tranif1 N14(hnl_607, gnd, rdl);
tranif1 N13(mux1, hnl_607, srdB);
rtranif0 P33(regin, vdd, gnd);
tranif0 P57(out, hnl_602, load);
tranif0 P55(hnl_602, vdd, pipeB);
tranif0 P54(hnl_603, vdd, lat1);
tranif0 P52(out, hnl_603, loadB);
tranif0 P48(hnl_608, vdd, hnl_604);
tranif0 P47(mux1, hnl_608, srdB);
tranif0 P10(mux1, hnl_609, srd);
tranif0 P11(hnl_609, vdd, rdl);
endmodule

module u5Output (chainOutEven, chainOutOdd, padin1, padin2, pad, RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, chainInEven, chainInOdd, chain_b, ictrl_5_, ictrl_4_, ictrl_3_,
ictrl_2_, ictrl_1_, ictrl_0_, regin0, regin1, regin2, regin3, srd, sytload_b, tclkL, tclkL_b, testLoad_b, writeSenseAmpPipe);
output chainOutEven, chainOutOdd, padin1, padin2;
inout pad;
input RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, chainInEven, chainInOdd, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, regin0, regin1, regin2, regin3,
srd, sytload_b, tclkL, tclkL_b, testLoad_b, writeSenseAmpPipe;
supply1 vdd;
supply0 gnd;
latW U656(hnl_610, hnl_611);
latW U539(hnl_68, hnl_612);
nand #(1) I609(hnl_613, hnl_614, chain_b);
nand #(1) U606(hnl_615, hnl_68, chain_b);
u5OutDrv OutDrv(pad, q0, q1, q2, q3, q4, q5);
P4res Rin3(pad, padin2);
P4res Rin2(hnl_616, padin1);
P4res Rin1(pad, hnl_616);
u5OutMux OutMux(q0, q1, q2, q3, q4, q5, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b);
u5OutLat3 I630(in6, load, load_b, hnl_617, RDL_4_, wrtPipe, wrtPipe_b);
u5OutLat3 I645(in7, load, load_b, hnl_618, RDL_6_, wrtPipe, wrtPipe_b);
u5OutLat3 I647(in3, load, load_b, hnl_619, RDL_7_, wrtPipe, wrtPipe_b);
u5OutLat3 I631(in2, load, load_b, hnl_620, RDL_5_, wrtPipe, wrtPipe_b);
u5OutLat2 I625(in5, load, load_b, hnl_621, RDL_2_, regin2, srd, srd_b, wrtPipe, wrtPipe_b);
u5OutLat2 I627(in1, load, load_b, hnl_622, RDL_3_, regin3, srd, srd_b, wrtPipe, wrtPipe_b);
latW U657(hnl_623, hnl_614);
latW U629(hnl_624, hnl_625);
latW U635(hnl_626, hnl_627);
latW U655(hnl_628, hnl_629);
latW U654(hnl_630, hnl_631);
latW U653(hnl_632, hnl_633);
latW U638(hnl_318, hnl_634);
latW U639(hnl_635, hnl_636);
latW U634(hnl_637, hnl_638);
latW U637(load_b, w2);
latW U636(load, w1);
latW U633(hnl_172, hnl_620);
latW U632(hnl_311, hnl_617);
latW U628(hnl_173, hnl_622);
latW U626(hnl_639, hnl_621);
latW U624(hnl_100, hnl_640);
u5OutLat1 lat1b0(in4, load, load_b, hnl_640, RDL_0_, regin0, srd, srd_b, wrtPipe, wrtPipe_b);
u5OutLat1 I623(in0, load, load_b, hnl_625, RDL_1_, regin1, srd, srd_b, wrtPipe, wrtPipe_b);
nor #(1) U613(chainOutOdd, hnl_641, chain_b);
nor #(1) U611(chainOutEven, hnl_642, chain_b);
nand #(1) U648(hnl_643, chain, chainInOdd);
nand #(1) U579(hnl_644, chain, chainInEven);
nand #(1) U595(hnl_645, sytload_b, testLoad_b);
not #(1) U610(oddData, hnl_613);
not #(1) I607(evenData, hnl_615);
not #(1) I614(wrtPipe, wrtPipe_b);
not #(1) I649(hnl_619, hnl_643);
not #(1) U578(chain, chain_b);
not #(1) I646(hnl_618, hnl_644);
not #(1) U673(hnl_641, hnl_614);
not #(1) U672(hnl_642, hnl_68);
not #(1) U398(wrtPipe_b, writeSenseAmpPipe);
not #(1) U593(hnl_646, hnl_626);
not #(1) U391(srd_b, srd);
cxfr U372(hnl_614, tclkL_b, tclkL, hnl_610);
cxfr U663(hnl_611, tclkL, tclkL_b, in0);
cxfr U667(hnl_625, tclkL_b, tclkL, hnl_628);
cxfr U660(hnl_629, tclkL, tclkL_b, in1);
cxfr U666(hnl_622, tclkL_b, tclkL, hnl_630);
cxfr U659(hnl_631, tclkL, tclkL_b, in2);
cxfr U665(hnl_620, tclkL_b, tclkL, hnl_632);
cxfr U658(hnl_633, tclkL, tclkL_b, in3);
cxfr U596(w2, tclkL_b, tclkL, hnl_646);
cxfr U599(w1, tclkL_b, tclkL, hnl_626);
cxfr U602(hnl_627, tclkL, tclkL_b, hnl_645);
cxfr U303(hnl_612, tclkL, tclkL_b, in4);
cxfr U320(hnl_640, tclkL_b, tclkL, hnl_637);
cxfr U661(hnl_638, tclkL, tclkL_b, in5);
cxfr U664(hnl_621, tclkL_b, tclkL, hnl_635);
cxfr U662(hnl_636, tclkL, tclkL_b, in6);
cxfr U310(hnl_617, tclkL_b, tclkL, hnl_318);
cxfr U311(hnl_634, tclkL, tclkL_b, in7);
endmodule

module u5LtMxDf (pd, D, DB, en, s_b, serialData);
output pd;
input D, DB, en, s_b, serialData;
supply1 vdd;
supply0 gnd;
nand #(1) U108(hnl_647, en, hnl_207);
rtranif0 P111(ds, vdd, dsb);
tranif0 P103(hnl_648, vdd, serialData);
tranif0 P102(dsb, hnl_648, hnl_647);
rtranif1 N110(ds, gnd, dsb);
tranif1 N106(hnl_649, gnd, serialData);
tranif1 N100(dsb, hnl_649, hnl_423);
not (weak0,weak1) #(1) U94(dsb, ds);
nand #(1) nandc(hnl_650, en, s_b);
nand #(1) nanda(hnl_651, en, s_b);
not #(1) ind(hnl_652, hnl_650);
not #(1) inb(lclk, hnl_651);
not #(1) U107(hnl_207, s_b);
not #(1) U104(hnl_423, hnl_647);
not #(1) I79(pd, d_bs1);
cxfr U85(dsb, lclk, lclkb, DB);
cxfr U64(ds, lclk, lclkb, D);
not #(1) ine(lclkb, hnl_652);
not #(1) U65(d_bs1, ds);
endmodule

module u5BLtMxD (pdb, D, DB, enb, s_b, serialDataB);
output pdb;
input D, DB, enb, s_b, serialDataB;
supply1 vdd;
supply0 gnd;
nor #(1) U111(hnl_653, enb, s_b);
rtranif0 P115(dsb, vdd, ds);
tranif0 P108(ds, hnl_654, hnl_655);
tranif0 P109(hnl_654, vdd, serialDataB);
rtranif1 N114(dsb, gnd, ds);
tranif1 N106(hnl_656, gnd, serialDataB);
tranif1 N105(ds, hnl_656, hnl_653);
nand #(1) nandd(outd, outc, s_b);
nand #(1) nandb(lclkb, outa, s_b);
not (weak0,weak1) #(1) U100(ds, dsb);
not #(1) inc(outc, enb);
not #(1) ina(outa, enb);
not #(1) ine(lclk, outd);
not #(1) U65(d_bs1, dsb);
cxfr U85(ds, lclk, lclkb, D);
cxfr U64(dsb, lclk, lclkb, DB);
not #(1) U112(hnl_655, hnl_653);
not #(1) I79(pdb, d_bs1);
endmodule

module u5Input (WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, sampledInEven, sampledInOdd, InClk, InClkB, VRefin, chain_b,
padin, pwrdnRcvrs, rclk, serialInEven, serialInOdd, writeD0123, writeD4567);
output WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, sampledInEven, sampledInOdd;
input InClk, InClkB, VRefin, chain_b, padin, pwrdnRcvrs, rclk, serialInEven, serialInOdd, writeD0123, writeD4567;
supply1 vdd;
supply0 gnd;
u5LtMxDf I311(pd3, DataOdd, DataOddB, rclk, chain_b, serialInOdd);
nand #(1) U315(hnl_657, hnl_658, writeD4567);
nand #(1) U314(hnl_659, hnl_660, writeD0123);
u5BLtMxD I312(EvenLat, DataEven, DataEvenB, rclk, chain_b, hnl_526);
u5pd2Lat I301(pd2, InClk, EvenLat, InClkB);
u5OIRcvr Odd(DataOddB, DataOdd, pwrdnRcvrs, padin, rclk, VRefin);
u5EIRcvr Even(DataEven, DataEvenB, pwrdnRcvrs, VRefin, padin, rclk);
not #(1) U320(hnl_545, hnl_661);
not #(1) U319(hnl_53, hnl_662);
not #(1) I318(writeD4L, hnl_657);
not #(1) I316(writeD0L, hnl_659);
not #(1) I309(sampledInOdd, hnl_463);
not #(1) I307(sampledInEven, EvenLat);
u5InLat4 I263(WDL_1_, hnl_663, writeD4L, writeD4_B);
u5InLat4 I265(WDL_3_, hnl_664, writeD4L, writeD4_B);
u5InLat4 I264(WDL_5_, hnl_665, writeD4L, writeD4_B);
u5InLat4 I259(WDL_0_, hnl_666, writeD4L, writeD4_B);
u5InLat4 I260(WDL_4_, hnl_667, writeD4L, writeD4_B);
u5InLat4 I266(WDL_7_, hnl_545, writeD4L, writeD4_B);
u5InLat4 I262(WDL_6_, hnl_53, writeD4L, writeD4_B);
u5InLat4 I261(WDL_2_, hnl_668, writeD4L, writeD4_B);
not #(1) U322(hnl_660, rclk);
not #(1) U321(hnl_658, rclk);
not #(1) U306(writeD4_B, writeD4L);
not #(1) U308(hnl_463, pd3);
not #(1) U305(writeD0_B, writeD0L);
not #(1) U300(hnl_526, serialInEven);
u5InLat3 I258(dataIn3, hnl_664, writeD0L, pd3, writeD0_B);
u5InLat3 I257(dataIn1, hnl_663, writeD0L, pd1, writeD0_B);
u5InLat3 I256(dataIn2, hnl_668, writeD0L, pd2, writeD0_B);
u5InLat3 I255(dataIn0, hnl_666, writeD0L, pd0, writeD0_B);
u5InLat2 I252(hnl_665, pd1, InClk, hnl_661, InClkB);
u5InLat2 I251(hnl_667, pd0, InClk, hnl_662, InClkB);
u5InLat1 I250(hnl_661, InClkB, pd3, InClk);
u5InLat1 I249(hnl_662, InClkB, pd2, InClk);
endmodule

module u5IOpad (WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, chainOutEven, chainOutOdd, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, testBD, pad, DAmode_b, RDL_7_,
RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, regin0, regin1, regin2, regin3, serialInEven,
serialInOdd, srd, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
output WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, chainOutEven, chainOutOdd, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, testBD;
inout pad;
input DAmode_b, RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, regin0, regin1, regin2,
regin3, serialInEven, serialInOdd, srd, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe;
supply1 vdd;
supply0 gnd;
nor #(1) U129(chainIn_b, pwrdnRcvrs, hnl_669);
not #(1) I130(hnl_669, chain_b);
tranif1 N126(hnl_670, gnd, padin1);
probe I128(hnl_670);
u5OutClk Outclk(tclkl, tclklB, tclk);
u5InClk Inclk(InClk, InClkB, rclk);
u5DABuf DABuf(testBD, DAmode_b, padin2);
u5Output Output(chainOutEven, chainOutOdd, padin1, padin2, pad, RDL_7_, RDL_6_, RDL_5_, RDL_4_, RDL_3_, RDL_2_, RDL_1_, RDL_0_, inputDataEven, inputDataOdd, chain_b, ictrl_5_, ictrl_4_, ictrl_3_,
ictrl_2_, ictrl_1_, ictrl_0_, regin0, regin1, regin2, regin3, srd, sytload_b, tclkl, tclklB, testLoad_b, writeSenseAmpPipe);
u5Input Input(WDL_7_, WDL_6_, WDL_5_, WDL_4_, WDL_3_, WDL_2_, WDL_1_, WDL_0_, dataIn0, dataIn1, dataIn2, dataIn3, pd0, pd1, pd2, pd3, inputDataEven, inputDataOdd, InClk, InClkB, VRefin, chainIn_b,
padin1, pwrdnRcvrs, rclk, serialInEven, serialInOdd, writeD0123, writeD4567);
endmodule

module u5DataIO (mergedWDL_7_, mergedWDL_6_, mergedWDL_5_, mergedWDL_4_, mergedWDL_3_, mergedWDL_2_, mergedWDL_1_, mergedWDL_0_, mergedWDL_15_, mergedWDL_14_, mergedWDL_13_, mergedWDL_12_,
mergedWDL_11_, mergedWDL_10_, mergedWDL_9_, mergedWDL_8_, mergedWDL_23_, mergedWDL_22_, mergedWDL_21_, mergedWDL_20_, mergedWDL_19_, mergedWDL_18_, mergedWDL_17_, mergedWDL_16_, mergedWDL_31_,
mergedWDL_30_, mergedWDL_29_, mergedWDL_28_, mergedWDL_27_, mergedWDL_26_, mergedWDL_25_, mergedWDL_24_, mergedWDL_39_, mergedWDL_38_, mergedWDL_37_, mergedWDL_36_, mergedWDL_35_, mergedWDL_34_,
mergedWDL_33_, mergedWDL_32_, mergedWDL_47_, mergedWDL_46_, mergedWDL_45_, mergedWDL_44_, mergedWDL_43_, mergedWDL_42_, mergedWDL_41_, mergedWDL_40_, mergedWDL_55_, mergedWDL_54_, mergedWDL_53_,
mergedWDL_52_, mergedWDL_51_, mergedWDL_50_, mergedWDL_49_, mergedWDL_48_, mergedWDL_63_, mergedWDL_62_, mergedWDL_61_, mergedWDL_60_, mergedWDL_59_, mergedWDL_58_, mergedWDL_57_, mergedWDL_56_,
mergedWDL_71_, mergedWDL_70_, mergedWDL_69_, mergedWDL_68_, mergedWDL_67_, mergedWDL_66_, mergedWDL_65_, mergedWDL_64_, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_,
dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_,
dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_,
pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_,
pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_, pd3_0_, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_, BusData_8_, BusData_7_, BusData_6_, BusData_5_,
BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_,
dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_,
dataZ3_1_, dataZ3_0_, DAmode_b, mergedRDL_7_, mergedRDL_6_, mergedRDL_5_, mergedRDL_4_, mergedRDL_3_, mergedRDL_2_, mergedRDL_1_, mergedRDL_0_, mergedRDL_15_, mergedRDL_14_, mergedRDL_13_,
mergedRDL_12_, mergedRDL_11_, mergedRDL_10_, mergedRDL_9_, mergedRDL_8_, mergedRDL_23_, mergedRDL_22_, mergedRDL_21_, mergedRDL_20_, mergedRDL_19_, mergedRDL_18_, mergedRDL_17_, mergedRDL_16_,
mergedRDL_31_, mergedRDL_30_, mergedRDL_29_, mergedRDL_28_, mergedRDL_27_, mergedRDL_26_, mergedRDL_25_, mergedRDL_24_, mergedRDL_39_, mergedRDL_38_, mergedRDL_37_, mergedRDL_36_, mergedRDL_35_,
mergedRDL_34_, mergedRDL_33_, mergedRDL_32_, mergedRDL_47_, mergedRDL_46_, mergedRDL_45_, mergedRDL_44_, mergedRDL_43_, mergedRDL_42_, mergedRDL_41_, mergedRDL_40_, mergedRDL_55_, mergedRDL_54_,
mergedRDL_53_, mergedRDL_52_, mergedRDL_51_, mergedRDL_50_, mergedRDL_49_, mergedRDL_48_, mergedRDL_63_, mergedRDL_62_, mergedRDL_61_, mergedRDL_60_, mergedRDL_59_, mergedRDL_58_, mergedRDL_57_,
mergedRDL_56_, mergedRDL_71_, mergedRDL_70_, mergedRDL_69_, mergedRDL_68_, mergedRDL_67_, mergedRDL_66_, mergedRDL_65_, mergedRDL_64_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_,
ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
output mergedWDL_7_, mergedWDL_6_, mergedWDL_5_, mergedWDL_4_, mergedWDL_3_, mergedWDL_2_, mergedWDL_1_, mergedWDL_0_, mergedWDL_15_, mergedWDL_14_, mergedWDL_13_, mergedWDL_12_, mergedWDL_11_,
mergedWDL_10_, mergedWDL_9_, mergedWDL_8_, mergedWDL_23_, mergedWDL_22_, mergedWDL_21_, mergedWDL_20_, mergedWDL_19_, mergedWDL_18_, mergedWDL_17_, mergedWDL_16_, mergedWDL_31_, mergedWDL_30_,
mergedWDL_29_, mergedWDL_28_, mergedWDL_27_, mergedWDL_26_, mergedWDL_25_, mergedWDL_24_, mergedWDL_39_, mergedWDL_38_, mergedWDL_37_, mergedWDL_36_, mergedWDL_35_, mergedWDL_34_, mergedWDL_33_,
mergedWDL_32_, mergedWDL_47_, mergedWDL_46_, mergedWDL_45_, mergedWDL_44_, mergedWDL_43_, mergedWDL_42_, mergedWDL_41_, mergedWDL_40_, mergedWDL_55_, mergedWDL_54_, mergedWDL_53_, mergedWDL_52_,
mergedWDL_51_, mergedWDL_50_, mergedWDL_49_, mergedWDL_48_, mergedWDL_63_, mergedWDL_62_, mergedWDL_61_, mergedWDL_60_, mergedWDL_59_, mergedWDL_58_, mergedWDL_57_, mergedWDL_56_, mergedWDL_71_,
mergedWDL_70_, mergedWDL_69_, mergedWDL_68_, mergedWDL_67_, mergedWDL_66_, mergedWDL_65_, mergedWDL_64_, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_,
dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_,
dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_, pd0_1_,
pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_, pd3_3_,
pd3_2_, pd3_1_, pd3_0_, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_;
inout BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_,
dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_,
dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_, dataZ3_0_;
input DAmode_b, mergedRDL_7_, mergedRDL_6_, mergedRDL_5_, mergedRDL_4_, mergedRDL_3_, mergedRDL_2_, mergedRDL_1_, mergedRDL_0_, mergedRDL_15_, mergedRDL_14_, mergedRDL_13_, mergedRDL_12_,
mergedRDL_11_, mergedRDL_10_, mergedRDL_9_, mergedRDL_8_, mergedRDL_23_, mergedRDL_22_, mergedRDL_21_, mergedRDL_20_, mergedRDL_19_, mergedRDL_18_, mergedRDL_17_, mergedRDL_16_, mergedRDL_31_,
mergedRDL_30_, mergedRDL_29_, mergedRDL_28_, mergedRDL_27_, mergedRDL_26_, mergedRDL_25_, mergedRDL_24_, mergedRDL_39_, mergedRDL_38_, mergedRDL_37_, mergedRDL_36_, mergedRDL_35_, mergedRDL_34_,
mergedRDL_33_, mergedRDL_32_, mergedRDL_47_, mergedRDL_46_, mergedRDL_45_, mergedRDL_44_, mergedRDL_43_, mergedRDL_42_, mergedRDL_41_, mergedRDL_40_, mergedRDL_55_, mergedRDL_54_, mergedRDL_53_,
mergedRDL_52_, mergedRDL_51_, mergedRDL_50_, mergedRDL_49_, mergedRDL_48_, mergedRDL_63_, mergedRDL_62_, mergedRDL_61_, mergedRDL_60_, mergedRDL_59_, mergedRDL_58_, mergedRDL_57_, mergedRDL_56_,
mergedRDL_71_, mergedRDL_70_, mergedRDL_69_, mergedRDL_68_, mergedRDL_67_, mergedRDL_66_, mergedRDL_65_, mergedRDL_64_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
pwrdnRcvrs, rclk, selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe;
supply1 vdd;
supply0 gnd;
u5IOpad IOpad_8_(mergedWDL_71_, mergedWDL_70_, mergedWDL_69_, mergedWDL_68_, mergedWDL_67_, mergedWDL_66_, mergedWDL_65_, mergedWDL_64_, chainOutEven_8_, chainOutOdd_8_, dataIn0_8_, dataIn1_8_,
dataIn2_8_, dataIn3_8_, pd0_8_, pd1_8_, pd2_8_, pd3_8_, testBD_8_, BusData_8_, DAmode_b, mergedRDL_71_, mergedRDL_70_, mergedRDL_69_, mergedRDL_68_, mergedRDL_67_, mergedRDL_66_, mergedRDL_65_,
mergedRDL_64_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, n0, n1, n2, n3, chainOutEven_7_, chainOutOdd_7_, selRegData, sytload_b, tclk, testLoad_b,
writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_7_(mergedWDL_63_, mergedWDL_62_, mergedWDL_61_, mergedWDL_60_, mergedWDL_59_, mergedWDL_58_, mergedWDL_57_, mergedWDL_56_, chainOutEven_7_, chainOutOdd_7_, dataIn0_7_, dataIn1_7_,
dataIn2_7_, dataIn3_7_, pd0_7_, pd1_7_, pd2_7_, pd3_7_, testBD_7_, BusData_7_, DAmode_b, mergedRDL_63_, mergedRDL_62_, mergedRDL_61_, mergedRDL_60_, mergedRDL_59_, mergedRDL_58_, mergedRDL_57_,
mergedRDL_56_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_7_, dataZ1_7_, dataZ2_7_, dataZ3_7_, chainOutEven_6_, chainOutOdd_6_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_6_(mergedWDL_55_, mergedWDL_54_, mergedWDL_53_, mergedWDL_52_, mergedWDL_51_, mergedWDL_50_, mergedWDL_49_, mergedWDL_48_, chainOutEven_6_, chainOutOdd_6_, dataIn0_6_, dataIn1_6_,
dataIn2_6_, dataIn3_6_, pd0_6_, pd1_6_, pd2_6_, pd3_6_, testBD_6_, BusData_6_, DAmode_b, mergedRDL_55_, mergedRDL_54_, mergedRDL_53_, mergedRDL_52_, mergedRDL_51_, mergedRDL_50_, mergedRDL_49_,
mergedRDL_48_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_6_, dataZ1_6_, dataZ2_6_, dataZ3_6_, chainOutEven_5_, chainOutOdd_5_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_5_(mergedWDL_47_, mergedWDL_46_, mergedWDL_45_, mergedWDL_44_, mergedWDL_43_, mergedWDL_42_, mergedWDL_41_, mergedWDL_40_, chainOutEven_5_, chainOutOdd_5_, dataIn0_5_, dataIn1_5_,
dataIn2_5_, dataIn3_5_, pd0_5_, pd1_5_, pd2_5_, pd3_5_, testBD_5_, BusData_5_, DAmode_b, mergedRDL_47_, mergedRDL_46_, mergedRDL_45_, mergedRDL_44_, mergedRDL_43_, mergedRDL_42_, mergedRDL_41_,
mergedRDL_40_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_5_, dataZ1_5_, dataZ2_5_, dataZ3_5_, chainOutEven_4_, chainOutOdd_4_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_4_(mergedWDL_39_, mergedWDL_38_, mergedWDL_37_, mergedWDL_36_, mergedWDL_35_, mergedWDL_34_, mergedWDL_33_, mergedWDL_32_, chainOutEven_4_, chainOutOdd_4_, dataIn0_4_, dataIn1_4_,
dataIn2_4_, dataIn3_4_, pd0_4_, pd1_4_, pd2_4_, pd3_4_, testBD_4_, BusData_4_, DAmode_b, mergedRDL_39_, mergedRDL_38_, mergedRDL_37_, mergedRDL_36_, mergedRDL_35_, mergedRDL_34_, mergedRDL_33_,
mergedRDL_32_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_4_, dataZ1_4_, dataZ2_4_, dataZ3_4_, chainOutEven_3_, chainOutOdd_3_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_3_(mergedWDL_31_, mergedWDL_30_, mergedWDL_29_, mergedWDL_28_, mergedWDL_27_, mergedWDL_26_, mergedWDL_25_, mergedWDL_24_, chainOutEven_3_, chainOutOdd_3_, dataIn0_3_, dataIn1_3_,
dataIn2_3_, dataIn3_3_, pd0_3_, pd1_3_, pd2_3_, pd3_3_, testBD_3_, BusData_3_, DAmode_b, mergedRDL_31_, mergedRDL_30_, mergedRDL_29_, mergedRDL_28_, mergedRDL_27_, mergedRDL_26_, mergedRDL_25_,
mergedRDL_24_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_3_, dataZ1_3_, dataZ2_3_, dataZ3_3_, chainOutEven_2_, chainOutOdd_2_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_2_(mergedWDL_23_, mergedWDL_22_, mergedWDL_21_, mergedWDL_20_, mergedWDL_19_, mergedWDL_18_, mergedWDL_17_, mergedWDL_16_, chainOutEven_2_, chainOutOdd_2_, dataIn0_2_, dataIn1_2_,
dataIn2_2_, dataIn3_2_, pd0_2_, pd1_2_, pd2_2_, pd3_2_, testBD_2_, BusData_2_, DAmode_b, mergedRDL_23_, mergedRDL_22_, mergedRDL_21_, mergedRDL_20_, mergedRDL_19_, mergedRDL_18_, mergedRDL_17_,
mergedRDL_16_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_2_, dataZ1_2_, dataZ2_2_, dataZ3_2_, chainOutEven_1_, chainOutOdd_1_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_1_(mergedWDL_15_, mergedWDL_14_, mergedWDL_13_, mergedWDL_12_, mergedWDL_11_, mergedWDL_10_, mergedWDL_9_, mergedWDL_8_, chainOutEven_1_, chainOutOdd_1_, dataIn0_1_, dataIn1_1_,
dataIn2_1_, dataIn3_1_, pd0_1_, pd1_1_, pd2_1_, pd3_1_, testBD_1_, BusData_1_, DAmode_b, mergedRDL_15_, mergedRDL_14_, mergedRDL_13_, mergedRDL_12_, mergedRDL_11_, mergedRDL_10_, mergedRDL_9_,
mergedRDL_8_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_1_, dataZ1_1_, dataZ2_1_, dataZ3_1_, chainOutEven_0_, chainOutOdd_0_, selRegData,
sytload_b, tclk, testLoad_b, writeD0123, writeD4567, writeSenseAmpPipe);
u5IOpad IOpad_0_(mergedWDL_7_, mergedWDL_6_, mergedWDL_5_, mergedWDL_4_, mergedWDL_3_, mergedWDL_2_, mergedWDL_1_, mergedWDL_0_, chainOutEven_0_, chainOutOdd_0_, dataIn0_0_, dataIn1_0_, dataIn2_0_,
dataIn3_0_, pd0_0_, pd1_0_, pd2_0_, pd3_0_, testBD_0_, BusData_0_, DAmode_b, mergedRDL_7_, mergedRDL_6_, mergedRDL_5_, mergedRDL_4_, mergedRDL_3_, mergedRDL_2_, mergedRDL_1_, mergedRDL_0_, VRefin,
vdd, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, dataZ0_0_, dataZ1_0_, dataZ2_0_, dataZ3_0_, gnd, gnd, selRegData, sytload_b, tclk, testLoad_b, writeD0123,
writeD4567, writeSenseAmpPipe);
endmodule

module u5Skip (autoskip, framePulseX, mtclk, rxclkL, sampleskip, txclkL);
output autoskip;
input framePulseX, mtclk, rxclkL, sampleskip, txclkL;
supply1 vdd;
supply0 gnd;
latBNcA I18(hnl_671, framePulseX, hnl_672);
latBNcA I47(hnl_672, sampleskip, hnl_585);
tranif1 N45(hnl_673, hnl_674, txclkL);
tranif1 N38(hnl_674, gnd, vdd);
tranif0 P40(hnl_673, vdd, txclkL);
not #(1) I35(autoskip, hnl_196);
ffSync I34(hnl_196, mtclk, hnl_671);
not #(1) U32(rxdly, hnl_144);
not #(1) U31(hnl_144, rxclkL);
not #(1) U30(hnl_675, gnd);
not #(1) U26(hnl_676, gnd);
not #(1) U25(hnl_677, gnd);
not #(1) U24(hnl_412, gnd);
not #(1) U23(hnl_678, gnd);
not #(1) U16(hnl_34, hnl_675);
nand #(1) U6(skb, hnl_585, rout);
nand #(1) U5(hnl_585, skb, tout);
ffA ffT(tout, rxdly, txclkL);
ffA ffR(rout, txclkL, rxdly);
endmodule

module u5DABufH (Out, En_b, In);
output Out;
input En_b, In;
supply1 vdd;
supply0 gnd;
not (weak0,weak1) #(1) U24(hnl_679, hnl_677);
nor #(1) U35(hnl_85, En_b, hnl_677);
tranif1 N31(hnl_680, gnd, In);
tranif1 N30(hnl_679, hnl_680, hnl_676);
tranif0 P29(hnl_679, hnl_681, En_b);
tranif0 P28(hnl_681, vdd, In);
not #(1) U26(hnl_676, En_b);
not #(1) U25(hnl_677, hnl_679);
not #(1) U17(Out, hnl_85);
endmodule

module u5Clk (DLLpwrdn, Rx_2, TestRASB, autoSkip, mclk, mtclk, rclk_b, rxclkL, slow, tclk_b, txclkL, DAmode_b, DLLByPassMode_b, RxClk, TxClk, VRefin, checkskip, clearCount_b, framePulseX,
powerDownMode, runclk_b, runtclk, sampleskip, turboDLL_b);
output DLLpwrdn, Rx_2, TestRASB, autoSkip, mclk, mtclk, rclk_b, rxclkL, slow, tclk_b, txclkL;
input DAmode_b, DLLByPassMode_b, RxClk, TxClk, VRefin, checkskip, clearCount_b, framePulseX, powerDownMode, runclk_b, runtclk, sampleskip, turboDLL_b;
supply1 vdd;
supply0 gnd;
not #(1) U100(DLLpwrdn, hnl_682);
nor #(1) U99(hnl_682, hnl_209, powerDownMode);
not #(1) U98(hnl_209, DAmode_b);
tranif0 N90(hnl_683, vdd, hnl_684);
tranif1 N86(hnl_685, gnd, hnl_684);
tranif1 N96(hnl_686, gnd, hnl_687);
tranif1 N89(hnl_688, gnd, hnl_684);
probe I95(hnl_686);
probe I93(hnl_683);
probe I92(hnl_688);
probe I85(hnl_685);
u5DLL DLL(rclk_b, mtclk, tclk_b, mclk, Vbiasn, rxclkL, txclkL, slow, runclk_b, runtclk, hnl_687, hnl_684, VRefin, DLLpwrdn, turboDLL_b, DLLByPassMode_b, DAmode_b);
u5Skip Skip(autoSkip, framePulseX, mtclk, rxclkL, sampleskip, txclkL);
u5Sync Sync(Rx_2, hnl_687, clearCount_b, VRefin, Vbiasn);
u5DABufH DABufH(TestRASB, DAmode_b, hnl_684);
u5InProt RxClkInProt(hnl_687, RxClk);
u5InProt TxClkInProt(hnl_684, TxClk);
endmodule

module u5ClkDrv (rclk, tclk, rclk_b, tclk_b);
inout rclk, tclk;
input rclk_b, tclk_b;
supply1 vdd;
supply0 gnd;
not #(1) U82(rclk, rclk_b);
not #(1) U80(tclk, tclk_b);
endmodule

module u5BCIn (Last_b, OpX_1_, OpX_0_, RawLast, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl_in, VRefin, ackWinOverD, loadLast, powerDownMode, rclk, reset,
standby, writeA45, writeA0123, writeA0123x);
output Last_b, OpX_1_, OpX_0_, RawLast, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_;
input BusCtrl_in, VRefin, ackWinOverD, loadLast, powerDownMode, rclk, reset, standby, writeA45, writeA0123, writeA0123x;
supply1 vdd;
supply0 gnd;
ffRA I61(hnl_689, rclk, reset_b, hnl_690);
ffRC I98(frameEnableX, rclk, pwrdnB, hnl_691);
nand #(1) U116(framePulse_b, frameRaw, frameEnableX);
not #(1) U118(frameRaw_b, frameRaw);
not #(1) U123(hnl_690, hnl_692);
not #(1) U115(hnl_693, writeA45);
ltxRB I103(hnl_202, preOpX_b, writeA0123x, reset_b);
ltxRB I37(hnl_193, preOpX_b, writeA45, reset_b);
ltxRB I35(hnl_195, preOp1, writeA0123x, hnl_694);
ltxRB I42(hnl_695, preOp2, writeA0123x, reset_b);
not #(1) U104(pwrdnB, powerDownMode);
nand #(1) U102(hnl_696, preOp1, preOp2, preOpX_b);
not #(1) U99(OpX_1_, hnl_202);
latBarSB #(1) I101(hnl_697, preOpX_b, writeA0123D, reset);
latBarSB #(1) I11(Last_b, preOp1, loadLast, hnl_698);
ffA I85(writeA0123D, writeA0123, rclk);
not #(1) I97(opcode_b_1_, hnl_195);
not #(1) I96(opcode_b_2_, hnl_695);
not #(1) U90(OpX_0_, hnl_193);
latSB #(1) I86(hnl_699, hnl_696, writeA0123, reset);
nand #(1) U68(hnl_698, hnl_693, reset_b);
nor #(1) U87(bcastWriteA, hnl_699, hnl_697);
nor #(1) I57(hnl_691, standby, hnl_690);
mux21 #(1) I54(hnl_692, framePulse_b, ackWinOverD, hnl_689);
latBEnbA I50(hnl_92, preOp2, rclk);
latBarA I51(preOpX_b, rclk, frameRaw);
latBarA I49(preOp1, rclk, hnl_92);
u5DfLat I47(preOp2, hnl_700, hnl_701, rclk, pwrdnB);
u5OIRcvr I46(hnl_701, hnl_700, powerDownMode, BusCtrl_in, rclk, VRefin);
u5DfLatB I45(frameRaw, hnl_702, hnl_703, rclk, pwrdnB);
u5EIRcvr I44(hnl_702, hnl_703, powerDownMode, VRefin, BusCtrl_in, rclk);
nor #(1) U70(hnl_694, reset, powerDownMode);
not #(1) U105(RawLast, hnl_92);
not #(1) U1(reset_b, reset);
endmodule

module u5BCOut (padin1, padin2, pad, BCOeven_b, BCOodd_b, BC_oe, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, mtclk);
output padin1, padin2;
inout pad;
input BCOeven_b, BCOodd_b, BC_oe, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, mtclk;
supply1 vdd;
supply0 gnd;
not #(1) ine(tclkL_b, outd);
nand #(1) nanda(outa, mtclk, BC_oe);
nand #(1) nandc(outc, mtclk, BC_oe);
P4res Rin3(hnl_704, padin1);
P4res Rin2(pad, hnl_704);
P4res Rin1(pad, padin2);

buf #(1) TRA1(tra1, BCOodd_b);
cxfr U603(hnl_705, tclkL_b, tclkL, tra1);

buf #(1) TRA2(tra2, BCOeven_b);
cxfr U602(hnl_627, tclkL, tclkL_b, tra2);

//cxfr U603(hnl_705, tclkL_b, tclkL, BCOodd_b);
//cxfr U602(hnl_627, tclkL, tclkL_b, BCOeven_b);
latW U604(nkT14, hnl_705);
latW U601(okT13, hnl_627);
not #(1) ind(outd, outc);
not #(1) inb(tclkL, outa);
u5OutMux I590(q0, q1, q2, q3, q4, q5, okT13, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, nkT14, tclkL, tclkL_b);
u5OutDrv I589(pad, q0, q1, q2, q3, q4, q5);
endmodule

module u5BClog (Last_b, OpX_1_, OpX_0_, RawLast, TestCAS, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl, BCOeven_b, BCOodd_b, BC_oe, DAmode_b, VRefin,
ackWinOverD, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, mtclk, powerDownMode, rclk, reset, standby, writeA45, writeA0123, writeA0123x);
output Last_b, OpX_1_, OpX_0_, RawLast, TestCAS, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_;
inout BusCtrl;
input BCOeven_b, BCOodd_b, BC_oe, DAmode_b, VRefin, ackWinOverD, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, mtclk, powerDownMode, rclk, reset, standby, writeA45,
writeA0123, writeA0123x;
supply1 vdd;
supply0 gnd;
tranif1 N137(hnl_706, gnd, BusCtrl_in);
probe I136(hnl_706);
u5BCIn BCIn(Last_b, OpX_1_, OpX_0_, RawLast, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl_in, VRefin, ackWinOverD, loadLast, powerDownMode, rclk, reset,
standby, writeA45, writeA0123, writeA0123x);
u5DABuf I122(TestCAS, DAmode_b, hnl_707);
u5BCOut BCOut(BusCtrl_in, hnl_707, BusCtrl, BCOeven_b, BCOodd_b, BC_oe, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, mtclk);
endmodule

module u5Top(SOut, BusCtrl, BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, BusEnable, RxClk, SIn, TxClk, VRef);
output SOut;
inout BusCtrl, BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_, BusEnable;
input RxClk, SIn, TxClk, VRef;
supply1 vdd;
supply0 gnd;
lvtncap Cbypass(gnd, vdd);
u5StdCel I1(ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_, AGEGND, AGEING, BCOeven_b, BCOodd_b, BC_oe, BSEL, CAS, CMPF, CMPV, DAmode_b, DLLByPassMode_b, HVST, MPBT, PDMD,
RASB, REQ, ROLLC, RSTR, SDST, testSOut, VCMNA, VRST, WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_, WML, WPBT, WRITE, ackWinOverD, chain_b, checkskip, clearCount_b, control_5_, control_4_,
control_3_, control_2_, control_1_, control_0_, deviceEnableMode, enableSOut, framePulseX, gated_mclk, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, powerDownMode, powerOn,
pwrdnRcvrs, reset, resetCap, runtclk, sampleskip, selRegData, standby, stbybWak, sytload_b, testLoad_b, turboDLL_b, writeA45, writeA0123, writeA0123x, writeD0123, writeD4567, writeSenseAmpPipe,
RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_,
RDL2_1_, RDL2_0_, RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_,
RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_, RDL8_6_,
RDL8_5_, RDL8_4_, RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_,
dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_, dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_,
dataZ3_0_, BEevenD, BEoddD, BIMDI, Last_b, OpX_1_, OpX_0_, PON, RCRED, RawLast, Rx_2, SInRaw_b, TestCAS, TestRASB, TestRSTR, VREG, VRefin, WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_,
WDL0_1_, WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_,
WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_,
WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_, WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_,
autoSkip, bcastWriteA, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_, dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_,
dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_, dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_,
dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, done, frameEnableX, framePulse_b, frameRaw_b, lowVref, mclk, mtclk, opcode_b_2_, opcode_b_1_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_,
pd0_1_, pd0_0_, pd1_8_, pd1_7_, pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_,
pd3_3_, pd3_2_, pd3_1_, pd3_0_, rawBE_b, rclk, runclk_b, slow, testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_);
u5MemC MemC(PON, VREG, RCRED, {RDL0_7_, RDL0_6_, RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_}, {RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_}, {RDL2_7_, RDL2_6_,
RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_}, {RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_}, {RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_,
RDL4_0_}, {RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_}, {RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_, RDL5_1_, RDL5_0_}, {RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_,
RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_}, {RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_}, BIMDI, {WE_7_, WE_6_, WE_5_, WE_4_, WE_3_, WE_2_, WE_1_, WE_0_}, WML, REQ, WRITE, CAS,
BSEL, {ADR_8_, ADR_7_, ADR_6_, ADR_5_, ADR_4_, ADR_3_, ADR_2_, ADR_1_, ADR_0_}, RSTR, RASB, MPBT, WPBT, PDMD, HVST, AGEGND, AGEING, VRST, SDST, ROLLC, VCMNA, {WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_,
WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_}, {WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_}, {WDL5_7_, WDL5_6_, WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_}, {WDL1_7_,
WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_}, {WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_}, {WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_, WDL2_3_, WDL2_2_,
WDL2_1_, WDL2_0_}, {WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_}, {WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_}, {WDL0_7_, WDL0_6_, WDL0_5_,
WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_});
u5IOgnd hnl_708(gnd, vdd);
u5IOgnd hnl_709(gnd, vdd);
u5IOgnd hnl_710(gnd, vdd);
u5IOgnd hnl_711(gnd, vdd);
u5IOgnd hnl_712(gnd, vdd);
u5BEInpt BEInpt(BEevenD, BEoddD, TestRSTR, rawBE_b, runclk_b, BusEnable, DAmode_b, VRefin, powerDownMode, rclk, stbybWak);
u5SIO SIO(SInRaw_b, SOut, VRefin, lowVref, CMPF, CMPV, DAmode_b, SIn, testSOut, VRef, deviceEnableMode, enableSOut, tclk);
u5DataIO DataIO(WDL0_7_, WDL0_6_, WDL0_5_, WDL0_4_, WDL0_3_, WDL0_2_, WDL0_1_, WDL0_0_, WDL1_7_, WDL1_6_, WDL1_5_, WDL1_4_, WDL1_3_, WDL1_2_, WDL1_1_, WDL1_0_, WDL2_7_, WDL2_6_, WDL2_5_, WDL2_4_,
WDL2_3_, WDL2_2_, WDL2_1_, WDL2_0_, WDL3_7_, WDL3_6_, WDL3_5_, WDL3_4_, WDL3_3_, WDL3_2_, WDL3_1_, WDL3_0_, WDL4_7_, WDL4_6_, WDL4_5_, WDL4_4_, WDL4_3_, WDL4_2_, WDL4_1_, WDL4_0_, WDL5_7_, WDL5_6_,
WDL5_5_, WDL5_4_, WDL5_3_, WDL5_2_, WDL5_1_, WDL5_0_, WDL6_7_, WDL6_6_, WDL6_5_, WDL6_4_, WDL6_3_, WDL6_2_, WDL6_1_, WDL6_0_, WDL7_7_, WDL7_6_, WDL7_5_, WDL7_4_, WDL7_3_, WDL7_2_, WDL7_1_, WDL7_0_,
WDL8_7_, WDL8_6_, WDL8_5_, WDL8_4_, WDL8_3_, WDL8_2_, WDL8_1_, WDL8_0_, chainOutEven_8_, chainOutOdd_8_, dataIn0_7_, dataIn0_6_, dataIn0_5_, dataIn0_4_, dataIn0_3_, dataIn0_2_, dataIn0_1_,
dataIn0_0_, dataIn1_7_, dataIn1_6_, dataIn1_5_, dataIn1_4_, dataIn1_3_, dataIn1_2_, dataIn1_1_, dataIn1_0_, dataIn2_7_, dataIn2_6_, dataIn2_5_, dataIn2_4_, dataIn2_3_, dataIn2_2_, dataIn2_1_,
dataIn2_0_, dataIn3_7_, dataIn3_6_, dataIn3_5_, dataIn3_4_, dataIn3_3_, dataIn3_2_, dataIn3_1_, dataIn3_0_, pd0_8_, pd0_7_, pd0_6_, pd0_5_, pd0_4_, pd0_3_, pd0_2_, pd0_1_, pd0_0_, pd1_8_, pd1_7_,
pd1_6_, pd1_5_, pd1_4_, pd1_3_, pd1_2_, pd1_1_, pd1_0_, pd2_8_, pd2_7_, pd2_6_, pd2_5_, pd2_4_, pd2_3_, pd2_2_, pd2_1_, pd2_0_, pd3_8_, pd3_7_, pd3_6_, pd3_5_, pd3_4_, pd3_3_, pd3_2_, pd3_1_, pd3_0_,
testBD_8_, testBD_7_, testBD_6_, testBD_5_, testBD_4_, testBD_3_, testBD_2_, testBD_1_, testBD_0_, BusData_8_, BusData_7_, BusData_6_, BusData_5_, BusData_4_, BusData_3_, BusData_2_, BusData_1_,
BusData_0_, dataZ0_7_, dataZ0_6_, dataZ0_5_, dataZ0_4_, dataZ0_3_, dataZ0_2_, dataZ0_1_, dataZ0_0_, dataZ1_7_, dataZ1_6_, dataZ1_5_, dataZ1_4_, dataZ1_3_, dataZ1_2_, dataZ1_1_, dataZ1_0_, dataZ2_7_,
dataZ2_6_, dataZ2_5_, dataZ2_4_, dataZ2_3_, dataZ2_2_, dataZ2_1_, dataZ2_0_, dataZ3_7_, dataZ3_6_, dataZ3_5_, dataZ3_4_, dataZ3_3_, dataZ3_2_, dataZ3_1_, dataZ3_0_, DAmode_b, RDL0_7_, RDL0_6_,
RDL0_5_, RDL0_4_, RDL0_3_, RDL0_2_, RDL0_1_, RDL0_0_, RDL1_7_, RDL1_6_, RDL1_5_, RDL1_4_, RDL1_3_, RDL1_2_, RDL1_1_, RDL1_0_, RDL2_7_, RDL2_6_, RDL2_5_, RDL2_4_, RDL2_3_, RDL2_2_, RDL2_1_, RDL2_0_,
RDL3_7_, RDL3_6_, RDL3_5_, RDL3_4_, RDL3_3_, RDL3_2_, RDL3_1_, RDL3_0_, RDL4_7_, RDL4_6_, RDL4_5_, RDL4_4_, RDL4_3_, RDL4_2_, RDL4_1_, RDL4_0_, RDL5_7_, RDL5_6_, RDL5_5_, RDL5_4_, RDL5_3_, RDL5_2_,
RDL5_1_, RDL5_0_, RDL6_7_, RDL6_6_, RDL6_5_, RDL6_4_, RDL6_3_, RDL6_2_, RDL6_1_, RDL6_0_, RDL7_7_, RDL7_6_, RDL7_5_, RDL7_4_, RDL7_3_, RDL7_2_, RDL7_1_, RDL7_0_, RDL8_7_, RDL8_6_, RDL8_5_, RDL8_4_,
RDL8_3_, RDL8_2_, RDL8_1_, RDL8_0_, VRefin, chain_b, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, pwrdnRcvrs, rclk, selRegData, sytload_b, tclk, testLoad_b, writeD0123, writeD4567,
writeSenseAmpPipe);
u5Clk Clk(hnl_713, Rx_2, TestRASB, autoSkip, mclk, mtclk, rclk_b, hnl_714, slow, tclk_b, hnl_715, DAmode_b, DLLByPassMode_b, RxClk, TxClk, VRefin, checkskip, clearCount_b, framePulseX, powerDownMode,
runclk_b, runtclk, sampleskip, turboDLL_b);
u5ClkDrv LeftCk(rclk, tclk, rclk_b, tclk_b);
u5ClkDrv RightClk(rclk, tclk, rclk_b, tclk_b);
u5CCAna CCAna({ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_}, done, {control_5_, control_4_, control_3_, control_2_, control_1_, control_0_}, resetCap, powerOn, VRefin, gated_mclk);
u5BClog BClog(Last_b, OpX_1_, OpX_0_, RawLast, TestCAS, bcastWriteA, frameEnableX, framePulse_b, frameRaw_b, opcode_b_2_, opcode_b_1_, BusCtrl, BCOeven_b, BCOodd_b, BC_oe, DAmode_b, VRefin,
ackWinOverD, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadLast, mtclk, powerDownMode, rclk, reset, standby, writeA45, writeA0123, writeA0123x);
endmodule