`timescale 1ns/1ns

module GCB_DDFF (q, qn, da, db, cpa, cpb, sdn, cdn);
   input da, db, cpa, cpb, sdn, cdn;
   output q, qn;
   reg tq;

   assign qn = (!sdn && !cdn) ? 1'b0 : ~q;
   assign q = (sdn && cdn) ? tq : (!sdn && cdn) ? 1'b1 : 1'b0;
   always @ (posedge cpa)
      tq <= #1 da;
   always @ (posedge cpb)
      tq <= #1 db;

endmodule