// This confidential and propriety software may be used
// only as authorized by a licensing agreement from
// Ocean Logic Pty Ltd http:/www.ocean-logic.com
// 
// In the event of publication, the following notice is
// applicable
// 
// (C) COPYRIGHT 2001 Ocean Logic Pty Ltd
// ALL RIGHTS RESERVED
//
// the entire notice must be reproduced on all
// authorized copies
// 
// File : addmod.vhd
// Author : Vincenzo Liguori
// Date : 01-03-02
// Version 1.0
// Abstract :
// This module implements a counter
// 
// addmodification history :
// Date      by  Version  Change description
// -------------------------------------------------
// 01-03-02  VL   1.0     Original

module addmod(
clk,
rstn,
en,
clrn,
endround,
inc,
raddr
);

// Inputs
input clk, rstn;
input en, clrn, endround;
input[1:0] inc;
// Outputs 
output[1:0] raddr;

wire   clk;
wire   rstn;
wire   en;
wire   clrn;
wire   endround;
wire  [1:0] inc;
reg  [1:0] raddr;


// Intermediate signals
wire [1:0] plus;

  assign plus = endround == 1'b 0 ? 2'b 01 : inc;
  always @(posedge clk or negedge rstn) begin
    if(rstn == 1'b 0) begin
      raddr <= {2{1'b0}};
    end else begin
      if(en == 1'b 1) begin
        if(clrn == 1'b 0) begin
          raddr <= {2{1'b0}};
        end
        else begin
          raddr <= raddr + plus;
        end
      end
    end
  end


endmodule