// This confidential and propriety software may be used
// only as authorized by a licensing agreement from
// Ocean Logic Pty Ltd http://www.ocean-logic.com
// 
// In the event of publication, the following notice is
// applicable
// 
// (C) COPYRIGHT 2001 Ocean Logic Pty Ltd
// ALL RIGHTS RESERVED
//
// the entire notice must be reproduced on all
// authorized copies
// 
// File : aes_d.vhd
// Author : Vincenzo Liguori
// Date : 02-03-02
// Version 1.0
// Abstract :
// This implements the AES decryption top module
// 
// Modification history :
// Date      by  Version  Change description
// -------------------------------------------------
// 02-03-02  VL   1.0     Original
// 08-07-02  frank        name change to avoid vcs module name conflict

module aes_d(
clk,
rstn,
en,
go,
ksize,
din,
key,
din_req,
dout,
dout_vld
);

// Inputs
input clk, rstn;
input en, go;
input[1:0] ksize;
input[31:0] din, key;
// Outputs 
output din_req;
output[31:0] dout;
output dout_vld;

wire   clk;
wire   rstn;
wire   en;
wire   go;
wire  [1:0] ksize;
wire  [31:0] din;
wire  [31:0] key;
wire   din_req;
wire  [31:0] dout;
wire   dout_vld;


wire  dinit;
wire [31:0] olddata;
wire  ibypass;
wire  final;
wire [1:0] raddr0;
wire [1:0] raddr1;
wire [1:0] raddr2;
wire [1:0] raddr3;
wire [1:0] waddr0;
wire [1:0] waddr1;
wire [1:0] waddr2;
wire [1:0] waddr3;

  assign din_req = dinit;
  aes_ctrl ct(
      // Inputs
    .clk(clk),
    .rstn(rstn),
    .en(en),
    .go(go),
    .ksize(ksize),
    // Outputs 
    .dinit(dinit),
    .ibypass(ibypass),
    .final(final),
    .raddr0(raddr0),
    .raddr1(raddr1),
    .raddr2(raddr2),
    .raddr3(raddr3),
    .waddr0(waddr0),
    .waddr1(waddr1),
    .waddr2(waddr2),
    .waddr3(waddr3),
    .dout_vld(dout_vld));

  // Status storage area
  aes_mem4 sm0(
      .clk(clk),
    .rstn(rstn),
    .en(en),
    .we(go),
    .ar(raddr0),
    .aw(waddr0),
    .din(dout[31:24] ),
    .dout(olddata[31:24] ));

  aes_mem4 sm1(
      .clk(clk),
    .rstn(rstn),
    .en(en),
    .we(go),
    .ar(raddr1),
    .aw(waddr1),
    .din(dout[23:16] ),
    .dout(olddata[23:16] ));

  aes_mem4 sm2(
      .clk(clk),
    .rstn(rstn),
    .en(en),
    .we(go),
    .ar(raddr2),
    .aw(waddr2),
    .din(dout[15:8] ),
    .dout(olddata[15:8] ));

  aes_mem4 sm3(
      .clk(clk),
    .rstn(rstn),
    .en(en),
    .we(go),
    .ar(raddr3),
    .aw(waddr3),
    .din(dout[7:0] ),
    .dout(olddata[7:0] ));

  // Main AES block
  aes_main ma(
      // Inputs
    .clk(clk),
    .rstn(rstn),
    .en(en),
    .dinit(dinit),
    .ibypass(ibypass),
    .final(final),
    .din(din),
    .olddata(olddata),
    .key(key),
    // Outputs 
    .dout(dout));


endmodule