// ----------------------------------------------------------------------------
//  Copyright 2001 VAutomation Inc. Nashua NH USA. All rights reserved.
//  This software is provided under license and contains proprietary
//  and confidential material which is the property of VAutomation Inc.
//  HTTP://www.vautomation.com
// ----------------------------------------------------------------------------
`timescale 1 ns / 1 ps  // timescale for following modules

// -----------------------------------------------------------------------------

module pvic_connection_interface (master_clock,
				  master_rst,
   device_1_t_cmdack,
   device_1_t_rdata,
   device_1_t_reop,
   device_1_t_rspval,
   device_1_t_addr,
   device_1_t_be,
   device_1_t_cmd,
   device_1_t_cmdval,
   device_1_t_eop,
   device_1_t_rspack,
   device_1_t_wdata,
   device_1_i_addr,
   device_1_i_be,
   device_1_i_cmd,
   device_1_i_cmdval,
   device_1_i_eop,
   device_1_i_rspack,
   device_1_i_wdata,
   device_1_i_cmdack,
   device_1_i_rdata,
   device_1_i_reop,
   device_1_i_rspval,
   pirq_1_irq_0,
   pirq_1_irq_1,
   pirq_1_irq_2,
   pirq_1_irq_3,
   pirq_1_irq_4,
   pirq_1_irq_5,
   pirq_1_irq_6,
   pirq_1_irq_7
);
input   master_clock;
input   master_rst;   
output   device_1_t_cmdack; //  Command Acknowledge
output   [31:0] device_1_t_rdata; //  Read Data
output   device_1_t_reop; //  Response End of Packet
output   device_1_t_rspval; //  Response Valid
input   [31:0] device_1_t_addr; //  Byte Address
input   [3:0] device_1_t_be; //  Byte enables
input   [1:0] device_1_t_cmd; //  Command 00=idle, 01=read, 10=write, 11=locked read
input   device_1_t_cmdval; //  Command Valid
input   device_1_t_eop; //  End Of Packet 
input   device_1_t_rspack; //  Unused
input   [31:0] device_1_t_wdata; //  Write Data
output   [31:0] device_1_i_addr; //  Byte Address
output   [3:0] device_1_i_be; //  Byte enables
output   [1:0] device_1_i_cmd; //  Command 00=idle, 01=read, 10=write, 11=locked read
output   device_1_i_cmdval; //  Command Valid
output   device_1_i_eop; //  End Of Packet 
output   device_1_i_rspack; //  Unused	
output   [31:0] device_1_i_wdata; //  Write Data
input   device_1_i_cmdack; //  Command Acknowledge
input   [31:0] device_1_i_rdata; //  Read Data
input   device_1_i_reop; //  Response End of Packet
input   device_1_i_rspval; //  Response Valid
input   pirq_1_irq_0; // IRQ0
input   pirq_1_irq_1; // IRQ1
input   pirq_1_irq_2; // IRQ2
input   pirq_1_irq_3; 
input   pirq_1_irq_4; // IRQ0
input   pirq_1_irq_5; // IRQ1
input   pirq_1_irq_6; // IRQ2
input   pirq_1_irq_7; 
//  BVCI Target
wire    device_1_t_cmdack; 
wire    [31:0] device_1_t_rdata; 
wire    device_1_t_reop; 
wire    device_1_t_rspval; 
wire    [31:0] device_1_i_addr; 
wire    [3:0] device_1_i_be; 
wire    [1:0] device_1_i_cmd; 
wire    device_1_i_cmdval; 
wire    device_1_i_eop; 
wire    device_1_i_rspack; 
wire    [31:0] device_1_i_wdata; 



//Put IN_SIG = 0, OUT_SIG = 1, INOUT_SIG = 3;

initial begin : startup
 $SignalInitVPI(
  0,    master_clock,
  0,    master_rst,
  1,   device_1_t_cmdack,
  1,   device_1_t_rdata,
  1,   device_1_t_reop,
  1,   device_1_t_rspval,
  0,    device_1_t_addr,
  0,    device_1_t_be,
  0,    device_1_t_cmd,
  0,    device_1_t_cmdval,
  0,    device_1_t_eop,
  0,    device_1_t_rspack,
  0,    device_1_t_wdata,
  1,   device_1_i_addr,
  1,   device_1_i_be,
  1,   device_1_i_cmd,
  1,   device_1_i_cmdval,
  1,   device_1_i_eop,
  1,   device_1_i_rspack,
  1,   device_1_i_wdata,
  0,    device_1_i_cmdack,
  0,    device_1_i_rdata,
  0,    device_1_i_reop,
  0,    device_1_i_rspval,
  0,    pirq_1_irq_0,
  0,    pirq_1_irq_1,
  0,    pirq_1_irq_2,
  0,    pirq_1_irq_3,
  0,    pirq_1_irq_4,
  0,    pirq_1_irq_5,
  0,    pirq_1_irq_6,
  0,    pirq_1_irq_7
   );
 
end

always @ (master_clock)
begin
   #(0);
   $SignalChangeCallbackVPI(
	master_clock,
	master_rst,
	device_1_t_cmdack,
	device_1_t_rdata,
	device_1_t_reop,
	device_1_t_rspval,
	device_1_t_addr,
	device_1_t_be,
	device_1_t_cmd,
	device_1_t_cmdval,
	device_1_t_eop,
	device_1_t_rspack,
	device_1_t_wdata,
	device_1_i_addr,
	device_1_i_be,
	device_1_i_cmd,
	device_1_i_cmdval,
	device_1_i_eop,
	device_1_i_rspack,
	device_1_i_wdata,
	device_1_i_cmdack,
	device_1_i_rdata,
	device_1_i_reop,
	device_1_i_rspval,
	pirq_1_irq_0,
	pirq_1_irq_1,
	pirq_1_irq_2,
	pirq_1_irq_3,
	pirq_1_irq_4,
	pirq_1_irq_5,
	pirq_1_irq_6,
	pirq_1_irq_7
    );
end


endmodule