/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- Input file was: vusb_bvci_tb
-- Date Created: Tue Jul 16 14:00:48 2002

*******************************************************************************/


`timescale 1 ns / 1 ps  // timescale for following modules

// ----------------------------------------------------------------------------
//  Copyright 2000 VAutomation Inc. Nashua NH USA. All rights reserved.
//  This software is provided under license and contains proprietary
//  and confidential material which is the property of VAutomation Inc.
//  HTTP://www.vautomation.com
// ----------------------------------------------------------------------------
//  File Name: $Workfile: vusb_bvci_tb.vhdl$
//  Revision: $Revision: 1.1.1.1 $
//  Description:
// 
//  Description:
//               This is the top level file for the standalone VUSB 1.1 test
//               bench with a BVCI interface. It instantiates the following
//               blocks:
// 
//                     vusb_bvci        - top level block of the vusb core with
//                                        BVCI interface
//                     vusbtst          - instantiation of vusb test bench
//                     pvic_connection_
//                     interface        - provides connection to dll
//  
// 
//  
// -----------------------------------------------------------------------------
//  This product is licensed to:
//  John Princen of RouteFree
// for use at site(s):
// broadon
// -----------Revision History--------------------------------------------------
//  $Log: 
//   18   VUSB      1.17        7/5/02 2:00:51 PM      Will Sanborn    Removed 
//         hub signals, which were not used.
//   17   VUSB      1.16        6/27/02 2:32:50 PM     Will Sanborn    Changed 
//         test bench so two separate clocks are used, one for system and one 
//         for clk48mhz, before they were both clocked off the 48 MHz clock.
//   16   VUSB      1.15        4/11/02 2:49:08 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   15   VUSB      1.14        2/8/02 11:25:56 AM     Tom Frechette   Changed 
//         name of interrupt.
//   14   VUSB      1.13        2/7/02 4:40:55 PM      Tom Frechette   Added 
//         sync and async resets to the top level.
//   13   VUSB      1.12        11/7/01 9:05:30 AM     Tom Frechette   Typos.
//   12   VUSB      1.11        11/7/01 9:00:57 AM     Tom Frechette   Bring in 
//         vbus sense to turn off dp_high and dm_high. Change the polarity of 
//         the dp_low and dm_low.
//   11   VUSB      1.10        7/23/01 2:25:16 PM     Tom Frechette   Added 
//         debug port.
//   10   VUSB      1.9         7/12/01 7:24:10 PM     Patrick Koran   Added 
//         reset to interface
//   9    VUSB      1.8         7/3/01 4:43:00 PM      Tom Frechette   Chnaged 
//         mode to a constant in vusb_cfg.
//   8    VUSB      1.7         6/26/01 11:23:01 AM    Tom Frechette   Changed 
//         usb_mode connection.
//   7    VUSB      1.6         6/22/01 9:10:00 AM     Tom Frechette   Changed 
//         name of config package
//   6    VUSB      1.5         6/21/01 10:42:07 AM    Tom Frechette   Added 
//         comments
//   5    VUSB      1.4         6/15/01 3:28:59 PM     Tom Frechette   Changed 
//         Architecture to be like ARC
//   4    VUSB      1.3         5/16/01 3:26:48 PM     Tom Frechette   Removed 
//         hc_mode en from top level. It wasn't connected to anything.
//   3    VUSB      1.2         5/15/01 10:42:31 AM    Tom Frechette   Added 
//         more interrupts to pvic and changed VUSB bus widths to be BVCI 
//         compliant
//   2    VUSB      1.1         5/8/01 4:13:52 PM      Tom Frechette   New host 
//         control
//   1    VUSB      1.0         5/2/01 4:03:43 PM      Tom Frechette   
//  $
//  $NoKeywords$
// -----------------------------------------------------------------------------
// ------------------------------------------------------------------------------
//  Copyright 1995 VAutomation Inc. Nashua NH (603)882-2282 ALL RIGHTS RESERVED.
//  This software is provided under license and contains proprietary and 
//  confidential material which is the property of VAutomation Inc.
// 
//  File: vusb_cfg.vhd	USB Configuration file.
// 
//  Revision: $Revision: 1.1.1.1 $
// 
//  Description: A Package file for the usb core that defines global usb constants
//      that contol how the VUSB core is synthesised.
// 
// ---------------------------------------------------------------------------
//  This product is licensed to:
//  $name$ of $company$
//  for use at site(s): 
//  $site$
// ------------------------------------------------------------------------------
//  Revision History
//  $Log: 
//   32   VUSB      1.31        7/5/02 9:15:50 AM      Chris Kolb      Moved 
//         VUSB build configruation Revision constant to vusb_cfg, and updated 
//         the rev number to 3.0.
//   31   VUSB      1.30        4/11/02 2:49:09 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   30   VUSB      1.29        3/18/02 10:52:11 AM    Tom Frechette   Changed 
//         IRQ_NUM default to 0x0.
//   29   VUSB      1.28        3/15/02 2:39:08 PM     Tom Frechette   Added 
//         Interupt info into add_info register.
//   28   VUSB      1.27        2/7/02 4:49:00 PM      Tom Frechette   Removed 
//         sync config variable.
//   27   VUSB      1.26        8/23/01 9:48:58 AM     Tom Frechette   
//   26   VUSB      1.25        7/25/01 3:41:35 PM     Tom Frechette   Changed 
//         FIFO Parameter Names.
//   25   VUSB      1.24        7/10/01 3:03:41 PM     Tom Frechette   Moved 
//         HOST comment for verilog.
//   24   VUSB      1.23        7/6/01 7:44:00 AM      Tom Frechette   Added 
//         host comments around host constant to make it look like vusb_sie.
//   23   VUSB      1.22        7/6/01 7:34:33 AM      Tom Frechette   Added 
//         device constant comment for ARC.
//   22   VUSB      1.21        7/3/01 4:42:08 PM      Tom Frechette   Changed 
//         mode to a constant in vusb_cfg.
//   21   VUSB      1.20        6/22/01 3:09:48 PM     Tom Frechette   Changed 
//         endpoint number.
//   20   VUSB      1.19        6/21/01 9:59:56 AM     Tom Frechette   Changed 
//         the name and added fifo constants
//   19   VUSB      1.18        6/21/01 9:51:24 AM     Tom Frechette   
//   18   VUSB      1.17        5/25/01 10:25:08 AM    Monika Leary    Set 
//         synchronous reset constant to '1'
//   17   VUSB      1.16        5/17/01 2:52:48 PM     Monika Leary    Added 
//         USE_SYNC_RESET constant
//   16   VUSB      1.15        12/14/00 8:42:11 AM    Christopher Meyers RCS 
//         Keyword To StarTeam Keyword Translation
//   15   VUSB      1.14        12/13/00 7:58:39 PM    Chris Kolb      Removed 
//         the HOST_WITHOUT_HUB constant. This control is now a Endpt0 control 
//         register bit in up_int.vhd.
//   14   VUSB      1.13        12/13/00 7:58:31 PM    Gregory Recupero Removed 
//         ^M's
//   13   VUSB      1.12        12/13/00 7:58:26 PM    Mark Pettigrew  
//         ulogicified source - no functional changes
//   12   VUSB      1.11        12/13/00 7:58:19 PM    Chris Kolb      Change 
//         type of HOST_WITHOUT_HUB from std_logic to integer so that it could 
//         be used to initialize a _synopsysTM(TM) compatible generic.
//   11   VUSB      1.10        12/13/00 7:58:14 PM    Chris Kolb      Set 
//         constant to support Host to Low Speed device thru a hub.
//   10   VUSB      1.9         12/13/00 7:58:07 PM    Chris Kolb      Changed 
//         LOW_SPEED_DEV constant to type integer to support generics.
//   9    VUSB      1.8         12/13/00 7:57:58 PM    Christopher Meyers 
//         removed ASIC_IMPLEMENTATION constant
//   8    VUSB      1.7         12/13/00 7:57:46 PM    Chris Kolb      Remove 
//         ^M's. No functional changes.
//   7    VUSB      1.6         12/13/00 7:57:39 PM    Chris Kolb      Added 
//         HOST_WITHOUT_HUB constant to support new code in the DPLLNRZI.
//   6    VUSB      1.5         12/13/00 7:57:19 PM    Chris Kolb      Turned 
//         host mode back on.
//   5    VUSB      1.4         12/13/00 7:57:12 PM    Chris Kolb      Reverted 
//         to device only implementation.
//   4    VUSB      1.3         12/13/00 7:57:08 PM    Chris Kolb      Added 
//         revision string.
//   3    VUSB      1.2         12/13/00 7:57:03 PM    Chris Kolb      Enabled 
//         implementation of embedded host functions.
//   2    VUSB      1.1         12/13/00 7:56:58 PM    Chris Kolb      Added 
//         IMPLEMENT_EMBEDED_HOST constant.
//   1    VUSB      1.0         12/13/00 7:56:51 PM    Chris Kolb      initial 
//         revision
//  $
// 
// 
// ------------------------------------------------------------------------------
module vusb_bvci_tb ;

 		// file containing translation of VHDL package 'vusb_cfg' 

wire    usb_clk; 
wire    usb_rst_a; 
wire    usb_clk48; 
wire    usb_rst48_a; 
wire    vdd; 
wire    gnd; 
//  BVCI Initiator Interface
wire    i_cmdack; //  init. command acknowledge
wire    [31:0] i_rdata; //  init. read data
wire    i_reop; //  init. response end of packet
wire    i_rspval; //  init. response valid
wire    [31:0] i_address; //  init. address
wire    [3:0] i_be; //  init. byte enables
wire    [1:0] i_cmd; //  init. command
wire    i_cmdval; //  init. command valid
wire    i_eop; //  init. end of packet
wire    i_rspack; //  init. response acknowledge
wire    [31:0] i_wdata; //  init. write data  
//  BVCI Target Interface
wire    [31:0] t_address; //  target address
wire    [3:0] t_be; //  target byte enables
wire    [1:0] t_cmd; //  target command
wire    t_cmdval; //  target command valid
wire    t_eop; //  target end of packet
wire    t_rspack; //  target response acknowledge
wire    [31:0] t_wdata; //  target write data
wire    t_cmdack; //  target command acknowledge
wire    [31:0] t_rdata; //  target read data
wire    t_reop; //  target response end of packet
wire    t_rspval; //  target response valid
wire    usb_int; 
//  usb signals
wire    usb_rcv; 
wire    usb_dp; 
wire    usb_dm; 
wire    usb_dpo; 
wire    usb_dmo; 
wire    usb_oe_n; 
wire    usb_speed; 
wire    usb_suspnd; 
//  pull-up resistor controls
wire    usb_dp_high; 
wire    usb_dp_low_n; 
wire    usb_dm_high; 
wire    usb_dm_low_n; 
//  OTG signals
wire    usb_id; 
wire    usb_a_vbus_vld; 
wire    usb_sess_vld; 
wire    usb_b_sess_end; 
wire    usb_vbus_on; 
wire    usb_vbus_chg; 
wire    usb_vbus_dschg; 
wire    usb_a_vbus_vld_n; 
wire    usb_sess_vld_n; 
wire    usb_b_sess_end_n; 
wire    usb_vbus_on_n; 
wire    usb_vbus_chg_n; 
wire    usb_vbus_dschg_n; 
// ---------------------------------------------------------------------------
//  test bench begins here
// ---------------------------------------------------------------------------

assign vdd = 1'b 1; 
assign gnd = 1'b 0; 
vusb_bvci u_vusb_bvci (.clk(usb_clk),
          .rst(usb_rst_a),
          .rst_a(usb_rst_a),
          .usb_clk48(usb_clk48),
          .usb_rst48(usb_rst48_a),
          .usb_rst48_a(usb_rst48_a),
          //  BVCI Initiator Interface
          .vusb_i_cmdack(i_cmdack),
          .vusb_i_rdata(i_rdata),
          .vusb_i_reop(i_reop),
          .vusb_i_rspval(i_rspval),
          .vusb_i_address(i_address),
          .vusb_i_be(i_be),
          .vusb_i_cmd(i_cmd),
          .vusb_i_cmdval(i_cmdval),
          .vusb_i_eop(i_eop),
          .vusb_i_rspack(i_rspack),
          .vusb_i_wdata(i_wdata),
          //  BVCI Target Interface
          .vusb_t_address(t_address),
          .vusb_t_be(t_be),
          .vusb_t_cmd(t_cmd),
          .vusb_t_cmdval(t_cmdval),
          .vusb_t_eop(t_eop),
          .vusb_t_rspack(t_rspack),
          .vusb_t_wdata(t_wdata),
          .vusb_t_cmdack(t_cmdack),
          .vusb_t_rdata(t_rdata),
          .vusb_t_reop(t_reop),
          .vusb_t_rspval(t_rspval),
          //  interrupt out
          .vusb_irq(usb_int),
          //  USB transceiver interfaces
          .usb_rcv(usb_rcv),
          .usb_dp(usb_dp),
          .usb_dm(usb_dm),
          .usb_vbus_in(vdd),
          .usb_dpo(usb_dpo),
          .usb_dmo(usb_dmo),
          .usb_oe_n(usb_oe_n),
          .usb_speed(usb_speed),
          .usb_suspnd(usb_suspnd),
          //  pull-up resistor controls
          .usb_dp_high(usb_dp_high),
          .usb_dp_low_n(usb_dp_low_n),
          .usb_dm_high(usb_dm_high),
          .usb_dm_low_n(usb_dm_low_n),
          //  OTG signals
          .usb_id(usb_id),
          .usb_a_vbus_vld(usb_a_vbus_vld),
          .usb_sess_vld(usb_sess_vld),
          .usb_b_sess_end(usb_b_sess_end),
          .usb_vbus_on(usb_vbus_on),
          .usb_vbus_chg(usb_vbus_chg),
          .usb_vbus_dschg(usb_vbus_dschg));
pvic_connection_interface u_pvic (.master_clock(usb_clk),
          .master_rst(usb_rst_a),
          //  cross connect the target & initiator
//  bvci target
          .device_1_t_cmdack(i_cmdack),
          .device_1_t_rdata(i_rdata),
          .device_1_t_reop(i_reop),
          .device_1_t_rspval(i_rspval),
          .device_1_t_addr(i_address),
          .device_1_t_be(i_be),
          .device_1_t_cmd(i_cmd),
          .device_1_t_cmdval(i_cmdval),
          .device_1_t_eop(i_eop),
          .device_1_t_rspack(i_rspack),
          .device_1_t_wdata(i_wdata),
          //  BVCI Initiator 
          .device_1_i_addr(t_address),
          .device_1_i_be(t_be),
          .device_1_i_cmd(t_cmd),
          .device_1_i_cmdval(t_cmdval),
          .device_1_i_eop(t_eop),
          .device_1_i_rspack(t_rspack),
          .device_1_i_wdata(t_wdata),
          .device_1_i_cmdack(t_cmdack),
          .device_1_i_rdata(t_rdata),
          .device_1_i_reop(t_reop),
          .device_1_i_rspval(t_rspval),
          //  interrupts
          .pirq_1_irq_0(usb_int),
          .pirq_1_irq_1(gnd),
          .pirq_1_irq_2(gnd),
          .pirq_1_irq_3(gnd),
          .pirq_1_irq_4(gnd),
          .pirq_1_irq_5(gnd),
          .pirq_1_irq_6(gnd),
          .pirq_1_irq_7(gnd));
vusb_tst u_vusb_tst (.usb_clk(usb_clk),
          .usb_rst_a(usb_rst_a),
          .usb_clk48(usb_clk48),
          .usb_rst48_a(usb_rst48_a),
          .usb_rcv(usb_rcv),
          .usb_dp(usb_dp),
          .usb_dm(usb_dm),
          .usb_dpo(usb_dpo),
          .usb_dmo(usb_dmo),
          .usb_oe_n(usb_oe_n),
          .usb_speed(usb_speed),
          .usb_suspnd(usb_suspnd),
          //  pull-up resistor controls
          .usb_dp_high(usb_dp_high),
          .usb_dp_low_n(usb_dp_low_n),
          .usb_dm_high(usb_dm_high),
          .usb_dm_low_n(usb_dm_low_n),
          //  OTG signals
          .usb_id(usb_id),
          .usb_a_vbus_vld_n(usb_a_vbus_vld_n),
          .usb_sess_vld_n(usb_sess_vld_n),
          .usb_b_sess_end_n(usb_b_sess_end_n),
          .usb_vbus_on_n(usb_vbus_on_n),
          .usb_vbus_chg_n(usb_vbus_chg_n),
          .usb_vbus_dschg_n(usb_vbus_dschg_n));
assign usb_sess_vld = ~usb_sess_vld_n; //  invert these signals
assign usb_a_vbus_vld = ~usb_a_vbus_vld_n; 
assign usb_b_sess_end = ~usb_b_sess_end_n; 
assign usb_vbus_on_n = ~usb_vbus_on; 
assign usb_vbus_chg_n = ~usb_vbus_chg; 
assign usb_vbus_dschg_n = ~usb_vbus_dschg; 

endmodule // module vusb_bvci_tb

//  VUSB synthesis and simulation configuration constants.