/****************************************************************************************
*
*    File Name:  MT46V8M16.V  
*      Version:  1.2
*         Date:  September 11th, 2001
*        Model:  BUS Functional
*    Simulator:  Model Technology
*
* Dependencies:  None
*
*       Author:  Son P. Huynh
*        Email:  sphuynh@micron.com
*        Phone:  (208) 368-3825
*      Company:  Micron Technology, Inc.
*  Part Number:  MT46V8M16 (2Meg x 16 x 4 Banks)
*
*  Description:  Micron 128Mb SDRAM DDR (Double Data Rate)
*
*   Limitation:  - Doesn't check for 4K-cycle refresh
*
*         Note:  - Set simulator resolution to "ps" accuracy
*                - Set Debug = 0 to disable $display messages
*                - Model assume Clk and Clk# crossing at both edge
*
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*                Copyright  1998 Micron Semiconductor Products, Inc.
*                All rights researved
*
* Rev  Author          Phone         Date        Changes
* ---  --------------  ------------  ----------  ---------------------------------------
* 1.2  Son Huynh       208-368-3825  09/11/2001  - Change $time to $realtime
*      Micron Technology Inc.                    - Add DLL, tRAP, and tRFC check
*                                                - Add Burst Terminate to Write check
*                                                - Fix tWR and tWTR check
*                                                - Fix Precharge to closed bank = NOP
*                                                - Fix DQ guarantee HiZ on power up
*
****************************************************************************************/

// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1ns / 1ps

module mt46v8m16 (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);

    // Constant Parameters
    parameter addr_bits =      12;
    parameter data_bits =      16;
    parameter col_bits  =       9;
    parameter mem_sizes = 2097151;

    // Port Declarations
    inout     [data_bits - 1 : 0] Dq;
    inout                 [1 : 0] Dqs;
    input     [addr_bits - 1 : 0] Addr;
    input                 [1 : 0] Ba;
    input                         Clk;
    input                         Clk_n;
    input                         Cke;
    input                         Cs_n;
    input                         Ras_n;
    input                         Cas_n;
    input                         We_n;
    input                 [1 : 0] Dm;

    // Memory Banks
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];

    reg                   [1 : 0] Bank_addr [0 : 8];
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
    reg        [col_bits - 1 : 0] Col_addr [0 : 8];
    reg                   [3 : 0] Command [0 : 8];

    reg       [addr_bits - 1 : 0] Mode_reg;
    reg       [data_bits - 1 : 0] Dq_dm, Dq_out;
    reg        [col_bits - 1 : 0] Col_temp, Burst_counter;

    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;
    reg                   [1 : 0] Dqs_int, Dqs_out;

    // Auto Precharge Parameters
    reg                   [1 : 0] Bank_precharge  [0 : 8];      // Precharge Command Bank
    reg                           A10_precharge   [0 : 8];      // Addr[10] = 1 (All Banks)
    reg                           Auto_precharge  [0 : 3];      // RW AutoPrecharge Bank
    reg                           Read_precharge  [0 : 3];      // R  AutoPrecharge Command
    reg                           Write_precharge [0 : 3];      // W  AutoPrecharge Command
    integer                       Count_precharge [0 : 3];      // RW AutoPrecharge Counter

    // Data Enable
    reg                           Data_in_enable;
    reg                           Data_out_enable;

    // Command and Dqs pipeline
    reg                   [3 : 0] Rw_command;
    reg                   [1 : 0] Bank, Bank_dqs, Previous_bank;
    reg       [addr_bits - 1 : 0] Row, Row_dqs;
    reg        [col_bits - 1 : 0] Col, Col_dqs;
    reg        [col_bits - 1 : 0] Col_brst, Col_brst_dqs;

    // Internal System Clock
    reg                           CkeZ, Sys_clk;

    // DLL Reset variable
    reg                           DLL_enable;
    reg                           DLL_reset;
    reg                           DLL_done;
    integer                       DLL_count;

    // DM variable for tWR and tWTR calculation
    reg                   [1 : 0] Dm_high;
    reg                   [6 : 0] Dm_pipe;

    // Burst Direction (only used in x32 part)
    reg                           Burst_dir, Burst_dir_dqs;
    reg                           Burst_dir_pipe [0 : 8];

    // Commands Decode
    wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
    wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
    wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
    wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[0] & ~Ba[1];
    wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
    wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
    wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
    wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;

    // Burst Length Decode
    wire      Burst_length_2  = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_4  = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
    wire      Burst_length_8  = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_f  =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];

    // CAS Latency Decode
    wire      Cas_latency_15  =  Mode_reg[6] & ~Mode_reg[5] &  Mode_reg[4];
    wire      Cas_latency_2   = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_25  =  Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_3   = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
    wire      Cas_latency_4   =  Mode_reg[6] & ~Mode_reg[5] & ~Mode_reg[4];

    wire      Debug = 1;                                    // Turn on Debug messages
    wire      Dq_in = Dqs & Data_in_enable;                 // For checking Data-in Setup/Hold time

    // DQ Buffer
    assign    Dq  = Dq_out;

    // DQS Buffer
    assign    Dqs = Dqs_out;

    // DQS Receiver
    wire      Dqs_rec = Dqs[1] & Dqs[0];

    //Commands Operation
    `define   ACT       0
    `define   NOP       1
    `define   READ      2
    `define   READ_A    3
    `define   WRITE     4
    `define   WRITE_A   5
    `define   PRECH     6
    `define   A_REF     7
    `define   BST       8
    `define   LMR       9
    `define   EMR      10

    // Timing Parameters for -75Z (CL = 2)
    parameter tCK  =   7.5;
    parameter tMRD =  15.0;
    parameter tRAS =  40.0;
    parameter tRC  =  65.0;
    parameter tRFC =  75.0;
    parameter tRCD =  20.0;
    parameter tRP  =  20.0;
    parameter tRRD =  15.0;
    parameter tWR  =  15.0;

    // Timing Check
    realtime  MRD_chk;
    realtime  RFC_chk;
    realtime  RRD_chk;
    realtime  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
    realtime  RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
    realtime  RC_chk0, RC_chk1, RC_chk2, RC_chk3;
    realtime  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
    realtime  RP_chk0, RP_chk1, RP_chk2, RP_chk3;
    realtime  WR_chk0, WR_chk1, WR_chk2, WR_chk3;
    realtime  tRAP;             // Time based on Burst Length

    initial begin
        CkeZ = 1'b0;
        Sys_clk = 1'b0;
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
        Dqs_int = 2'b00;
        Dqs_out = 2'bzz;
        Dq_out = {data_bits{1'bz}};
        Data_in_enable = 1'b0;
        Data_out_enable = 1'b0;
        DLL_enable = 1'b0;
        DLL_reset = 1'b0;
        DLL_done = 1'b0;
        DLL_count = 0;
        //$readmemh("bank0.txt", Bank0);
        //$readmemh("bank1.txt", Bank1);
        //$readmemh("bank2.txt", Bank2);
        //$readmemh("bank3.txt", Bank3);
        $timeformat (-9, 3, " ns", 12);
    end

    // System Clock
    always begin
        @ (posedge Clk) begin
            Sys_clk = CkeZ;
            CkeZ = Cke;
        end
        @ (negedge Clk) begin
            Sys_clk = 1'b0;
        end
    end

    // Main Process
    always @ (Sys_clk) begin
        // Internal Commamd Pipelined
        Command[0] = Command[1];
        Command[1] = Command[2];
        Command[2] = Command[3];
        Command[3] = Command[4];
        Command[4] = Command[5];
        Command[5] = Command[6];
        Command[6] = Command[7];
        Command[7] = Command[8];
        Command[8] = `NOP;

        Col_addr[0] = Col_addr[1];
        Col_addr[1] = Col_addr[2];
        Col_addr[2] = Col_addr[3];
        Col_addr[3] = Col_addr[4];
        Col_addr[4] = Col_addr[5];
        Col_addr[5] = Col_addr[6];
        Col_addr[6] = Col_addr[7];
        Col_addr[7] = Col_addr[8];
        Col_addr[8] = 0;

        Bank_addr[0] = Bank_addr[1];
        Bank_addr[1] = Bank_addr[2];
        Bank_addr[2] = Bank_addr[3];
        Bank_addr[3] = Bank_addr[4];
        Bank_addr[4] = Bank_addr[5];
        Bank_addr[5] = Bank_addr[6];
        Bank_addr[6] = Bank_addr[7];
        Bank_addr[7] = Bank_addr[8];
        Bank_addr[8] = 0;

        Burst_dir_pipe[0] = Burst_dir_pipe[1];
        Burst_dir_pipe[1] = Burst_dir_pipe[2];
        Burst_dir_pipe[2] = Burst_dir_pipe[3];
        Burst_dir_pipe[3] = Burst_dir_pipe[4];
        Burst_dir_pipe[4] = Burst_dir_pipe[5];
        Burst_dir_pipe[5] = Burst_dir_pipe[6];
        Burst_dir_pipe[6] = Burst_dir_pipe[7];
        Burst_dir_pipe[7] = Burst_dir_pipe[8];
        Burst_dir_pipe[8] = 0;

        // Precharge Pipeline
        Bank_precharge[0] = Bank_precharge[1];
        Bank_precharge[1] = Bank_precharge[2];
        Bank_precharge[2] = Bank_precharge[3];
        Bank_precharge[3] = Bank_precharge[4];
        Bank_precharge[4] = Bank_precharge[5];
        Bank_precharge[5] = Bank_precharge[6];
        Bank_precharge[6] = Bank_precharge[7];
        Bank_precharge[7] = Bank_precharge[8];
        Bank_precharge[8] = 2'b0;

        A10_precharge[0] = A10_precharge[1];
        A10_precharge[1] = A10_precharge[2];
        A10_precharge[2] = A10_precharge[3];
        A10_precharge[3] = A10_precharge[4];
        A10_precharge[4] = A10_precharge[5];
        A10_precharge[5] = A10_precharge[6];
        A10_precharge[6] = A10_precharge[7];
        A10_precharge[7] = A10_precharge[8];
        A10_precharge[8] = 1'b0;

        // Commands Operation decode
        if (Sys_clk === 1'b1) begin
            // DLL Reset Check
            if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
                DLL_count = DLL_count + 1;
                if (DLL_count >= 200) begin
                    DLL_done = 1'b1;
                end
            end

            // Read or Write with Auto Precharge Counter
            if (Auto_precharge[0] === 1'b1) begin
                Count_precharge[0] = Count_precharge[0] + 1;
            end
            if (Auto_precharge[1] === 1'b1) begin
                Count_precharge[1] = Count_precharge[1] + 1;
            end
            if (Auto_precharge[2] === 1'b1) begin
                Count_precharge[2] = Count_precharge[2] + 1;
            end
            if (Auto_precharge[3] === 1'b1) begin
                Count_precharge[3] = Count_precharge[3] + 1;
            end

            // tRAP = tRAS_min - (Burst Length * tCK / 2)
            if (Burst_length_2 === 1'b1) begin
                tRAP = tRAS - (2 * tCK / 2);
            end
            if (Burst_length_4 === 1'b1) begin
                tRAP = tRAS - (4 * tCK / 2);
            end
            if (Burst_length_8 === 1'b1) begin
                tRAP = tRAS - (8 * tCK / 2);
            end

            // tWR and tWTR start @ posedge of clock
            // [6 : 5] = Bank
            //     [4] = Data In
            // [3 : 2] = DM at posedge DQS
            // [1 : 0] = DM at negedge DQS
            if (Dm_pipe [4] === 1'b1) begin
                // DM interrupt cases
                if ((Dm_pipe[3 : 2] === 2'b00 && Dm_pipe [1 : 0] === 2'b00) ||          // EVEN
                    (Dm_pipe[3 : 2] === 2'b00 && Dm_pipe [1 : 0] === 2'b11) ||          // ODD
                    (Dm_pipe[3 : 2] === 2'b11 && Dm_pipe [1 : 0] === 2'b00)) begin      // ODD
                    
                    // tWR start
                    if (Dm_pipe [6 : 5] === 2'b00) begin
                        WR_chk0 = $realtime;
                    end
                    if (Dm_pipe [6 : 5] === 2'b01) begin
                        WR_chk1 = $realtime;
                    end
                    if (Dm_pipe [6 : 5] === 2'b10) begin
                        WR_chk2 = $realtime;
                    end
                    if (Dm_pipe [6 : 5] === 2'b11) begin
                        WR_chk3 = $realtime;
                    end
                    
                    // tWTR check
                    if (Read_enable === 1'b1) begin
                        $display ("%m : at time %t ERROR: tWTR violation", $realtime);
                    end
                end
            end

            // Auto Refresh
            if (Aref_enable === 1'b1) begin
                // Display Debug Message
                if (Debug) begin
                    $display ("%m : at time %t AREF : Auto Refresh", $realtime);
                end
                
                // Auto Refresh to Auto Refresh
                if ($realtime - RFC_chk < tRFC) begin
                    $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $realtime);
                end
                
                // Precharge to Auto Refresh
                if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
                    ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
                    $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
                end
                
                // Precharge to Auto Refresh
                if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
                    $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $realtime);
                end
                
                // Record Current tRFC time
                RFC_chk = $realtime;
            end
        
            // Extended Mode Register
            if (Ext_mode_enable === 1'b1) begin
                if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
                    if (Addr[0] === 1'b0) begin
                        DLL_enable = 1'b1;
                        if (Debug) begin
                            $display ("%m : at time %t EMR  : Enable DLL", $realtime);
                        end
                    end else begin
                        DLL_enable = 1'b0;
                        if (Debug) begin
                            $display ("%m : at time %t EMR  : Disable DLL", $realtime);
                        end
                    end
                end else begin
                    $display ("%m : at time %t ERROR: all banks must be Precharge before Extended Mode Register", $realtime);
                end

                // Precharge to EMR
                if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
                    ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
                    $display ("%m : at time %t ERROR: tRP violation during Extended Mode Register", $realtime);
                end

                // LMR/EMR to LMR/EMR
                if ($realtime - MRD_chk < tMRD) begin
                    $display ("%m : at time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
                end

                // Record current tMRD time
                MRD_chk = $realtime;
            end
        
            // Load Mode Register
            if (Mode_reg_enable === 1'b1) begin
                // Decode DLL, CAS Latency, Burst Type, and Burst Length
                if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
                    Mode_reg = Addr;
                    if (Debug) begin
                        $display ("%m : at time %t LMR  : Load Mode Register", $realtime);
                        // Operating mode
                        if (Addr [11 : 7] === 5'b00000) begin
                            $display ("                                            Normal Operation");
                        end else if (Addr [11 : 7] === 5'b00010) begin
                            $display ("                                            Reset DLL");
                        end else begin
                            $display ("                                            Invalid Operating Mode");
                        end
                        
                        // CAS Latency
                        if (Addr[6 : 4] === 3'b101) begin
                            $display ("                                            CAS Latency  = 1.5");
                        end else if (Addr[6 : 4] === 3'b010) begin
                            $display ("                                            CAS Latency  = 2.0");
                        end else if (Addr[6 : 4] === 3'b110) begin
                            $display ("                                            CAS Latency  = 2.5");
                        end else if (Addr[6 : 4] === 3'b011) begin
                            $display ("                                            CAS Latency  = 3.0");
                        end else if (Addr[6 : 4] === 3'b100) begin
                            $display ("                                            CAS Latency  = 4.0");
                        end else begin
                            $display ("                                            CAS Latency not supported");
                        end
                        
                        // Burst Length
                        if (Addr[2 : 0] === 3'b001) begin
                            $display ("                                            Burst Length = 2");
                        end else if (Addr[2 : 0] === 3'b010) begin
                            $display ("                                            Burst Length = 4");
                        end else if (Addr[2 : 0] === 3'b011) begin
                            $display ("                                            Burst Length = 8");
                        end else if (Addr[2 : 0] === 3'b111) begin
                            $display ("                                            Burst Length = Full Page");
                        end else begin
                            $display ("                                            Burst Length not supported");
                        end
                        
                        // Burst Type
                        if (Addr[3] === 1'b0) begin
                            $display ("                                            Burst Type   = Sequential");
                        end else begin
                            $display ("                                            Burst Type   = Interleaved");
                        end
                        
                        // DLL Reset
                        if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
                            DLL_reset = 1'b1;
                            DLL_done = 1'b0;
                            DLL_count = 0;
                        end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
                            $display ("%m : at time %t ERROR: DLL ENABLE in EMR.  DLL RESET is required.", $realtime);
                        end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
                            $display ("%m : at time %t ERROR: DLL DISABLE in EMR.  DLL RESET will be ignored.", $realtime);
                        end
                    end
                end else begin
                    $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
                end

                // Precharge to LMR
                if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
                    ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
                    $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
                end

                // LMR/EMR to LMR/EMR
                if ($realtime - MRD_chk < tMRD) begin
                    $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
                end

                // Record current tMRD time
                MRD_chk = $realtime;
            end

            // Activate Block
            if (Active_enable === 1'b1) begin
                // Activate an open bank can corrupted.
                if ((Ba === 2'b00 && Pc_b0  === 1'b0) || (Ba === 2'b01 && Pc_b1  === 1'b0) ||
                    (Ba === 2'b10 && Pc_b2  === 1'b0) || (Ba === 2'b11 && Pc_b3  === 1'b0)) begin
                    $display ("%m : at time %t ERROR: Bank = %d is already activated (OPEN).", $realtime, Ba);
                end
                
                // Activate Bank 0
                if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
                    // Activate to Activate (same bank)
                    if ($realtime - RC_chk0 < tRC) begin
                        $display ("%m : at time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
                    end

                    // Precharge to Activate
                    if ($realtime - RP_chk0 < tRP) begin
                        $display ("%m : at time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
                    end

                    // Record variables for checking violation
                    Act_b0 = 1'b1;
                    Pc_b0 = 1'b0;
                    B0_row_addr = Addr [addr_bits - 1 : 0];
                    RC_chk0  = $realtime;
                    RCD_chk0 = $realtime;
                    RAS_chk0 = $realtime;
                    RAP_chk0 = $realtime;
                end

                // Activate Bank 1
                if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
                    // Activate to Activate (same bank)
                    if ($realtime - RC_chk1 < tRC) begin
                        $display ("%m : at time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
                    end

                    // Precharge to Activate
                    if ($realtime - RP_chk1 < tRP) begin
                        $display ("%m : at time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
                    end

                    // Record variables for checking violation
                    Act_b1 = 1'b1;
                    Pc_b1 = 1'b0;
                    B1_row_addr = Addr [addr_bits - 1 : 0];
                    RC_chk1  = $realtime;
                    RCD_chk1 = $realtime;
                    RAS_chk1 = $realtime;
                    RAP_chk1 = $realtime;
                end

                // Activate Bank 2
                if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
                    // Activate to Activate (same bank)
                    if ($realtime - RC_chk2 < tRC) begin
                        $display ("%m : at time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
                    end

                    // Precharge to Activate
                    if ($realtime - RP_chk2 < tRP) begin
                        $display ("%m : at time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
                    end

                    // Record variables for checking violation
                    Act_b2 = 1'b1;
                    Pc_b2 = 1'b0;
                    B2_row_addr = Addr [addr_bits - 1 : 0];
                    RC_chk2  = $realtime;
                    RCD_chk2 = $realtime;
                    RAS_chk2 = $realtime;
                    RAP_chk2 = $realtime;
                end

                // Activate Bank 3
                if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
                    // Activate to Activate (same bank)
                    if ($realtime - RC_chk3 < tRC) begin
                        $display ("%m : at time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
                    end

                    // Precharge to Activate
                    if ($realtime - RP_chk3 < tRP) begin
                        $display ("%m : at time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
                    end

                    // Record variables for checking violation
                    Act_b3 = 1'b1;
                    Pc_b3 = 1'b0;
                    B3_row_addr = Addr [addr_bits - 1 : 0];
                    RC_chk3  = $realtime;
                    RCD_chk3 = $realtime;
                    RAS_chk3 = $realtime;
                    RAP_chk3 = $realtime;
                end

                // Display Debug Message
                if (Debug) begin
                    $display ("%m : at time %t ACT  : Bank = %d Row = %d", $realtime, Ba, Addr);
                end
                
                // Activate to Activate (different bank)
                if ((Previous_bank != Ba) && ($realtime - RRD_chk < tRRD)) begin
                    $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba);
                end
                
                // AutoRefresh to Activate
                if ($realtime - RFC_chk < tRFC) begin
                    $display ("%m : at time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba);
                end

                // Record variable for checking violation
                RRD_chk = $realtime;
                Previous_bank = Ba;
            end
        
            // Precharge Block - consider NOP if bank already precharged or in process of precharging
            if (Prech_enable === 1'b1) begin
                // Display Debug Message
                if (Debug) begin
                    $display ("%m : at time %t PRE  : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                end

                // EMR or LMR to Precharge
                if ($realtime - MRD_chk < tMRD) begin
                    $display ("%m : at time %t ERROR: tMRD violation during Precharge", $realtime);
                end

                // Precharge bank 0
                if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
                    Act_b0 = 1'b0;
                    Pc_b0 = 1'b1;
                    RP_chk0 = $realtime;
                    
                    // Activate to Precharge Bank
                    if ($realtime - RAS_chk0 < tRAS) begin
                        $display ("%m : at time %t ERROR: tRAS violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                    
                    // tWR violation check for Write
                    if ($realtime - WR_chk0 < tWR) begin
                        $display ("%m : at time %t ERROR: tWR violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                end

                // Precharge bank 1
                if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
                    Act_b1 = 1'b0;
                    Pc_b1 = 1'b1;
                    RP_chk1 = $realtime;

                    // Activate to Precharge Bank 1
                    if ($realtime - RAS_chk1 < tRAS) begin
                        $display ("%m : at time %t ERROR: tRAS violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                    
                    // tWR violation check for Write
                    if ($realtime - WR_chk1 < tWR) begin
                        $display ("%m : at time %t ERROR: tWR violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                end

                // Precharge bank 2
                if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
                    Act_b2 = 1'b0;
                    Pc_b2 = 1'b1;
                    RP_chk2 = $realtime;
                    
                    // Activate to Precharge Bank 2
                    if ($realtime - RAS_chk2 < tRAS) begin
                        $display ("%m : at time %t ERROR: tRAS violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                    
                    // tWR violation check for Write
                    if ($realtime - WR_chk2 < tWR) begin
                        $display ("%m : at time %t ERROR: tWR violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                end

                // Precharge bank 3
                if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
                    Act_b3 = 1'b0;
                    Pc_b3 = 1'b1;
                    RP_chk3 = $realtime;
                    
                    // Activate to Precharge Bank 3
                    if ($realtime - RAS_chk3 < tRAS) begin
                        $display ("%m : at time %t ERROR: tRAS violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                    
                    // tWR violation check for Write
                    if ($realtime - WR_chk3 < tWR) begin
                        $display ("%m : at time %t ERROR: tWR violation during Precharge : Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
                    end
                end

                // Terminate a WRITE immediately (if same bank or all banks)
                if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
                    Data_in_enable = 1'b0;
                end
                
                // Precharge Command Pipeline for READ
                if (Cas_latency_15 === 1'b1) begin
                    Command[3] = `PRECH;
                    Bank_precharge[3] = Ba;
                    A10_precharge[3] = Addr[10];
                end else if (Cas_latency_2 === 1'b1) begin
                    Command[4] = `PRECH;
                    Bank_precharge[4] = Ba;
                    A10_precharge[4] = Addr[10];
                end else if (Cas_latency_25 === 1'b1) begin
                    Command[5] = `PRECH;
                    Bank_precharge[5] = Ba;
                    A10_precharge[5] = Addr[10];
                end else if (Cas_latency_3 === 1'b1) begin
                    Command[6] = `PRECH;
                    Bank_precharge[6] = Ba;
                    A10_precharge[6] = Addr[10];
                end else if (Cas_latency_4 === 1'b1) begin
                    Command[8] = `PRECH;
                    Bank_precharge[8] = Ba;
                    A10_precharge[8] = Addr[10];
                end
            end
        
            // Burst terminate
            if (Burst_term === 1'b1) begin
                // Burst Terminate Command Pipeline for Read
                if (Cas_latency_15 === 1'b1) begin
                    Command[3] = `BST;
                end else if (Cas_latency_2 === 1'b1) begin
                    Command[4] = `BST;
                end else if (Cas_latency_25 === 1'b1) begin
                    Command[5] = `BST;
                end else if (Cas_latency_3 === 1'b1) begin
                    Command[6] = `BST;
                end else if (Cas_latency_4 === 1'b1) begin
                    Command[8] = `BST;
                end

                // Display Debug Message
                if (Debug) begin
                    $display ("%m : at time %t BST  : Burst Terminate",$realtime);
                end

                // Illegal to burst terminate a Write
                if (Data_in_enable === 1'b1) begin
                    $display ("%m : at time %t ERROR: It's illegal to burst terminate a Write", $realtime);
                end
                
                // Illegal to burst terminate a Read with Auto Precharge
                if (Data_out_enable === 1'b1 && Read_precharge[Bank] === 1'b1) begin
                    $display ("%m : at time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime);
                end
            end
            
            // Read, Write, Column Latch
            if (Read_enable === 1'b1 || Write_enable === 1'b1) begin
                // Check to see if bank is open (ACT)
                if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
                    (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
                    $display("%m : at time %t ERROR: Cannot Read or Write - Bank = %d is not Activated", $realtime, Ba);
                end

                // Read/Write interrupt a Read/Write with Auto Precharge
                if ((Auto_precharge[0] === 1'b1 && (Read_precharge[0] === 1'b1 || Write_precharge[0] === 1'b1) && Ba === 2'b00) ||
                    (Auto_precharge[1] === 1'b1 && (Read_precharge[1] === 1'b1 || Write_precharge[1] === 1'b1) && Ba === 2'b01) ||
                    (Auto_precharge[2] === 1'b1 && (Read_precharge[2] === 1'b1 || Write_precharge[2] === 1'b1) && Ba === 2'b10) ||
                    (Auto_precharge[3] === 1'b1 && (Read_precharge[3] === 1'b1 || Write_precharge[3] === 1'b1) && Ba === 2'b11)) begin
                    $display ("%m : at time %t ERROR: It's illegal to interrupt a Read or Write with Auto Precharge", $realtime);
                end

                // Read Command
                if (Read_enable === 1'b1) begin
                    // CAS Latency pipeline
                    if (Cas_latency_15 === 1'b1) begin
                        if (Addr[10] === 1'b1) begin
                            Command[3] = `READ_A;
                        end else begin
                            Command[3] = `READ;
                        end
                        Col_addr[3] = Addr;
                        Bank_addr[3] = Ba;
                        Burst_dir_pipe [3] = Burst_length_f & Addr [0];
                    end else if (Cas_latency_2 === 1'b1) begin
                        if (Addr[10] === 1'b1) begin
                            Command[4] = `READ_A;
                        end else begin
                            Command[4] = `READ;
                        end
                        Col_addr[4] = Addr;
                        Bank_addr[4] = Ba;
                        Burst_dir_pipe [4] = Burst_length_f & Addr [0];
                    end else if (Cas_latency_25 === 1'b1) begin
                        if (Addr[10] === 1'b1) begin
                            Command[5] = `READ_A;
                        end else begin
                            Command[5] = `READ;
                        end
                        Col_addr[5] = Addr;
                        Bank_addr[5] = Ba;
                        Burst_dir_pipe [5] = Burst_length_f & Addr [0];
                    end else if (Cas_latency_3 === 1'b1) begin
                        if (Addr[10] === 1'b1) begin
                            Command[6] = `READ_A;
                        end else begin
                            Command[6] = `READ;
                        end
                        Col_addr[6] = Addr;
                        Bank_addr[6] = Ba;
                        Burst_dir_pipe [6] = Burst_length_f & Addr [0];
                    end else if (Cas_latency_4 === 1'b1) begin
                        if (Addr[10] === 1'b1) begin
                            Command[8] = `READ_A;
                        end else begin
                            Command[8] = `READ;
                        end
                        Col_addr[8] = Addr;
                        Bank_addr[8] = Ba;
                        Burst_dir_pipe [8] = Burst_length_f & Addr [0];
                    end

                    // Check for DLL reset before Read
                    if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
                        $display ("%m : at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable (%0d / 200).", $realtime, DLL_count);
                    end

                    // Activate to Read without Auto Precharge
                    if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) ||
                        (Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) ||
                        (Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) ||
                        (Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin
                        $display("%m : at time %t ERROR: tRCD violation during Read to Bank %d", $realtime, Ba);
                    end

                    // Activate to Read with Auto Precharge
                    if ((Addr [10] === 1'b1 && Ba === 2'b00 && $realtime - RAP_chk0 < tRAP) ||
                        (Addr [10] === 1'b1 && Ba === 2'b01 && $realtime - RAP_chk1 < tRAP) ||
                        (Addr [10] === 1'b1 && Ba === 2'b10 && $realtime - RAP_chk2 < tRAP) ||
                        (Addr [10] === 1'b1 && Ba === 2'b11 && $realtime - RAP_chk3 < tRAP)) begin
                        $display ("%m : at time %t ERROR: tRAP violation during Read to Bank %d", $realtime, Ba);
                    end

                    // Terminate a Write
                    if (Data_in_enable === 1'b1) begin
                        Data_in_enable = 1'b0;
                    end

                // Write Command
                end else if (Write_enable === 1'b1) begin
                    // Write Latency pipeline
                    if (Addr[10] === 1'b1) begin
                        Command[2] = `WRITE_A;
                    end else begin
                        Command[2] = `WRITE;
                    end
                    Col_addr[2] = Addr;
                    Bank_addr[2] = Ba;
                    Burst_dir_pipe [2] = Burst_length_f & Addr [0];

                    // Activate to Write
                    if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) ||
                        (Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) ||
                        (Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) ||
                        (Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin
                        $display("%m : at time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba);
                    end
                end

                // Read or Write with Auto Precharge
                if (Addr[10] === 1'b1) begin
                    Auto_precharge [Ba]= 1'b1;
                    Count_precharge [Ba]= 0;
                    if (Read_enable === 1'b1) begin
                        Read_precharge[Ba] = 1'b1;
                    end else if (Write_enable === 1'b1) begin
                        Write_precharge[Ba] = 1'b1;
                    end
                end
            end

            //  Read with Auto Precharge Calculation
            //      The device start internal precharge:
            //          1.  BL/2 cycles after command
            //          2.  Meet minimum tRAS requirement
            if ((Auto_precharge[0] === 1'b1) && (Read_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[0] >= 1) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[0] >= 2) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[0] >= 4)) begin
                    Pc_b0 = 1'b1;
                    Act_b0 = 1'b0;
                    RP_chk0 = $realtime;
                    Auto_precharge[0] = 1'b0;
                    Read_precharge[0] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $realtime);
                    end
                end
            end
            if ((Auto_precharge[1] === 1'b1) && (Read_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[1] >= 1) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[1] >= 2) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[1] >= 4)) begin
                    Pc_b1 = 1'b1;
                    Act_b1 = 1'b0;
                    RP_chk1 = $realtime;
                    Auto_precharge[1] = 1'b0;
                    Read_precharge[1] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $realtime);
                    end
                end
            end
            if ((Auto_precharge[2] === 1'b1) && (Read_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[2] >= 1) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[2] >= 2) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[2] >= 4)) begin
                    Pc_b2 = 1'b1;
                    Act_b2 = 1'b0;
                    RP_chk2 = $realtime;
                    Auto_precharge[2] = 1'b0;
                    Read_precharge[2] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $realtime);
                    end
                end
            end
            if ((Auto_precharge[3] === 1'b1) && (Read_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[3] >= 1) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[3] >= 2) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[3] >= 4)) begin
                    Pc_b3 = 1'b1;
                    Act_b3 = 1'b0;
                    RP_chk3 = $realtime;
                    Auto_precharge[3] = 1'b0;
                    Read_precharge[3] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $realtime);
                    end
                end
            end

            //  Write with Auto Precharge Calculation
            //      The device start internal precharge
            //          1.  Two Clock after last burst
            //          2.  Meet minimum tRAS requirement
            //  Since tWR is time base, the model will dynamically calculate tRP
            if ((Auto_precharge[0] === 1'b1) && (Write_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[0] >= 4) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[0] >= 5) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[0] >= 7)) begin
                    Pc_b0 = 1'b1;
                    Act_b0 = 1'b0;
                    RP_chk0 = $realtime - ((2 * tCK) - tWR);
                    Auto_precharge[0] = 1'b0;
                    Write_precharge[0] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $realtime);
                    end
                end
            end
            if ((Auto_precharge[1] === 1'b1) && (Write_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[1] >= 4) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[1] >= 5) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[1] >= 7)) begin
                    Pc_b1 = 1'b1;
                    Act_b1 = 1'b0;
                    RP_chk1 = $realtime - ((2 * tCK) - tWR);
                    Auto_precharge[1] = 1'b0;
                    Write_precharge[1] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $realtime);
                    end
                end
            end
            if ((Auto_precharge[2] === 1'b1) && (Write_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[2] >= 4) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[2] >= 5) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[2] >= 7)) begin
                    Pc_b2 = 1'b1;
                    Act_b2 = 1'b0;
                    RP_chk2 = $realtime - ((2 * tCK) - tWR);
                    Auto_precharge[2] = 1'b0;
                    Write_precharge[2] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $realtime);
                    end
                end
            end
            if ((Auto_precharge[3] === 1'b1) && (Write_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin
                if ((Burst_length_2 === 1'b1 && Count_precharge[3] >= 4) || 
                    (Burst_length_4 === 1'b1 && Count_precharge[3] >= 5) ||
                    (Burst_length_8 === 1'b1 && Count_precharge[3] >= 7)) begin
                    Pc_b3 = 1'b1;
                    Act_b3 = 1'b0;
                    RP_chk3 = $realtime - ((2 * tCK) - tWR);
                    Auto_precharge[3] = 1'b0;
                    Write_precharge[3] = 1'b0;
                    if (Debug) begin
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $realtime);
                    end
                end
            end
        end

        // Internal Precharge or Bst
        if (Command[0] === `PRECH) begin                            // Precharge terminate a read with same bank or all banks
            if (Bank_precharge[0] === Bank || A10_precharge[0] === 1'b1) begin
                if (Data_out_enable === 1'b1) begin
                    Dqs_out = 2'bzz;
                    Data_out_enable = 1'b0;
                end
            end
        end else if (Command[0] === `BST) begin                     // BST terminate a read to current bank
            if (Data_out_enable === 1'b1) begin
                Dqs_out = 2'bzz;
                Data_out_enable = 1'b0;
            end
        end

        // Delay for Dqs to go HiZ then accept new internal Dqs
        #0.001;

        // Dqs Generator
        if (Data_out_enable === 1'b1) begin
            Dqs_int = 2'b00;
            if (Dqs_out === 2'b00) begin
                Dqs_out = 2'b11;
            end else if (Dqs_out === 2'b11) begin
                Dqs_out = 2'b00;
            end else begin
                Dqs_out = 2'b00;
            end
        end else if (Data_out_enable === 1'b0 && Dqs_int === 2'b00) begin
            Dqs_out = 2'bzz;
            Dq_out = {data_bits{1'bz}};
        end

        // Delay for Dqs to go HiZ then accept new Read or Write
        #0.001;

        // Internal Dqs
        if (Command[2] === `READ || Command[2] === `READ_A) begin
            if ((Dqs_out !== 2'b00 || Dqs_out !== 2'b11) && (Data_out_enable === 1'b0)) begin
                Dqs_out = 2'b00;
                Dqs_int = 2'b11;
            end
        end else if (Command[2] === `WRITE || Command[2] === `WRITE_A) begin
            Dqs_out = 2'bzz;
        end

        // Detect Read or Write command (work with any DSS)
        Rw_command = Command[1];
    end

    // Latch address for Read or Write
    task Latch_address;
        begin
            Bank_dqs = Bank_addr[1];
            Col_dqs  = Col_addr[1];
            Col_brst_dqs = Col_addr[1];
            Burst_dir_dqs = Burst_dir_pipe[1];
            if (Bank_addr[1] === 2'b00) begin
                Row_dqs = B0_row_addr;
            end else if (Bank_addr[1] === 2'b01) begin
                Row_dqs = B1_row_addr;
            end else if (Bank_addr[1] === 2'b10) begin
                Row_dqs = B2_row_addr;
            end else if (Bank_addr[1] === 2'b11) begin
                Row_dqs = B3_row_addr;
            end
        end
    endtask

    // Read or Write command waiting for posedge DQS
    always @ (Rw_command) begin
        if (Rw_command === `READ || Rw_command === `READ_A) begin
            Latch_address;
            @ (Sys_clk);
            Bank = Bank_dqs;
            Row = Row_dqs;
            Col = Col_dqs;
            Col_brst = Col_brst_dqs;
            Burst_dir = Burst_dir_dqs;
            Burst_counter = 0;
            Data_in_enable = 1'b0;
            Data_out_enable = 1'b1;
        end else if (Rw_command === `WRITE || Rw_command === `WRITE_A) begin
            Latch_address;
            @ (posedge Dqs);
            Bank = Bank_dqs;
            Row = Row_dqs;
            Col = Col_dqs;
            Col_brst = Col_brst_dqs;
            Burst_dir = Burst_dir_dqs;
            Burst_counter = 0;
            Data_in_enable = 1'b1;
            Data_out_enable = 1'b0;
        end
    end

    // DQS buffer (Driver/Receiver)
    always @ (Dqs_rec) begin
        #0.001;                                                     // Delay to avoid race condition with Rw_command
        // DM latch for tWR calculation (DM interrupt cases)
        if (Dqs_rec === 1'b1) begin
            Dm_high = Dm;
        end else begin
            Dm_pipe = {Bank, Data_in_enable, Dm_high, Dm};
        end
        // Read or Write
        if (Data_in_enable === 1'b1) begin                          // Writing Data to Memory
            // Array buffer
            if (Bank === 2'b00) begin
                Dq_dm [data_bits - 1 : 0] = Bank0 [{Row, Col}];
            end
            if (Bank === 2'b01) begin
                Dq_dm [data_bits - 1 : 0] = Bank1 [{Row, Col}];
            end
            if (Bank === 2'b10) begin
                Dq_dm [data_bits - 1 : 0] = Bank2 [{Row, Col}];
            end
            if (Bank === 2'b11) begin
                Dq_dm [data_bits - 1 : 0] = Bank3 [{Row, Col}];
            end
            // Dqm operation
            if (Dm[0] === 1'b0) begin
                Dq_dm [ 7 : 0] = Dq [ 7 : 0];
            end
            if (Dm[1] === 1'b0) begin
                Dq_dm [15 : 8] = Dq [15 : 8];
            end
            // Write to memory
            if (Bank === 2'b00) begin
                Bank0 [{Row, Col}] = Dq_dm [data_bits - 1 : 0];
            end
            if (Bank === 2'b01) begin
                Bank1 [{Row, Col}] = Dq_dm [data_bits - 1 : 0];
            end
            if (Bank === 2'b10) begin
                Bank2 [{Row, Col}] = Dq_dm [data_bits - 1 : 0];
            end
            if (Bank === 2'b11) begin
                Bank3 [{Row, Col}] = Dq_dm [data_bits - 1 : 0];
            end
            // Output result
            if (Debug === 1'b1 && Dm !== 2'b11) begin
                $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $realtime, Bank, Row, Col, Dq_dm);
            end
            // Advance burst counter subroutine
            Burst;
        end else if (Data_out_enable === 1'b1) begin                // Reading Data from Memory
            if (Bank === 2'b00) begin
                Dq_out [data_bits - 1 : 0] = Bank0[{Row, Col}];
            end
            if (Bank === 2'b01) begin
                Dq_out [data_bits - 1 : 0] = Bank1[{Row, Col}];
            end
            if (Bank === 2'b10) begin
                Dq_out [data_bits - 1 : 0] = Bank2[{Row, Col}];
            end
            if (Bank === 2'b11) begin
                Dq_out [data_bits - 1 : 0] = Bank3[{Row, Col}];
            end
            if (Debug) begin
                $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $realtime, Bank, Row, Col, Dq_out);
            end
            Burst;
        end else begin
            Dq_out [data_bits - 1 : 0] = {data_bits{1'bz}};
        end
    end

    // Burst Calculation
    task Burst;
        begin
            // Advance Burst Counter
            Burst_counter = Burst_counter + 1;

            // Burst Type
            if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst
                if (Burst_dir === 1'b0) begin
                    Col_temp = Col + 1;
                end else begin
                    Col_temp = Col - 1;
                end
            end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst
                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
            end
            
            // Burst Length
            if (Burst_length_2) begin                               // Burst Length = 2
                Col [0] = Col_temp [0];
            end else if (Burst_length_4) begin                      // Burst Length = 4
                Col [1 : 0] = Col_temp [1 : 0];
            end else if (Burst_length_8) begin                      // Burst Length = 8
                Col [2 : 0] = Col_temp [2 : 0];
            end else begin                                          // Burst Length = FULL
                Col = Col_temp;
            end
            
            // Data Counter
            if (Burst_length_2 === 1'b1) begin
                if (Burst_counter >= 2) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_4 === 1'b1) begin
                if (Burst_counter >= 4) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_8 === 1'b1) begin
                if (Burst_counter >= 8) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end
        end
    endtask

    // Timing Check for -7 (CAS Latency = 2)
    specify
        specparam
                    tKC =  7.500,       // tCK already declared so I use tKC instead :)
                    tCH =  3.375,       // 0.45 * tCK
                    tCL =  3.375,       // 0.45 * tCK
                    tDH =  0.500,
                    tDS =  0.500,
                    tIH =  0.900,
                    tIS =  0.900;
        $width    (posedge Clk,          tCH     );
        $width    (negedge Clk,          tCL     );
        $period   (negedge Clk,          tKC     );
        $period   (posedge Clk,          tKC     );
        $setuphold(posedge Clk,   Cke,   tIS, tIH);
        $setuphold(posedge Clk,   Cs_n,  tIS, tIH);
        $setuphold(posedge Clk,   Cas_n, tIS, tIH);
        $setuphold(posedge Clk,   Ras_n, tIS, tIH);
        $setuphold(posedge Clk,   We_n,  tIS, tIH);
        $setuphold(posedge Clk,   Addr,  tIS, tIH);
        $setuphold(posedge Clk,   Ba,    tIS, tIH);
        $setuphold(posedge Dq_in, Dq,    tDS, tDH);
        $setuphold(negedge Dq_in, Dq,    tDS, tDH);
        $setuphold(posedge Dq_in, Dm,    tDS, tDH);
        $setuphold(negedge Dq_in, Dm,    tDS, tDH);
    endspecify

endmodule