// VERSION:1.00 DATE:2002/06/04 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TBGTSMLAHORPCLX2 (
    // -------------------------- output
    N01, N02,
    // -------------------------- input
    H01, H02, H03
);
    output N01;
    output N02;
    input H01;
    input H02;
    input H03;

    reg notifier;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H03, H03 );

    or ( _G001, _H03, _H01 );
    DLSFQ ( _G002, _G001, _H02, 1'b1, 1'b1, notifier );
    not ( _G002B, _G002 );
    or ( N01, _G002B, _H02 );
    buf ( N02, _H01 );

    specify
        specparam DMY_SPC=1:1:1;

        $setup ( posedge H01, negedge H02, DMY_SPC, notifier );
        $setup ( negedge H01, negedge H02, DMY_SPC, notifier );
        $hold ( negedge H02, posedge H01, DMY_SPC, notifier );
        $hold ( negedge H02, negedge H01, DMY_SPC, notifier );

        $setup ( posedge H03, negedge H02, DMY_SPC, notifier );
        $setup ( negedge H03, negedge H02, DMY_SPC, notifier );
        $hold ( negedge H02, posedge H03, DMY_SPC, notifier );
        $hold ( negedge H02, negedge H03, DMY_SPC, notifier );

        $width ( posedge H02, DMY_SPC, 0, notifier );

        ( H01 *> N02 ) = ( DMY_SPC, DMY_SPC );
        ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );

    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine