// VERSION:1.00 DATE:2001/10/12 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDBIAAG3NNX2 ( N01, N02, H01, H02, H04 );
    input  H01;
    input  H02;
    input  H04;
    inout  N01;
    output N02;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H04, H04 );
    bufif1 ( _G001, _H01, _H02 );
    bufif1 ( N01, _G001, _H02 );
    not ( _G002, N01 );
    nand ( N02, _G002, _H04 );

    specify
        specparam DMY_SPC=1:1:1;

        ( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H02 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
	( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
        ( H04 *> N02 ) = ( DMY_SPC, DMY_SPC );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine