TDBIAC33DL12S.v
999 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIAC33DL12S ( N01, N02, H02, H03 );
input H02;
input H03;
inout N01;
output N02;
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( N02, N01 );
bufif1 ( _G001, _H02, _H03 );
bufif1 ( _G002, _G001, _H03 );
nmos ( _G002, N01_int, _G003 );
nmos ( N01, _G002, 1'b1 );
udp2down ( _G003, _H03, _G004 );
buf #1( _G004, N01 );
pulldown ( N01_int );
specify
specparam DMY_SPC=1;
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine