// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDBIAC33NN12S ( N01, N02, H02, H03 );
    input  H02;
    input  H03;
    inout N01;
    output N02;

    buf ( _H02, H02 );
    buf ( _H03, H03 );
    bufif1 ( _G001, _H02, _H03 );
    bufif1 ( N01, _G001, _H03 );
    buf ( N02, N01 );

    specify
        specparam DMY_SPC=1;

        ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H03 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
        ( N01 *> N02 ) = ( DMY_SPC, DMY_SPC ); 
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine