TDBIADIMNN17.v
1.03 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
// VERSION:1.00 DATE:2001/09/11 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIADIMNN17 ( N01, N02, H01, H03, H04, H05, H06 );
input H01;
input H03;
input H04;
input H05;
input H06;
inout N01;
output N02;
buf ( _H01, H01 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
not ( _H04N, _H04 );
not ( _H05N, _H05 );
nor ( _G001, _H04N, _H05N, _H06 );
bufif1 ( _G005, _H03, _G001 );
bufif1 ( _G006, _G005, _G001 );
buf ( _G007, _G006 );
bufif1 ( _G008, _H01, _G007 );
bufif1 ( N01, _G008, _G007 );
buf ( N02, N01 );
specify
specparam DMY_SPC=1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine