// VERSION:1.00 DATE:2002/06/03 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module THIPALVDN ( N01, H01, H02, H03 );
    output N01;
    input H01, H02, H03;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H03, H03 );
    udp_PECL u1 ( _G001, _H01, _H02 );
    not ( _G002, _H03 );
    or ( N01, _G001, _G002 );

    defparam u1.PECL_DLY = 101;
    wire flag_PECL = u1.flag_PECL;

    specify
      specparam DMY_SPC = 1:1:1;

      if ( !flag_PECL )
        ( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
      if ( !flag_PECL )
        ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine