TDSECCOX2.v
908 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
// VERSION:1.00 DATE:00/09/20 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSECCOX2 ( N01, H01, H02, H03 );
input H01;
input H02;
input H03;
output N01;
buf ( _H01, H01 );
not ( _G001, _H01 );
buf ( _H02, H02 );
not ( _G002, _H02 );
buf ( _H03, H03 );
not ( _G003, _H03 );
and ( _G010, _G001, _G002 );
and ( _G011, _G001, _G003 );
and ( _G012, _G002, _H03 );
nor ( N01, _G010, _G011, _G012 );
specify
specparam DMY_SPC=1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine