TDSEDFLQRSBX2.v
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// VERSION:1.00 DATE:00/09/20 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSEDFLQRSBX2 ( N01, N02, H01, H02, H03, H04, H05, H06, H07 );
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
input H07;
output N01;
output N02;
reg notif_lssd;
reg notifier;
reg notifier_all;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
buf ( _H07, H07 );
not ( _H02B, _H02 );
not ( _H07B, _H07 );
not ( _C001, _H02B );
not ( _SIN01, _H05 );
and ( _C003, _H02B, _H07B );
LSSD opc_lssd ( _C002, _D001, _H01, _SIN01, _C001, _H06,
notif_lssd, 1'b1 );
DLSFQ_LSSD2 opc_dlsf_lssd ( _D002, _H04, _H03, _C002, _D001,
notif_lssd, 1'b1 );
DLSFQ ( _G001, _D002, _C003, _H03, _H04, notifier );
DLSFQB ( _G001N, _D002, _C003, _H03, _H04, notifier );
buf (N01, _G001);
buf (N02, _G001N);
// timing check flag
wire docheck1 = ( _H03 !== 1'b0 && _H04 !== 1'b0 && _H02B !== 1'b0 );
wire docheck2 = ( _H03 !== 1'b0 && _H04 !== 1'b0 && _H06 !== 1'b1 );
wire docheck3 = ( _H04 !== 1'b0 && _H02B !== 1'b0 );
wire docheck4 = ( _H03 !== 1'b0 && _H02B !== 1'b0 );
wire docheck5 = ( _H03 !== 1'b0 && _H06 !== 1'b1 );
wire docheck6 = ( _H04 !== 1'b0 && _H06 !== 1'b1 );
wire docheck7 = ( _H03 !== 1'b0 && _H04 !== 1'b0 && _H07B !== 1'b0 );
wire docheck8 = ( _H04 !== 1'b0 && ( _H02B !== 1'b1 || _H06 !== 1'b1 || _H07B !== 1'b1 ) );
wire docheck9 = ( _H03 !== 1'b0 && ( _H02B !== 1'b1 || _H06 !== 1'b1 || _H07B !== 1'b1 ) );
initial //initialize data flags
begin
notif_lssd = 0;
notifier = 0;
end
always @( notifier_all )
begin
if ( _H02B !== 1'b0 && _H06 !== 1'b1 ) notif_lssd = !notif_lssd;
notifier = !notifier;
end
specify
specparam DMY_SPC=1;
specparam DMY_SPC2=1:1:1;
$setup ( posedge H01, negedge H02 &&& docheck2, DMY_SPC, notif_lssd );
$setup ( negedge H01, negedge H02 &&& docheck2, DMY_SPC, notif_lssd );
$hold ( negedge H02, posedge H01 &&& docheck2, DMY_SPC, notif_lssd );
$hold ( negedge H02, negedge H01 &&& docheck2, DMY_SPC, notif_lssd );
$setup ( posedge H03, negedge H02 &&& docheck6, DMY_SPC, notif_lssd );
$hold ( negedge H02, posedge H03 &&& docheck6, DMY_SPC, notif_lssd );
$setup ( posedge H04, negedge H02 &&& docheck5, DMY_SPC, notif_lssd );
$hold ( negedge H02, posedge H04 &&& docheck5, DMY_SPC, notif_lssd );
$setup ( posedge H05, negedge H06 &&& docheck1, DMY_SPC, notif_lssd );
$setup ( negedge H05, negedge H06 &&& docheck1, DMY_SPC, notif_lssd );
$hold ( negedge H06, posedge H05 &&& docheck1, DMY_SPC, notif_lssd );
$hold ( negedge H06, negedge H05 &&& docheck1, DMY_SPC, notif_lssd );
$setup ( posedge H03, negedge H06 &&& docheck3, DMY_SPC, notif_lssd );
$hold ( negedge H06, posedge H03 &&& docheck3, DMY_SPC, notif_lssd );
$setup ( posedge H04, negedge H06 &&& docheck4, DMY_SPC, notif_lssd );
$hold ( negedge H06, posedge H04 &&& docheck4, DMY_SPC, notif_lssd );
$width ( posedge H02 &&& docheck2, DMY_SPC, 0, notif_lssd );
$width ( negedge H02 &&& docheck7, DMY_SPC, 0, notifier );
$width ( negedge H03 &&& docheck8, DMY_SPC, 0, notifier_all );
$width ( negedge H04 &&& docheck9, DMY_SPC, 0, notifier_all );
$width ( posedge H06 &&& docheck1, DMY_SPC, 0, notif_lssd );
$width ( negedge H07 &&& docheck1, DMY_SPC, 0, notifier );
( H02 => N01 ) = ( DMY_SPC, DMY_SPC );
( H02 => N02 ) = ( DMY_SPC, DMY_SPC );
( H03 => N01 ) = ( DMY_SPC2, DMY_SPC );
( H03 => N02 ) = ( DMY_SPC, DMY_SPC2 );
( H04 => N01 ) = ( DMY_SPC, DMY_SPC2 );
( H04 => N02 ) = ( DMY_SPC2, DMY_SPC );
( H05 => N01 ) = ( DMY_SPC2, DMY_SPC2 );
( H05 => N02 ) = ( DMY_SPC2, DMY_SPC2 );
( H06 => N01 ) = ( DMY_SPC2, DMY_SPC2 );
( H06 => N02 ) = ( DMY_SPC2, DMY_SPC2 );
( H07 => N01 ) = ( DMY_SPC, DMY_SPC );
( H07 => N02 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine