TBMUX4Y0.v
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// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBMUX4Y0 ( N01, H01, H02, H03, H04, H05, H06 );
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
output N01;
buf ( _H01, H01 );
not ( _G001, _H01 );
buf ( _H02, H02 );
not ( _G002, _H02 );
buf ( _H03, H03 );
not ( _G003, _H03 );
buf ( _H04, H04 );
not ( _G004, _H04 );
buf ( _H05, H05 );
not ( _G005, _H05 );
buf ( _H06, H06 );
not ( _G006, _H06 );
and ( _G010, _G001, _G002 );
and ( _G011, _G001, _G005 );
and ( _G012, _G002, _H05 );
or ( _G013, _G010, _G011, _G012 );
and ( _G014, _G003, _G004 );
and ( _G015, _G003, _G005 );
and ( _G016, _G004, _H05 );
or ( _G017, _G014, _G015, _G016 );
and ( _G018, _G013, _G017 );
and ( _G019, _G013, _G006 );
and ( _G020, _G017, _H06 );
nor ( N01, _G018, _G019, _G020 );
specify
specparam DMY_SPC=1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H04 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H05 )
( H05 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H05 )
( H05 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H06 )
( H06 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H06 )
( H06 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine