// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDDFLQYRBX1 ( N01, H01, H02, H03 );
    input H01;
    input H02;
    input H03;
    output N01;
    reg notifier;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H03, H03 );
    and ( _G001, _H01, _H03 );
    not ( _H02N, _H02 );
    buf ( N01, _G002 );
    DESFQ ( _G002, _G001, _H02N, 1'b1, 1'b1, notifier );

    wire docheck1 = ( _H03 !== 1'b0 );
    wire docheck2 = ( _H01 !== 1'b0 );

    specify
        specparam DMY_SPC = 1:1:1;

        $setup ( posedge H01, negedge H02 &&& docheck1, DMY_SPC, notifier );
        $setup ( negedge H01, negedge H02 &&& docheck1, DMY_SPC, notifier );
        $hold ( negedge H02, posedge H01 &&& docheck1, DMY_SPC, notifier );
        $hold ( negedge H02, negedge H01 &&& docheck1, DMY_SPC, notifier );
        $setup ( posedge H03, negedge H02 &&& docheck2, DMY_SPC, notifier );
        $setup ( negedge H03, negedge H02 &&& docheck2, DMY_SPC, notifier );
        $hold ( negedge H02, posedge H03 &&& docheck2, DMY_SPC, notifier );
        $hold ( negedge H02, negedge H03 &&& docheck2, DMY_SPC, notifier );

        $width ( posedge H02, DMY_SPC, 0, notifier );
        $width ( negedge H02, DMY_SPC, 0, notifier );

        ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );

    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine